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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : nova_defines.v
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// Generated : April 20,2008
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Global parameters of nova
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//BitStream_controller parameters
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//-------------------------------------------------------------------------------------------------
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//---Beha_BitStream_ram.v---
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`define Beha_Bitstream_ram_size 131071 //Beha_Bitstream_ram size
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//bitstream_gclk_gen
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//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame
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//1)50,000 cycles are not enough for foreman300,8th frame.So increase to 51,000 cycles
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//2)51,000 cycles are not enough for foreman300,11th frame.So increase to 51,500 cycles
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//3)51,500 cycles are not enough for foreman300,38th frame.So increase to 52,000 cycles
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//4)52,000 cycles are not enough for foreman300,66th frame.So increase to 52,500 cycles
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//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles
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//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles
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//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read,
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//the cycles required to decode each frame increased
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//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles
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//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles
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`define cycles_per_frame0 17'd45000
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`define cycles_per_frame1 17'd50000 //fast enough for akiyo300
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`define cycles_per_frame2 17'd57300 //preferred frequency for most critical sequence:foreman300
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`define cycles_per_frame3 17'd70000
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//---pc_decoding---
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`define rst_consumed_bits_sel 3'b000
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`define exp_golomb 3'b001
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`define fixed_length 3'b011
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`define dependent_variable 3'b010
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`define cavlc_consumed 3'b110
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`define trailing_bits 3'b111
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`define pcm_alignment 3'b101
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//---syntax_decoding---
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//mb_type_general
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`define MB_Inter16x16 4'b0000
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`define MB_Inter16x8 4'b0001
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`define MB_Inter8x16 4'b0010
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`define MB_P_8x8 4'b0011
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`define MB_P_8x8ref0 4'b0100
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`define MB_P_skip 4'b0101
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`define MB_I_PCM 4'b0110
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`define MB_type_reserved0 4'b0111
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`define MB_Intra16x16_CBPChroma0 4'b1000
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`define MB_Intra16x16_CBPChroma1 4'b1001
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`define MB_Intra16x16_CBPChroma2 4'b1010
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`define MB_type_reserved1 4'b1011
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`define MB_Intra4x4 4'b1100
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`define MB_type_reserved2 4'b1101
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`define MB_type_reserved3 4'b1110
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`define MB_type_rst 4'b1111
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//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg
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`define MB_addrA_addrB_Inter 2'b00
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`define MB_addrA_addrB_P_skip 2'b01
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`define MB_addrA_addrB_Intra16x16 2'b10
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`define MB_addrA_addrB_Intra4x4 2'b11
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//MBTypeGen_mbAddrD
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`define MB_addrD_Inter_P_skip 1'b0
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`define MB_addrD_Intra 1'b1
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//Gray-encoded FSM states to reduce power consumption during state switching
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`define rst_parser 2'b00
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`define start_code_prefix 2'b01
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`define nal_unit 2'b11
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`define rst_nal_unit 3'b000
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`define forbidden_zero_bit_2_nal_unit_type 3'b001
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`define slice_layer_non_IDR_rbsp 3'b011
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`define slice_layer_IDR_rbsp 3'b010
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`define seq_parameter_set_rbsp 3'b110
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`define pic_parameter_set_rbsp 3'b111
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`define rbsp_trailing_one_bit 3'b101
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`define rbsp_trailing_zero_bits 3'b100
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`define rst_slice_layer_wo_partitioning 2'b00
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`define slice_header 2'b01
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`define slice_data 2'b11
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`define rst_seq_parameter_set 4'b0000
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`define fixed_header 4'b0001
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`define level_idc_s 4'b0011
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`define seq_parameter_set_id_sps_s 4'b0010
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`define log2_max_frame_num_minus4_s 4'b0110
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`define pic_order_cnt_type_s 4'b0111
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`define log2_max_pic_order_cnt_lsb_minus4_s 4'b0101
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`define num_ref_frames_s 4'b0100
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`define gaps_in_frame_num_value_allowed_flag_s 4'b1100
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`define pic_width_in_mbs_minus1_s 4'b1101
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`define pic_height_in_map_units_minus1_s 4'b1111
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`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110
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`define vui_parameter_present_flag_s 4'b1010
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`define rst_pic_parameter_set 4'b0000
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`define pic_parameter_set_id_pps_s 4'b0001
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`define seq_parameter_set_id_pps_s 4'b0011
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`define entropy_coding_mode_flag_2_pic_order_present_flag 4'b0010
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`define num_slice_groups_minus1_s 4'b0110
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`define num_ref_idx_l0_active_minus1_pps_s 4'b0111
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`define num_ref_idx_l1_active_minus1_pps_s 4'b0101
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`define weighted_pred_flag_2_weighted_bipred_idc 4'b0100
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`define pic_init_qp_minus26_s 4'b1100
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`define pic_init_qs_minus26_s 4'b1101
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`define chroma_qp_index_offset_s 4'b1111
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`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110
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`define rst_slice_header 4'b0000
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`define first_mb_in_slice_s 4'b0001
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`define slice_type_s 4'b0011
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`define pic_parameter_set_id_slice_header_s 4'b0010
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`define frame_num_s 4'b0110
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`define idr_pic_id_s 4'b0111
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`define pic_order_cnt_lsb_s 4'b0101
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`define num_ref_idx_active_override_flag_s 4'b0100
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`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100
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`define ref_pic_list_reordering 4'b1101
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`define dec_ref_pic_marking 4'b1111
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`define slice_qp_delta_s 4'b1110
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`define disable_deblocking_filter_idc_s 4'b1010
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`define slice_alpha_c0_offset_div2_s 4'b1011
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`define slice_beta_offset_div2_s 4'b1001
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//ref_pic_list_reordering_state
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`define rst_ref_pic_list_reordering 3'b000
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`define ref_pic_list_reordering_flag_l0_s 3'b001
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//dec_ref_pic_marking_state
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`define rst_dec_ref_pic_marking 2'b00
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`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01
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`define adaptive_ref_pic_marking_mode_flag_s 2'b11
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`define rst_slice_data 4'b0000
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`define mb_skip_run_s 4'b0001
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`define skip_run_duration 4'b0011
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`define mb_type_s 4'b0010
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`define pcm_alignment_zero_bit_s 4'b0110
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`define pcm_byte_s 4'b0111
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`define sub_mb_pred 4'b0101
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`define mb_pred 4'b0100
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`define coded_block_pattern_s 4'b1100
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`define mb_qp_delta_s 4'b1101
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`define residual 4'b1111
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`define mb_num_update 4'b1110
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//mb_pred_state
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`define rst_mb_pred 3'b000
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`define prev_intra4x4_pred_mode_flag_s 3'b001
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`define rem_intra4x4_pred_mode_s 3'b011
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`define intra_chroma_pred_mode_s 3'b010
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`define ref_idx_l0_s 3'b110
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`define mvd_l0_s 3'b111
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//sub_mb_pred_state
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`define rst_sub_mb_pred 2'b00
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`define sub_mb_type_s 2'b01
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`define sub_ref_idx_l0_s 2'b11
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`define sub_mvd_l0_s 2'b10
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`define rst_residual 4'b0000
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`define Intra16x16DCLevel_s 4'b0001
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`define Intra16x16ACLevel_s 4'b0011
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`define Intra16x16ACLevel_0_s 4'b0010
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`define LumaLevel_s 4'b0110
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`define LumaLevel_0_s 4'b0111
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`define ChromaDCLevel_Cb_s 4'b0101
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`define ChromaDCLevel_Cr_s 4'b0100
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`define ChromaACLevel_Cb_s 4'b1100
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`define ChromaACLevel_Cr_s 4'b1101
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`define ChromaACLevel_0_s 4'b1110
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`define rst_cavlc_decoder 4'b0000
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`define nAnB_decoding_s 4'b0001
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`define nC_decoding_s 4'b0011
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`define NumCoeffTrailingOnes_LUT 4'b0010
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`define TrailingOnesSignFlag 4'b0110
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`define LevelPrefix 4'b0111
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`define LevelSuffix 4'b0101
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`define total_zeros_LUT 4'b0100
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`define run_before_LUT 4'b1100
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`define RunOfZeros 4'b1101
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`define LevelRunCombination 4'b1111
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//---LumaLevel_mbAddrB_RF---
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`define LumaLevel_mbAddrB_RF_data_width 20
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`define LumaLevel_mbAddrB_RF_data_depth 11
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//---ChromaLevel_Cb_mbAddrB_RF---
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`define ChromaLevel_Cb_mbAddrB_RF_data_width 10
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`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11
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//---ChromaLevel_Cr_mbAddrB_RF---
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`define ChromaLevel_Cr_mbAddrB_RF_data_width 10
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`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11
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//---Intra4x4_PredMode_RF---
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`define Intra4x4_PredMode_RF_data_width 16
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`define Intra4x4_PredMode_RF_data_depth 11
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//---mvx_mbAddrB_RF---
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`define mvx_mbAddrB_RF_data_width 32
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`define mvx_mbAddrB_RF_data_depth 11
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//---mvy_mbAddrB_RF---
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`define mvy_mbAddrB_RF_data_width 32
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`define mvy_mbAddrB_RF_data_depth 11
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//---mvx_mbAddrB_RF---
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`define mvx_mbAddrC_RF_data_width 8
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`define mvx_mbAddrC_RF_data_depth 10
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//---mvy_mbAddrB_RF---
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`define mvy_mbAddrC_RF_data_width 8
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`define mvy_mbAddrC_RF_data_depth 10
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//-------------------------------------------------------------------------------------------------
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//Intra prediction parameters
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//-------------------------------------------------------------------------------------------------
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//---Intra_mbAddrB_RAM---
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`define Intra_mbAddrB_RAM_data_width 32
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`define Intra_mbAddrB_RAM_data_depth 88
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//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl---
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`define Intra4x4_Vertical 4'b0000
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`define Intra4x4_Horizontal 4'b0001
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`define Intra4x4_DC 4'b0010
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`define Intra4x4_Diagonal_Down_Left 4'b0011
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`define Intra4x4_Diagonal_Down_Right 4'b0100
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`define Intra4x4_Vertical_Right 4'b0101
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`define Intra4x4_Horizontal_Down 4'b0110
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`define Intra4x4_Vertical_Left 4'b0111
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`define Intra4x4_Horizontal_Up 4'b1000
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`define Intra16x16_Vertical 2'b00
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`define Intra16x16_Horizontal 2'b01
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`define Intra16x16_DC 2'b10
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`define Intra16x16_Plane 2'b11
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`define Intra_chroma_DC 2'b00
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`define Intra_chroma_Horizontal 2'b01
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`define Intra_chroma_Vertical 2'b10
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`define Intra_chroma_Plane 2'b11
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//-------------------------------------------------------------------------------------------------
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//Inter prediction parameters
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//-------------------------------------------------------------------------------------------------
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//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window---
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`define pos_Int 4'b0000
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`define pos_a 4'b0100
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`define pos_b 4'b1000
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`define pos_c 4'b1100
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`define pos_d 4'b0001
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`define pos_e 4'b0101
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`define pos_f 4'b1001
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`define pos_g 4'b1101
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`define pos_h 4'b0010
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`define pos_i 4'b0110
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`define pos_j 4'b1010
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`define pos_k 4'b1110
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`define pos_n 4'b0011
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`define pos_p 4'b0111
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`define pos_q 4'b1011
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`define pos_r 4'b1111
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//---Inter_pred_pipeline
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`define pic_width 8'd176
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`define pic_height 8'd144
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`define half_pic_width 7'd88
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`define half_pic_height 7'd72
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//-------------------------------------------------------------------------------------------------
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//Deblocking filter parameters
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//-------------------------------------------------------------------------------------------------
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//---bs_decoding---
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`define I8x8 2'b00 //size of inter prediction partitions
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`define I16x8 2'b01
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`define I8x16 2'b10
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`define I16x16 2'b11
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//---DF_mbAddrA_RAM---
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`define DF_mbAddrA_RAM_data_width 32
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`define DF_mbAddrA_RAM_data_depth 32
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//---DF_mbAddrB_RAM---
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`define DF_mbAddrB_RAM_data_width 32
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`define DF_mbAddrB_RAM_data_depth 352
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//---rec_DF_RAM0---
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`define rec_DF_RAM0_data_width 32
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`define rec_DF_RAM0_data_depth 96
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//---rec_DF_RAM1---
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`define rec_DF_RAM1_data_width 32
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`define rec_DF_RAM1_data_depth 96
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//-------------------------------------------------------------------------------------------------
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//Hybrid pipeline control parameters
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//-------------------------------------------------------------------------------------------------
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