Subversion Repositories open8_urisc

-- Copyright (c)2020 Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- VHDL Units :  open8_cfg

-- Description:  Contains project specific constants to configure an Open8

--                system. This file contains an example from a working

--                configuration to demonstrate how it was used.

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      04/16/20 Design Start

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

library work;

  use work.open8_pkg.all;

package open8_cfg is

  -- Internal signals & constants

  constant Clock_Frequency   : real         := 100000000.0;

  -- Peripheral Options

  -- SDLC Configuration

  constant Master_Mode       : boolean      := true;

  constant BitClock_Freq     : real         := 20000000.0;

  constant Clock_Offset      : integer      := 3;

  -- MAX7221 Driver Configuration

  constant MAX7221_BITRATE   : real         := 5000000.0;

  -- Open8 CPU Options

  constant Allow_Stack_Address_Move : boolean := true;

  constant Stack_Xfer_Flag          : integer := PSR_GP4;

  constant Enable_Auto_Increment    : boolean := true;

  constant BRK_Implements_WAI       : boolean := true;

  constant Enable_NMI               : boolean := true;

  constant Sequential_Interrupts    : boolean := true;

  constant RTI_Ignores_GP_Flags     : boolean := true;

  constant Default_Int_Mask         : DATA_TYPE := x"00";

  -- Location and size of variable memory (BSS_START)

  constant LRAM_Size         : integer := 4096; -- Should match the LRAM model

  constant LRAM_Address      : ADDRESS_TYPE := x"0000";

   -- Store interrupt vectors at the top of ROM (INTR_VEC_TABLE)

  constant ISR_Start_Addr    : ADDRESS_TYPE := x"FFF0";

  -- Interrupt assignments

  -- These are assigned in order priority from 0 (highest) to 7 (lowest)

  constant INT_PIT           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;

  constant INT_ETC           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;

  constant INT_ALU           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;

  constant INT_RTC           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 3;

  constant INT_SDLC          : integer range 0 to OPEN8_DATA_WIDTH - 1 := 4;

  constant INT_BTN           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 5;

  constant INT_VEC           : integer range 0 to OPEN8_DATA_WIDTH - 1 := 6;

  -- Peripheral I/O map

  constant ALU_Address       : ADDRESS_TYPE := x"1000";  -- ALU16 coprocessor

  constant TMR_Address       : ADDRESS_TYPE := x"1100";  -- System Timer / RT Clock

  constant ETC_Address       : ADDRESS_TYPE := x"1200";  -- Epoch Timer/Alarm Clock

  constant LED_Address       : ADDRESS_TYPE := x"1400";  -- LED Display

  constant DSW_Address       : ADDRESS_TYPE := x"1800";  -- Dip Switches

  constant BTN_Address       : ADDRESS_TYPE := x"2000";  -- Push Buttons

  constant SDLC_Address      : ADDRESS_TYPE := x"2200";  -- LCD serial interface

  constant SER_Address       : ADDRESS_TYPE := x"2400";  -- UART interface

  constant MAX_Address       : ADDRESS_TYPE := x"2800";  -- Max 7221 base address

  constant ROM_Address       : ADDRESS_TYPE := x"8000";  -- Application ROM

  -- Set this to the number of readable modules in the design, as it sets the

  --  number of ports on the read aggregator function.

  constant OPEN8_READ_BUSES  : integer := 10;

  -- Read Data Bus aggregator and bus assignments.

  --  Note that the ordering isn't important, only that each device has a

  --   unique number less than READ_BUS_COUNT.

  constant RDB_RAM           : integer range 0 to OPEN8_READ_BUSES - 1 := 0;

  constant RDB_ALU           : integer range 0 to OPEN8_READ_BUSES - 1 := 1;

  constant RDB_TMR           : integer range 0 to OPEN8_READ_BUSES - 1 := 2;

  constant RDB_ETC           : integer range 0 to OPEN8_READ_BUSES - 1 := 3;

  constant RDB_LED           : integer range 0 to OPEN8_READ_BUSES - 1 := 4;

  constant RDB_DSW           : integer range 0 to OPEN8_READ_BUSES - 1 := 5;

  constant RDB_BTN           : integer range 0 to OPEN8_READ_BUSES - 1 := 6;

  constant RDB_SDLC          : integer range 0 to OPEN8_READ_BUSES - 1 := 7;

  constant RDB_SER           : integer range 0 to OPEN8_READ_BUSES - 1 := 8;

  constant RDB_ROM           : integer range 0 to OPEN8_READ_BUSES - 1 := 9;

  -- System configuration calculations - no adjustable parameters below this point

  type OPEN8_BUS_ARRAY is array(0 to OPEN8_READ_BUSES - 1) of DATA_TYPE;

  constant INIT_READ_BUS     : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);

  function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE;

  -- Compute the stack start address based on the RAM size

  constant RAM_Vector_Size   : integer := ceil_log2(LRAM_Size - 1);

  constant RAM_END_vector    : std_logic_vector(RAM_Vector_Size - 1 downto 0)

                                := (others => '1');

  constant Stack_Start_Addr  : ADDRESS_TYPE := LRAM_Address + RAM_END_vector;

end package;

package body open8_cfg is

  function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE is

    variable i               : integer   := 0;

    variable retval          : DATA_TYPE := x"00";

  begin

    retval                   := x"00";

    for i in 0 to OPEN8_READ_BUSES - 1 loop

      retval                 := retval or x(i);

    end loop;

    return retval;

  end function;

end package body;