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[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_cfg.vhd] - Blame information for rev 264

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Line No. Rev Author Line
1 258 jshamlet
-- VHDL units : em_interface
2
-- Description: Connects all of the components that comprise the ROMEO/JAGM
3
--               ESAF test stimulus controller
4 227 jshamlet
--
5
-- Revision History
6
-- Author          Date     Change
7
------------------ -------- ---------------------------------------------------
8 258 jshamlet
-- Seth Henry      04/16/20 Version block added
9 227 jshamlet
 
10
library ieee;
11
  use ieee.std_logic_1164.all;
12
 
13
library work;
14
  use work.open8_pkg.all;
15 258 jshamlet
  use work.open8_cfg.all;
16 227 jshamlet
 
17 258 jshamlet
entity em_interface is
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port(
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  -- Master oscillator
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  Ext_50M_Osc                : in  std_logic;
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  -- Push buttons
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  KEY0                       : in  std_logic;
23
  KEY1                       : in  std_logic;
24
  -- LED outputs
25
  LEDS                       : out std_logic_vector(7 downto 0);
26
  -- Configuration Switches
27
  DIPSW                      : in  std_logic_vector(3 downto 0);
28
  -- GPINs (input only)
29
  GPIN0                      : in  std_logic_vector(1 downto 0);
30
  GPIN1                      : in  std_logic_vector(1 downto 0);
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  GPIN2                      : in  std_logic_vector(2 downto 0);
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  -- GPIO
33
  GPIO0                      : inout std_logic_vector(33 downto 0);
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  GPIO1                      : inout std_logic_vector(33 downto 0);
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  GPIO2                      : inout std_logic_vector(12 downto 0)
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);
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end entity;
38 227 jshamlet
 
39 258 jshamlet
architecture behave of em_interface is
40 227 jshamlet
 
41 258 jshamlet
  -- I/O mapping aliases
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43 258 jshamlet
  -- Clocks & Resets
44
  alias  Sys_Clock_50M       is Ext_50M_Osc;
45 227 jshamlet
 
46 258 jshamlet
  -- External Pushbuttons
47
  alias  FMSIM_PB_Reset      is GPIN2(0);
48
  alias  FPGA_PB_Reset       is GPIN2(2);
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  alias  DBG_PB              is GPIO2(3);
50 240 jshamlet
 
51 258 jshamlet
  -- Diagnostic
52
  alias  JP1_1               is GPIN0(0);
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  alias  JP1_3               is GPIN0(1);
54 227 jshamlet
 
55 258 jshamlet
  alias  JP1_37              is GPIO0(30);
56
  alias  JP1_38              is GPIO0(31);
57
  alias  JP1_39              is GPIO0(32);
58
  alias  JP1_40              is GPIO0(33);
59 240 jshamlet
 
60 258 jshamlet
  alias  JP2_4               is GPIO1(1);
61 227 jshamlet
 
62 258 jshamlet
  -- Status LED
63
  alias  Status_LED          is GPIO2(10);
64 227 jshamlet
 
65 258 jshamlet
  -- Telemetry Serial
66
  alias  TM_Tx_Out           is GPIO1(0);
67
  alias  TM_CTS_In           is GPIN1(1);
68 227 jshamlet
 
69 258 jshamlet
  -- Vector RX (TS Input)
70
  alias  Vec_Rx              is GPIN1(0);
71 227 jshamlet
 
72 258 jshamlet
  -- MAX 7221 SPI Interface
73
  alias  MX_LDCSn            is GPIO2(9);
74
  alias  Mx_Clock            is GPIO2(5);
75
  alias  Mx_Data             is GPIO2(7);
76 227 jshamlet
 
77 258 jshamlet
  -- SDLC Serial Interface
78
  alias  SDLC_EM2IF          is GPIO0(18);
79
  alias  SDLC_Clock          is GPIO0(19);
80
  alias  SDLC_IF2EM          is GPIO0(20);
81 227 jshamlet
 
82 258 jshamlet
  -- Relay/Discrete I/O
83
  alias  EM_Elec_Power       is GPIO2(8);
84
  alias  EM_Arm_Power        is GPIO0(29);
85
  alias  EM_Separation       is GPIO0(5);
86
  alias  EM_Detonate_Cmd_1   is GPIO0(17);
87
  alias  EM_Detonate_Cmd_2   is GPIO0(9);
88
  alias  EM_Test_G1          is GPIO0(7);
89
  alias  EM_Test_G2          is GPIO0(11);
90
  alias  EM_Test_Mode        is GPIO0(2);
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92 258 jshamlet
  alias  EM_Config_ID_1      is GPIO0(0);
93
  alias  EM_Config_ID_2      is GPIO0(4);
94
  alias  EM_Config_ID_3      is GPIO0(8);
95
  alias  EM_Spare_1          is GPIO0(1);
96
  alias  EM_Int_Impact       is GPIO0(3);
97
  alias  EM_FPGA_POR_Reset   is GPIO0(6);
98
  alias  EM_PIC_POR_Reset    is GPIO0(10);
99
  alias  EM_Spare_Rly        is GPIO0(12);
100 227 jshamlet
 
101 258 jshamlet
  alias  EM_Accel_PDM        is GPIO2(11);
102 227 jshamlet
 
103 258 jshamlet
  -- Unused EM signals
104
  alias  EM_TXD_TST          is GPIO0(13);
105
  alias  EM_Aux_In_1         is GPIO0(14);
106
  alias  EM_Aux_Out_1        is GPIO0(15);
107
  alias  EM_RCV_TST          is GPIO0(16);
108 227 jshamlet
 
109 258 jshamlet
  -- PC FM Simulator IF          (NANO)
110
  alias  PC_Contact          is GPIO0(26);
111
  alias  PC_EM2FM            is GPIO0(27);
112
  alias  PC_FM2EM            is GPIO0(28);
113
  alias  PC_Fire_Out         is GPIO0(21);
114 227 jshamlet
 
115 258 jshamlet
  -- MC FM Simulator IF          (NANO)
116
  alias  MC_Contact          is GPIO0(23);
117
  alias  MC_EM2FM            is GPIO0(24);
118
  alias  MC_FM2EM            is GPIO0(25);
119
  alias  MC_Fire_Out         is GPIO0(22);
120 227 jshamlet
 
121 258 jshamlet
  -- NI DIO
122
  alias  NI_P0_0             is GPIO1(17);
123
  alias  NI_P0_1             is GPIO1(2);
124
  alias  NI_P0_2             is GPIO1(15);
125
  alias  NI_P0_3             is GPIO1(4);
126
  alias  NI_P0_4             is GPIO1(13);
127
  alias  NI_P0_5             is GPIO1(6);
128
  alias  NI_P0_6             is GPIO1(11);
129
  alias  NI_P0_7             is GPIO1(8);
130 227 jshamlet
 
131 258 jshamlet
  alias  NI_P1_0             is GPIO1(9);
132
  alias  NI_P1_1             is GPIO1(10);
133
  alias  NI_P1_2             is GPIO1(7);
134
  alias  NI_P1_3             is GPIO1(12);
135
  alias  NI_P1_4             is GPIO1(5);
136
  alias  NI_P1_5             is GPIO1(14);
137
  alias  NI_P1_6             is GPIO1(3);
138
  alias  NI_P1_7             is GPIO1(16);
139
 
140
  alias  NI_P2_0             is GPIO1(33);
141
  alias  NI_P2_1             is GPIO1(18);
142
  alias  NI_P2_2             is GPIO1(31);
143
  alias  NI_P2_3             is GPIO1(20);
144
  alias  NI_P2_4             is GPIO1(29);
145
  alias  NI_P2_5             is GPIO1(22);
146
  alias  NI_P2_6             is GPIO1(27);
147
  alias  NI_P2_7             is GPIO1(20);
148
 
149
  alias  NI_P3_0             is GPIO1(25);
150
  alias  NI_P3_1             is GPIO1(26);
151
  alias  NI_P3_2             is GPIO1(23);
152
  alias  NI_P3_3             is GPIO1(28);
153
  alias  NI_P3_4             is GPIO1(21);
154
  alias  NI_P3_5             is GPIO1(30);
155
  alias  NI_P3_6             is GPIO1(19);
156
  alias  NI_P3_7             is GPIO1(32);
157
 
158
  -- Internal mapping signals
159
 
160
  signal Sys_Async_Reset     : std_logic;
161
 
162
  signal Ext_Switches        : DATA_TYPE := x"00";
163
  signal CPU_Flags           : EXT_GP_FLAGS := "00000";
164
 
165
  signal BAR_LED             : DATA_TYPE := x"00";
166
 
167
  signal Vec_Req             : std_logic := '0';
168
  signal Vec_Index           : std_logic_vector(5 downto 0) := "000000";
169
  signal Vec_Data            : std_logic_vector(15 downto 0 ) := x"0000";
170
 
171
begin
172
 
173
  Reset_Input_proc: process( Sys_Clock_50M, FPGA_PB_Reset, NI_P0_7 )
174 227 jshamlet
  begin
175 258 jshamlet
    if( FPGA_PB_Reset = '0' or NI_P0_7 = '1' )then
176
      Sys_Async_Reset        <= '0';
177
    elsif( rising_edge( Sys_Clock_50M ) )then
178
      Sys_Async_Reset        <= '1';
179
    end if;
180
  end process;
181 227 jshamlet
 
182 258 jshamlet
  Vec_Req                    <= NI_P0_6;
183
 
184
  Vec_Index                  <= NI_P0_5 & NI_P0_4 & NI_P0_3 &
185
                                NI_P0_2 & NI_P0_1 & NI_P0_0;
186
 
187
  Vec_Data                   <= NI_P2_7 & NI_P2_6 & NI_P2_5 & NI_P2_4 &
188
                                NI_P2_3 & NI_P2_2 & NI_P2_1 & NI_P2_0 &
189
                                NI_P1_7 & NI_P1_6 & NI_P1_5 & NI_P1_4 &
190
                                NI_P1_3 & NI_P1_2 & NI_P1_1 & NI_P1_0;
191
 
192
  NI_P3_0                    <= BAR_LED(0);
193
  NI_P3_1                    <= BAR_LED(1);
194
  NI_P3_2                    <= BAR_LED(2);
195
  NI_P3_3                    <= BAR_LED(3);
196
  NI_P3_4                    <= BAR_LED(4);
197
  NI_P3_5                    <= BAR_LED(5);
198
  NI_P3_6                    <= BAR_LED(6);
199
  NI_P3_7                    <= BAR_LED(7);
200
 
201
  LEDS                       <= BAR_LED;
202
 
203
  Ext_Switches               <= DIPSW & KEY1 & KEY0 & DBG_PB & FMSIM_PB_Reset;
204
 
205
  JP1_37                     <= CPU_Flags(EXT_ISR);
206
  JP1_38                     <= CPU_Flags(EXT_GP5);
207
  JP1_39                     <= CPU_Flags(EXT_GP6);
208
  JP1_40                     <= CPU_Flags(EXT_GP7);
209
 
210
  U_CORE : entity work.em_core
211
  port map(
212
    Sys_Async_Reset          => Sys_Async_Reset,
213
    Sys_Clock_50M            => Sys_Clock_50M,
214
 
215
    -- Switches
216
    Ext_Switches             => Ext_Switches,
217
 
218
    -- LEDS
219
    BAR_LED                  => BAR_LED,
220
    Status_LED               => Status_LED,
221
 
222
    -- CPU Flags
223
    CPU_Flags                => CPU_Flags,
224
 
225
    -- Telemetry Serial
226
    TM_Tx_Out                => TM_Tx_Out,
227
    TM_CTS_In                => TM_CTS_In,
228
 
229
    -- MAX 7221 SPI Interface
230
    MX_LDCSn                 => MX_LDCSn,
231
    Mx_Clock                 => Mx_Clock,
232
    Mx_Data                  => Mx_Data,
233
 
234
    -- Vector RX (Aux TS Input)
235
    Vec_Req                  => Vec_Req,
236
    Vec_Index                => Vec_Index,
237
    Vec_Data                 => Vec_Data,
238
    Vec_Rx                   => Vec_Rx,
239
 
240
    -- SDLC Serial Interface
241
    SDLC_EM2IF               => SDLC_EM2IF,
242
    SDLC_Clock               => SDLC_Clock,
243
    SDLC_IF2EM               => SDLC_IF2EM,
244
 
245
    -- Relay/Discrete I/O
246
    EM_Elec_Power            => EM_Elec_Power,
247
    EM_Arm_Power             => EM_Arm_Power,
248
    EM_Separation            => EM_Separation,
249
    EM_Detonate_Cmd_1        => EM_Detonate_Cmd_1,
250
    EM_Detonate_Cmd_2        => EM_Detonate_Cmd_2,
251
    EM_Test_G1               => EM_Test_G1,
252
    EM_Test_G2               => EM_Test_G2,
253
    EM_Test_Mode             => EM_Test_Mode,
254
 
255
    EM_Config_ID_1           => EM_Config_ID_1,
256
    EM_Config_ID_2           => EM_Config_ID_2,
257
    EM_Config_ID_3           => EM_Config_ID_3,
258
    EM_Spare_1               => EM_Spare_1,
259
    EM_Int_Impact            => EM_Int_Impact,
260
    EM_FPGA_POR_Reset        => EM_FPGA_POR_Reset,
261
    EM_PIC_POR_Reset         => EM_PIC_POR_Reset,
262
    EM_Spare_Rly             => EM_Spare_Rly,
263
 
264
    EM_Accel_PDM             => EM_Accel_PDM,
265
 
266
    -- PC FM Simulator IF
267
    PC_Contact               => PC_Contact,
268
    PC_EM2FM                 => PC_EM2FM,
269
    PC_FM2EM                 => PC_FM2EM,
270
    PC_Fire_Out              => PC_Fire_Out,
271
 
272
    -- MC FM Simulator IF
273
    MC_Contact               => MC_Contact,
274
    MC_EM2FM                 => MC_EM2FM,
275
    MC_FM2EM                 => MC_FM2EM,
276
    MC_Fire_Out              => MC_Fire_Out
277
  );
278
 
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end architecture;

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