OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [hd44780_4b.vhd] - Blame information for rev 302

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 287 jshamlet
-- Copyright (c)2021 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Entity: o8_hd44780_4b
25
-- Description: Provides low-level timing of the control signals in 4-bit mode
26
--              (required by o8_hd44780_if)
27
--
28
-- Revision History
29
-- Author          Date     Change
30
------------------ -------- ---------------------------------------------------
31
-- Seth Henry      04/12/21 Design Start
32
 
33 286 jshamlet
library ieee;
34
  use ieee.std_logic_1164.all;
35
  use ieee.std_logic_unsigned.all;
36
  use ieee.std_logic_arith.all;
37
  use ieee.std_logic_misc.all;
38
 
39
entity hd44780_4b is
40
generic(
41
  Tsu                        : integer :=  40; -- ns
42
  Tpw                        : integer := 250; -- nS
43
  Tcyc                       : integer := 500; -- nS
44
  Clock_Frequency            : real    := 50000000.0; -- Hz
45
  Reset_Level                : std_logic := '1'
46
);
47
port(
48
  Clock                      : in  std_logic;
49
  Reset                      : in  std_logic;
50
  --
51
  Wr_Fnset                   : in  std_logic;
52
  Wr_Data                    : in  std_logic_vector(7 downto 0);
53
  Wr_Reg                     : in  std_logic;
54
  Wr_En                      : in  std_logic;
55
  --
56
  IO_Done                    : out std_logic;
57
  --
58
  LCD_RS                     : out std_logic;
59
  LCD_E                      : out std_logic;
60
  LCD_DQ                     : out std_logic_vector(7 downto 0)
61
);
62
end entity;
63
 
64
architecture behave of hd44780_4b is
65
 
66
  -- The ceil_log2 function returns the minimum register width required to
67
  --  hold the supplied integer.
68
  function ceil_log2 (x : in natural) return natural is
69
    variable retval          : natural;
70
  begin
71
    retval                   := 1;
72
    while ((2**retval) - 1) < x loop
73
      retval                 := retval + 1;
74
    end loop;
75
    return retval;
76
  end function;
77
 
78
  constant CONV_NANOSECS     : real := 0.000000001;
79
 
80
  constant Tsu_r             : real := CONV_NANOSECS * real(Tsu);
81
  constant Tpw_r             : real := CONV_NANOSECS * real(Tpw);
82
  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyc);
83
 
84
  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);
85
  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);
86
 
87
  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
88
                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
89
  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=
90
                               (others => '0');
91
 
92
  constant TPW_i             : integer := integer(Clock_Frequency * Tpw_r);
93
  constant TPW_DELAY         : std_logic_vector(TCYC_BITS-1 downto 0) :=
94
                               conv_std_logic_vector(TPW_i-1, TCYC_BITS);
95
 
96
  constant TSU_i             : integer := integer(Clock_Frequency * Tsu_r);
97
  constant TSU_BITS          : integer := ceil_log2(TSU_i);
98
  constant TSU_DELAY         : std_logic_vector(TSU_BITS - 1 downto 0) :=
99
                               conv_std_logic_vector(TSU_i-1,TSU_BITS);
100
  signal tsnh_timer          : std_logic_vector(TSU_BITS-1 downto 0) :=
101
                                (others => '0');
102
 
103
  type IO_STATES   is (IDLE,
104
                       INIT_UB, TAS_UB, TPW_UB, TCYC_UB,
105
                       INIT_LB, TPW_LB, TCYC_LB,
106
                       DONE );
107
  signal io_state            : IO_STATES;
108
  signal fn_set              : std_logic;
109
 
110
  signal Wr_Buffer           : std_logic_vector(8 downto 0);
111
  alias Wr_Buffer_A          is Wr_Buffer(8);
112
  alias Wr_Buffer_U          is Wr_Buffer(7 downto 4);
113
  alias Wr_Buffer_L          is Wr_Buffer(3 downto 0);
114
 
115
  alias LCD_DQ_U             is LCD_DQ(7 downto 4);
116
  alias LCD_DQ_L             is LCD_DQ(3 downto 0);
117
 
118
begin
119
 
120
  LCD_IO_proc: process( Clock, Reset )
121
  begin
122
    if( Reset = Reset_Level )then
123
      io_state               <= IDLE;
124
      fn_set                 <= '0';
125
      tcyc_timer             <= (others => '0');
126
      tsnh_timer             <= (others => '0');
127
      Wr_Buffer              <= (others => '0');
128
      IO_Done                <= '0';
129
      LCD_RS                 <= '0';
130
      LCD_E                  <= '0';
131
      LCD_DQ                 <= (others => '0');
132
    elsif( rising_edge(Clock) )then
133
      IO_Done                <= '0';
134
      LCD_E                  <= '0';
135
      LCD_DQ_L               <= (others => '0');
136
      case( io_state )is
137
        when IDLE =>
138
          if( Wr_En = '1' )then
139
            Wr_Buffer        <= Wr_Reg & Wr_Data;
140
            fn_set           <= Wr_Fnset;
141
            io_state         <= INIT_UB;
142
          end if;
143
 
144
        when INIT_UB =>
145
          tsnh_timer         <= TSU_DELAY;
146
          tcyc_timer         <= (others => '0');
147
          LCD_RS             <= Wr_Buffer_A;
148
          io_state           <= TAS_UB;
149
 
150
        when TAS_UB =>
151
          tsnh_timer         <= tsnh_timer - 1;
152
          if( or_reduce(tsnh_timer) = '0' )then
153
            io_state         <= TPW_UB;
154
          end if;
155
 
156
        when TPW_UB =>
157
          tcyc_timer         <= tcyc_timer + 1;
158
          LCD_E              <= '1';
159
          LCD_DQ_U           <= Wr_Buffer_U;
160
          if( tcyc_timer = TPW_DELAY )then
161
            io_state         <= TCYC_UB;
162
          end if;
163
 
164
        when TCYC_UB =>
165
          tcyc_timer         <= tcyc_timer + 1;
166
          if( tcyc_timer >= TCYC_DELAY )then
167
            io_state         <= INIT_LB;
168
          end if;
169
 
170
        when INIT_LB =>
171
          tcyc_timer         <= (others => '0');
172
          io_state           <= TPW_LB;
173
          if( fn_set = '1' )then
174
            fn_set           <= '0';
175
            io_state         <= TPW_UB;
176
          end if;
177
 
178
        when TPW_LB =>
179
          tcyc_timer         <= tcyc_timer + 1;
180
          LCD_E              <= '1';
181
          LCD_DQ_U           <= Wr_Buffer_L;
182
          if( tcyc_timer = TPW_DELAY )then
183
            io_state         <= TCYC_LB;
184
          end if;
185
 
186
        when TCYC_LB =>
187
          tcyc_timer         <= tcyc_timer + 1;
188
          if( tcyc_timer >= TCYC_DELAY )then
189
            io_state         <= DONE;
190
          end if;
191
 
192
        when DONE =>
193
          IO_Done            <= '1';
194
          LCD_RS             <= '0';
195
          LCD_DQ_U           <= (others => '0');
196
          io_state           <= IDLE;
197
 
198
        when others =>
199
          null;
200
      end case;
201
    end if;
202
  end process;
203
 
204
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.