OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [gdb/] [sim-arm.h] - Blame information for rev 101

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 khays
/* This file defines the interface between the Arm simulator and GDB.
2
 
3
   Copyright 2002, 2003, 2007, 2008, 2009, 2010, 2011
4
   Free Software Foundation, Inc.
5
 
6
   Contributed by Red Hat.
7
 
8
   This file is part of GDB.
9
 
10
   This program is free software; you can redistribute it and/or modify
11
   it under the terms of the GNU General Public License as published by
12
   the Free Software Foundation; either version 3 of the License, or
13
   (at your option) any later version.
14
 
15
   This program is distributed in the hope that it will be useful,
16
   but WITHOUT ANY WARRANTY; without even the implied warranty of
17
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
   GNU General Public License for more details.
19
 
20
   You should have received a copy of the GNU General Public License
21
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
#if !defined (SIM_ARM_H)
24
#define SIM_ARM_H
25
 
26
#ifdef __cplusplus
27
extern "C" { // }
28
#endif
29
 
30
enum sim_arm_regs
31
{
32
  SIM_ARM_R0_REGNUM,
33
  SIM_ARM_R1_REGNUM,
34
  SIM_ARM_R2_REGNUM,
35
  SIM_ARM_R3_REGNUM,
36
  SIM_ARM_R4_REGNUM,
37
  SIM_ARM_R5_REGNUM,
38
  SIM_ARM_R6_REGNUM,
39
  SIM_ARM_R7_REGNUM,
40
  SIM_ARM_R8_REGNUM,
41
  SIM_ARM_R9_REGNUM,
42
  SIM_ARM_R10_REGNUM,
43
  SIM_ARM_R11_REGNUM,
44
  SIM_ARM_R12_REGNUM,
45
  SIM_ARM_R13_REGNUM,
46
  SIM_ARM_R14_REGNUM,
47
  SIM_ARM_R15_REGNUM, /* PC */
48
  SIM_ARM_FP0_REGNUM,
49
  SIM_ARM_FP1_REGNUM,
50
  SIM_ARM_FP2_REGNUM,
51
  SIM_ARM_FP3_REGNUM,
52
  SIM_ARM_FP4_REGNUM,
53
  SIM_ARM_FP5_REGNUM,
54
  SIM_ARM_FP6_REGNUM,
55
  SIM_ARM_FP7_REGNUM,
56
  SIM_ARM_FPS_REGNUM,
57
  SIM_ARM_PS_REGNUM,
58
  SIM_ARM_MAVERIC_COP0R0_REGNUM,
59
  SIM_ARM_MAVERIC_COP0R1_REGNUM,
60
  SIM_ARM_MAVERIC_COP0R2_REGNUM,
61
  SIM_ARM_MAVERIC_COP0R3_REGNUM,
62
  SIM_ARM_MAVERIC_COP0R4_REGNUM,
63
  SIM_ARM_MAVERIC_COP0R5_REGNUM,
64
  SIM_ARM_MAVERIC_COP0R6_REGNUM,
65
  SIM_ARM_MAVERIC_COP0R7_REGNUM,
66
  SIM_ARM_MAVERIC_COP0R8_REGNUM,
67
  SIM_ARM_MAVERIC_COP0R9_REGNUM,
68
  SIM_ARM_MAVERIC_COP0R10_REGNUM,
69
  SIM_ARM_MAVERIC_COP0R11_REGNUM,
70
  SIM_ARM_MAVERIC_COP0R12_REGNUM,
71
  SIM_ARM_MAVERIC_COP0R13_REGNUM,
72
  SIM_ARM_MAVERIC_COP0R14_REGNUM,
73
  SIM_ARM_MAVERIC_COP0R15_REGNUM,
74
  SIM_ARM_MAVERIC_DSPSC_REGNUM,
75
  SIM_ARM_IWMMXT_COP0R0_REGNUM,
76
  SIM_ARM_IWMMXT_COP0R1_REGNUM,
77
  SIM_ARM_IWMMXT_COP0R2_REGNUM,
78
  SIM_ARM_IWMMXT_COP0R3_REGNUM,
79
  SIM_ARM_IWMMXT_COP0R4_REGNUM,
80
  SIM_ARM_IWMMXT_COP0R5_REGNUM,
81
  SIM_ARM_IWMMXT_COP0R6_REGNUM,
82
  SIM_ARM_IWMMXT_COP0R7_REGNUM,
83
  SIM_ARM_IWMMXT_COP0R8_REGNUM,
84
  SIM_ARM_IWMMXT_COP0R9_REGNUM,
85
  SIM_ARM_IWMMXT_COP0R10_REGNUM,
86
  SIM_ARM_IWMMXT_COP0R11_REGNUM,
87
  SIM_ARM_IWMMXT_COP0R12_REGNUM,
88
  SIM_ARM_IWMMXT_COP0R13_REGNUM,
89
  SIM_ARM_IWMMXT_COP0R14_REGNUM,
90
  SIM_ARM_IWMMXT_COP0R15_REGNUM,
91
  SIM_ARM_IWMMXT_COP1R0_REGNUM,
92
  SIM_ARM_IWMMXT_COP1R1_REGNUM,
93
  SIM_ARM_IWMMXT_COP1R2_REGNUM,
94
  SIM_ARM_IWMMXT_COP1R3_REGNUM,
95
  SIM_ARM_IWMMXT_COP1R4_REGNUM,
96
  SIM_ARM_IWMMXT_COP1R5_REGNUM,
97
  SIM_ARM_IWMMXT_COP1R6_REGNUM,
98
  SIM_ARM_IWMMXT_COP1R7_REGNUM,
99
  SIM_ARM_IWMMXT_COP1R8_REGNUM,
100
  SIM_ARM_IWMMXT_COP1R9_REGNUM,
101
  SIM_ARM_IWMMXT_COP1R10_REGNUM,
102
  SIM_ARM_IWMMXT_COP1R11_REGNUM,
103
  SIM_ARM_IWMMXT_COP1R12_REGNUM,
104
  SIM_ARM_IWMMXT_COP1R13_REGNUM,
105
  SIM_ARM_IWMMXT_COP1R14_REGNUM,
106
  SIM_ARM_IWMMXT_COP1R15_REGNUM
107
};
108
 
109
#ifdef __cplusplus
110
}
111
#endif
112
 
113
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.