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/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
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2008, 2009, 2010 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opintl.h"
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#include "opcode/ppc.h"
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/* This file provides several disassembler functions, all of which use
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the disassembler interface defined in dis-asm.h. Several functions
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
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ppc_cpu_t);
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struct dis_private
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{
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/* Stash the result of parsing disassembler_options here. */
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ppc_cpu_t dialect;
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};
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#define POWERPC_DIALECT(INFO) \
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(((struct dis_private *) ((INFO)->private_data))->dialect)
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struct ppc_mopt {
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const char *opt;
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ppc_cpu_t cpu;
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ppc_cpu_t sticky;
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};
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struct ppc_mopt ppc_opts[] = {
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{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
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{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
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| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
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{ "603", (PPC_OPCODE_PPC),
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{ "604", (PPC_OPCODE_PPC),
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{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
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{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
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, 0 },
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
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| PPC_OPCODE_A2),
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{ "altivec", (PPC_OPCODE_PPC),
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PPC_OPCODE_ALTIVEC },
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{ "any", 0,
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PPC_OPCODE_ANY },
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{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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{ "com", (PPC_OPCODE_COMMON),
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{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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{ "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC),
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{ "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
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{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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{ "ppc", (PPC_OPCODE_PPC),
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{ "ppc32", (PPC_OPCODE_PPC),
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{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
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{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
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{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
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{ "pwr", (PPC_OPCODE_POWER),
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{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
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{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
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{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
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{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
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PPC_OPCODE_SPE },
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{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
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| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
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{ "vsx", (PPC_OPCODE_PPC),
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PPC_OPCODE_VSX },
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};
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/* Handle -m and -M options that set cpu type, and .machine arg. */
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ppc_cpu_t
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ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
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{
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/* Sticky bits. */
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ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
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| PPC_OPCODE_SPE | PPC_OPCODE_ANY);
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unsigned int i;
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for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
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if (strcmp (ppc_opts[i].opt, arg) == 0)
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{
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if (ppc_opts[i].sticky)
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{
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retain_flags |= ppc_opts[i].sticky;
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if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
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| PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0)
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break;
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}
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ppc_cpu = ppc_opts[i].cpu;
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break;
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}
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if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
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return 0;
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ppc_cpu |= retain_flags;
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return ppc_cpu;
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}
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/* Determine which set of machines to disassemble for. */
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static int
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powerpc_init_dialect (struct disassemble_info *info)
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{
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ppc_cpu_t dialect = 0;
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char *arg;
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struct dis_private *priv = calloc (sizeof (*priv), 1);
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if (priv == NULL)
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return FALSE;
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arg = info->disassembler_options;
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while (arg != NULL)
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{
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ppc_cpu_t new_cpu = 0;
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char *end = strchr (arg, ',');
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if (end != NULL)
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*end = 0;
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if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
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dialect = new_cpu;
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else if (strcmp (arg, "32") == 0)
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dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
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else if (strcmp (arg, "64") == 0)
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dialect |= PPC_OPCODE_64;
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else
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fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
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if (end != NULL)
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*end++ = ',';
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arg = end;
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}
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if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
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{
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if (info->mach == bfd_mach_ppc64)
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dialect |= PPC_OPCODE_64;
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else
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dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
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/* Choose a reasonable default. */
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dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
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| PPC_OPCODE_ALTIVEC);
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}
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info->private_data = priv;
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POWERPC_DIALECT(info) = dialect;
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return TRUE;
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}
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| 257 |
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| 258 |
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/* Print a big endian PowerPC instruction. */
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| 259 |
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| 260 |
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int
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print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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| 262 |
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{
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| 263 |
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if (info->private_data == NULL && !powerpc_init_dialect (info))
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return -1;
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return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
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| 266 |
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}
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| 267 |
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| 268 |
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/* Print a little endian PowerPC instruction. */
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| 269 |
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| 270 |
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int
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| 271 |
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print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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| 272 |
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{
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| 273 |
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if (info->private_data == NULL && !powerpc_init_dialect (info))
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| 274 |
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return -1;
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| 275 |
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return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
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| 276 |
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}
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| 277 |
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| 278 |
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/* Print a POWER (RS/6000) instruction. */
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| 279 |
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| 280 |
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int
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| 281 |
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print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
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| 282 |
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{
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| 283 |
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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| 284 |
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}
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| 285 |
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| 286 |
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/* Extract the operand value from the PowerPC or POWER instruction. */
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| 287 |
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| 288 |
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static long
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| 289 |
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operand_value_powerpc (const struct powerpc_operand *operand,
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| 290 |
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unsigned long insn, ppc_cpu_t dialect)
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| 291 |
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{
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| 292 |
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long value;
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| 293 |
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int invalid;
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| 294 |
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/* Extract the value from the instruction. */
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| 295 |
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if (operand->extract)
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| 296 |
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value = (*operand->extract) (insn, dialect, &invalid);
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| 297 |
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else
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| 298 |
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{
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| 299 |
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value = (insn >> operand->shift) & operand->bitm;
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| 300 |
|
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
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| 301 |
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{
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| 302 |
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/* BITM is always some number of zeros followed by some
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| 303 |
|
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number of ones, followed by some numer of zeros. */
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| 304 |
|
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unsigned long top = operand->bitm;
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| 305 |
|
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/* top & -top gives the rightmost 1 bit, so this
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| 306 |
|
|
fills in any trailing zeros. */
|
| 307 |
|
|
top |= (top & -top) - 1;
|
| 308 |
|
|
top &= ~(top >> 1);
|
| 309 |
|
|
value = (value ^ top) - top;
|
| 310 |
|
|
}
|
| 311 |
|
|
}
|
| 312 |
|
|
|
| 313 |
|
|
return value;
|
| 314 |
|
|
}
|
| 315 |
|
|
|
| 316 |
|
|
/* Determine whether the optional operand(s) should be printed. */
|
| 317 |
|
|
|
| 318 |
|
|
static int
|
| 319 |
|
|
skip_optional_operands (const unsigned char *opindex,
|
| 320 |
|
|
unsigned long insn, ppc_cpu_t dialect)
|
| 321 |
|
|
{
|
| 322 |
|
|
const struct powerpc_operand *operand;
|
| 323 |
|
|
|
| 324 |
|
|
for (; *opindex != 0; opindex++)
|
| 325 |
|
|
{
|
| 326 |
|
|
operand = &powerpc_operands[*opindex];
|
| 327 |
|
|
if ((operand->flags & PPC_OPERAND_NEXT) != 0
|
| 328 |
|
|
|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
| 329 |
|
|
&& operand_value_powerpc (operand, insn, dialect) != 0))
|
| 330 |
|
|
return 0;
|
| 331 |
|
|
}
|
| 332 |
|
|
|
| 333 |
|
|
return 1;
|
| 334 |
|
|
}
|
| 335 |
|
|
|
| 336 |
|
|
/* Print a PowerPC or POWER instruction. */
|
| 337 |
|
|
|
| 338 |
|
|
static int
|
| 339 |
|
|
print_insn_powerpc (bfd_vma memaddr,
|
| 340 |
|
|
struct disassemble_info *info,
|
| 341 |
|
|
int bigendian,
|
| 342 |
|
|
ppc_cpu_t dialect)
|
| 343 |
|
|
{
|
| 344 |
|
|
bfd_byte buffer[4];
|
| 345 |
|
|
int status;
|
| 346 |
|
|
unsigned long insn;
|
| 347 |
|
|
const struct powerpc_opcode *opcode;
|
| 348 |
|
|
const struct powerpc_opcode *opcode_end;
|
| 349 |
|
|
unsigned long op;
|
| 350 |
|
|
ppc_cpu_t dialect_orig = dialect;
|
| 351 |
|
|
|
| 352 |
|
|
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
| 353 |
|
|
if (status != 0)
|
| 354 |
|
|
{
|
| 355 |
|
|
(*info->memory_error_func) (status, memaddr, info);
|
| 356 |
|
|
return -1;
|
| 357 |
|
|
}
|
| 358 |
|
|
|
| 359 |
|
|
if (bigendian)
|
| 360 |
|
|
insn = bfd_getb32 (buffer);
|
| 361 |
|
|
else
|
| 362 |
|
|
insn = bfd_getl32 (buffer);
|
| 363 |
|
|
|
| 364 |
|
|
/* Get the major opcode of the instruction. */
|
| 365 |
|
|
op = PPC_OP (insn);
|
| 366 |
|
|
|
| 367 |
|
|
/* Find the first match in the opcode table. We could speed this up
|
| 368 |
|
|
a bit by doing a binary search on the major opcode. */
|
| 369 |
|
|
opcode_end = powerpc_opcodes + powerpc_num_opcodes;
|
| 370 |
|
|
again:
|
| 371 |
|
|
for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
|
| 372 |
|
|
{
|
| 373 |
|
|
unsigned long table_op;
|
| 374 |
|
|
const unsigned char *opindex;
|
| 375 |
|
|
const struct powerpc_operand *operand;
|
| 376 |
|
|
int invalid;
|
| 377 |
|
|
int need_comma;
|
| 378 |
|
|
int need_paren;
|
| 379 |
|
|
int skip_optional;
|
| 380 |
|
|
|
| 381 |
|
|
table_op = PPC_OP (opcode->opcode);
|
| 382 |
|
|
if (op < table_op)
|
| 383 |
|
|
break;
|
| 384 |
|
|
if (op > table_op)
|
| 385 |
|
|
continue;
|
| 386 |
|
|
|
| 387 |
|
|
if ((insn & opcode->mask) != opcode->opcode
|
| 388 |
|
|
|| (opcode->flags & dialect) == 0
|
| 389 |
|
|
|| (opcode->deprecated & dialect_orig) != 0)
|
| 390 |
|
|
continue;
|
| 391 |
|
|
|
| 392 |
|
|
/* Make two passes over the operands. First see if any of them
|
| 393 |
|
|
have extraction functions, and, if they do, make sure the
|
| 394 |
|
|
instruction is valid. */
|
| 395 |
|
|
invalid = 0;
|
| 396 |
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
| 397 |
|
|
{
|
| 398 |
|
|
operand = powerpc_operands + *opindex;
|
| 399 |
|
|
if (operand->extract)
|
| 400 |
|
|
(*operand->extract) (insn, dialect, &invalid);
|
| 401 |
|
|
}
|
| 402 |
|
|
if (invalid)
|
| 403 |
|
|
continue;
|
| 404 |
|
|
|
| 405 |
|
|
/* The instruction is valid. */
|
| 406 |
|
|
if (opcode->operands[0] != 0)
|
| 407 |
|
|
(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
|
| 408 |
|
|
else
|
| 409 |
|
|
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
| 410 |
|
|
|
| 411 |
|
|
/* Now extract and print the operands. */
|
| 412 |
|
|
need_comma = 0;
|
| 413 |
|
|
need_paren = 0;
|
| 414 |
|
|
skip_optional = -1;
|
| 415 |
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
| 416 |
|
|
{
|
| 417 |
|
|
long value;
|
| 418 |
|
|
|
| 419 |
|
|
operand = powerpc_operands + *opindex;
|
| 420 |
|
|
|
| 421 |
|
|
/* Operands that are marked FAKE are simply ignored. We
|
| 422 |
|
|
already made sure that the extract function considered
|
| 423 |
|
|
the instruction to be valid. */
|
| 424 |
|
|
if ((operand->flags & PPC_OPERAND_FAKE) != 0)
|
| 425 |
|
|
continue;
|
| 426 |
|
|
|
| 427 |
|
|
/* If all of the optional operands have the value zero,
|
| 428 |
|
|
then don't print any of them. */
|
| 429 |
|
|
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
|
| 430 |
|
|
{
|
| 431 |
|
|
if (skip_optional < 0)
|
| 432 |
|
|
skip_optional = skip_optional_operands (opindex, insn,
|
| 433 |
|
|
dialect);
|
| 434 |
|
|
if (skip_optional)
|
| 435 |
|
|
continue;
|
| 436 |
|
|
}
|
| 437 |
|
|
|
| 438 |
|
|
value = operand_value_powerpc (operand, insn, dialect);
|
| 439 |
|
|
|
| 440 |
|
|
if (need_comma)
|
| 441 |
|
|
{
|
| 442 |
|
|
(*info->fprintf_func) (info->stream, ",");
|
| 443 |
|
|
need_comma = 0;
|
| 444 |
|
|
}
|
| 445 |
|
|
|
| 446 |
|
|
/* Print the operand as directed by the flags. */
|
| 447 |
|
|
if ((operand->flags & PPC_OPERAND_GPR) != 0
|
| 448 |
|
|
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
|
| 449 |
|
|
(*info->fprintf_func) (info->stream, "r%ld", value);
|
| 450 |
|
|
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
|
| 451 |
|
|
(*info->fprintf_func) (info->stream, "f%ld", value);
|
| 452 |
|
|
else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
| 453 |
|
|
(*info->fprintf_func) (info->stream, "v%ld", value);
|
| 454 |
|
|
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
| 455 |
|
|
(*info->fprintf_func) (info->stream, "vs%ld", value);
|
| 456 |
|
|
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
| 457 |
|
|
(*info->print_address_func) (memaddr + value, info);
|
| 458 |
|
|
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
| 459 |
|
|
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
| 460 |
|
|
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
|
| 461 |
|
|
(*info->fprintf_func) (info->stream, "fsl%ld", value);
|
| 462 |
|
|
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
|
| 463 |
|
|
(*info->fprintf_func) (info->stream, "fcr%ld", value);
|
| 464 |
|
|
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
|
| 465 |
|
|
(*info->fprintf_func) (info->stream, "%ld", value);
|
| 466 |
|
|
else if ((operand->flags & PPC_OPERAND_CR) != 0
|
| 467 |
|
|
&& (dialect & PPC_OPCODE_PPC) != 0)
|
| 468 |
|
|
{
|
| 469 |
|
|
if (operand->bitm == 7)
|
| 470 |
|
|
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
| 471 |
|
|
else
|
| 472 |
|
|
{
|
| 473 |
|
|
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
| 474 |
|
|
int cr;
|
| 475 |
|
|
int cc;
|
| 476 |
|
|
|
| 477 |
|
|
cr = value >> 2;
|
| 478 |
|
|
if (cr != 0)
|
| 479 |
|
|
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
| 480 |
|
|
cc = value & 3;
|
| 481 |
|
|
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
| 482 |
|
|
}
|
| 483 |
|
|
}
|
| 484 |
|
|
else
|
| 485 |
|
|
(*info->fprintf_func) (info->stream, "%ld", value);
|
| 486 |
|
|
|
| 487 |
|
|
if (need_paren)
|
| 488 |
|
|
{
|
| 489 |
|
|
(*info->fprintf_func) (info->stream, ")");
|
| 490 |
|
|
need_paren = 0;
|
| 491 |
|
|
}
|
| 492 |
|
|
|
| 493 |
|
|
if ((operand->flags & PPC_OPERAND_PARENS) == 0)
|
| 494 |
|
|
need_comma = 1;
|
| 495 |
|
|
else
|
| 496 |
|
|
{
|
| 497 |
|
|
(*info->fprintf_func) (info->stream, "(");
|
| 498 |
|
|
need_paren = 1;
|
| 499 |
|
|
}
|
| 500 |
|
|
}
|
| 501 |
|
|
|
| 502 |
|
|
/* We have found and printed an instruction; return. */
|
| 503 |
|
|
return 4;
|
| 504 |
|
|
}
|
| 505 |
|
|
|
| 506 |
|
|
if ((dialect & PPC_OPCODE_ANY) != 0)
|
| 507 |
|
|
{
|
| 508 |
|
|
dialect = ~(ppc_cpu_t) PPC_OPCODE_ANY;
|
| 509 |
|
|
goto again;
|
| 510 |
|
|
}
|
| 511 |
|
|
|
| 512 |
|
|
/* We could not find a match. */
|
| 513 |
|
|
(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
|
| 514 |
|
|
|
| 515 |
|
|
return 4;
|
| 516 |
|
|
}
|
| 517 |
|
|
|
| 518 |
|
|
void
|
| 519 |
|
|
print_ppc_disassembler_options (FILE *stream)
|
| 520 |
|
|
{
|
| 521 |
|
|
unsigned int i, col;
|
| 522 |
|
|
|
| 523 |
|
|
fprintf (stream, _("\n\
|
| 524 |
|
|
The following PPC specific disassembler options are supported for use with\n\
|
| 525 |
|
|
the -M switch:\n"));
|
| 526 |
|
|
|
| 527 |
|
|
for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
|
| 528 |
|
|
{
|
| 529 |
|
|
col += fprintf (stream, " %s,", ppc_opts[i].opt);
|
| 530 |
|
|
if (col > 66)
|
| 531 |
|
|
{
|
| 532 |
|
|
fprintf (stream, "\n");
|
| 533 |
|
|
col = 0;
|
| 534 |
|
|
}
|
| 535 |
|
|
}
|
| 536 |
|
|
fprintf (stream, " 32, 64\n");
|
| 537 |
|
|
}
|
