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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [v850-opc.c] - Blame information for rev 53

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1 18 khays
/* Assemble V850 instructions.
2
   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
 
22
#include <stdio.h>
23
#include "sysdep.h"
24
#include "opcode/v850.h"
25
#include "bfd.h"
26
#include "opintl.h"
27
 
28
 
29
/* Regular opcodes.  */
30
#define OP(x)           ((x & 0x3f) << 5)
31
#define OP_MASK         OP (0x3f)
32
 
33
/* Conditional branch opcodes (Format III).  */
34
#define BOP(x)          ((0x58 << 4) | (x & 0x0f))
35
#define BOP_MASK        ((0x78 << 4) | 0x0f)
36
 
37
/* Conditional branch opcodes (Format VII).  */
38
#define BOP7(x)         (0x107e0 | (x & 0xf))
39
#define BOP7_MASK       (0x1ffe0 | 0xf)
40
 
41
/* One-word opcodes.  */
42
#define one(x)          ((unsigned int) (x))
43
 
44
/* Two-word opcodes.  */
45
#define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
46
 
47
 
48
/* The functions used to insert and extract complicated operands.  */
49
 
50
/* Note: There is a conspiracy between these functions and
51
   v850_insert_operand() in gas/config/tc-v850.c.  Error messages
52
   containing the string 'out of range' will be ignored unless a
53
   specific command line option is given to GAS.  */
54
 
55
static const char * not_valid    = N_ ("displacement value is not in range and is not aligned");
56
static const char * out_of_range = N_ ("displacement value is out of range");
57
static const char * not_aligned  = N_ ("displacement value is not aligned");
58
 
59
static const char * immediate_out_of_range = N_ ("immediate value is out of range");
60
static const char * branch_out_of_range = N_ ("branch value out of range");
61
static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset");
62
static const char * branch_to_odd_offset = N_ ("branch to odd offset");
63
 
64
 
65
int
66
v850_msg_is_out_of_range (const char* msg)
67
{
68
  return msg == out_of_range
69
    || msg == immediate_out_of_range
70
    || msg == branch_out_of_range;
71
}
72
 
73
static unsigned long
74
insert_i5div1 (unsigned long insn, long value, const char ** errmsg)
75
{
76
  if (value > 30 || value < 2)
77
    {
78
      if (value & 1)
79
        * errmsg = _(not_valid);
80
      else
81
        * errmsg = _(out_of_range);
82
    }
83
  else if (value & 1)
84
    * errmsg = _(not_aligned);
85
 
86
  value = (32 - value)/2;
87
 
88
  return (insn | ((value << (2+16)) & 0x3c0000));
89
}
90
 
91
static unsigned long
92
extract_i5div1 (unsigned long insn, int * invalid)
93
{
94
  unsigned long ret = (insn & 0x003c0000) >> (16+2);
95
  ret = 32 - (ret * 2);
96
 
97
  if (invalid != 0)
98
    *invalid = (ret > 30 || ret < 2) ? 1 : 0;
99
  return ret;
100
}
101
 
102
static unsigned long
103
insert_i5div2 (unsigned long insn, long value, const char ** errmsg)
104
{
105
  if (value > 30 || value < 4)
106
    {
107
      if (value & 1)
108
        * errmsg = _(not_valid);
109
      else
110
        * errmsg = _(out_of_range);
111
    }
112
  else if (value & 1)
113
    * errmsg = _(not_aligned);
114
 
115
  value = (32 - value)/2;
116
 
117
  return (insn | ((value << (2+16)) & 0x3c0000));
118
}
119
 
120
static unsigned long
121
extract_i5div2 (unsigned long insn, int * invalid)
122
{
123
  unsigned long ret = (insn & 0x003c0000) >> (16+2);
124
  ret = 32 - (ret * 2);
125
 
126
  if (invalid != 0)
127
    *invalid = (ret > 30 || ret < 4) ? 1 : 0;
128
  return ret;
129
}
130
 
131
static unsigned long
132
insert_i5div3 (unsigned long insn, long value, const char ** errmsg)
133
{
134
  if (value > 32 || value < 2)
135
    {
136
      if (value & 1)
137
        * errmsg = _(not_valid);
138
      else
139
        * errmsg = _(out_of_range);
140
    }
141
  else if (value & 1)
142
    * errmsg = _(not_aligned);
143
 
144
  value = (32 - value)/2;
145
 
146
  return (insn | ((value << (2+16)) & 0x3c0000));
147
}
148
 
149
static unsigned long
150
extract_i5div3 (unsigned long insn, int * invalid)
151
{
152
  unsigned long ret = (insn & 0x003c0000) >> (16+2);
153
  ret = 32 - (ret * 2);
154
 
155
  if (invalid != 0)
156
    *invalid = (ret > 32 || ret < 2) ? 1 : 0;
157
  return ret;
158
}
159
 
160
static unsigned long
161
insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
162
{
163
  if (value > 0x1f || value < 0)
164
    {
165
      if (value & 1)
166
        * errmsg = _(not_valid);
167
      else
168
        * errmsg = _(out_of_range);
169
    }
170
  else if (value & 1)
171
    * errmsg = _(not_aligned);
172
 
173
  value >>= 1;
174
 
175
  return insn | (value & 0x0f);
176
}
177
 
178
static unsigned long
179
extract_d5_4 (unsigned long insn, int * invalid)
180
{
181
  unsigned long ret = (insn & 0x0f);
182
 
183
  ret <<= 1;
184
 
185
  if (invalid != 0)
186
    *invalid = 0;
187
  return ret;
188
}
189
 
190
static unsigned long
191
insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
192
{
193
  if (value > 0xff || value < 0)
194
    {
195
      if ((value % 4) != 0)
196
        * errmsg = _(not_valid);
197
      else
198
        * errmsg = _(out_of_range);
199
    }
200
  else if ((value % 4) != 0)
201
    * errmsg = _(not_aligned);
202
 
203
  value >>= 1;
204
 
205
  return insn | (value & 0x7e);
206
}
207
 
208
static unsigned long
209
extract_d8_6 (unsigned long insn, int * invalid)
210
{
211
  unsigned long ret = (insn & 0x7e);
212
 
213
  ret <<= 1;
214
 
215
  if (invalid != 0)
216
    *invalid = 0;
217
  return ret;
218
}
219
 
220
static unsigned long
221
insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
222
{
223
  if (value > 0xff || value < 0)
224
    {
225
      if ((value % 2) != 0)
226
        * errmsg = _(not_valid);
227
      else
228
        * errmsg = _(out_of_range);
229
    }
230
  else if ((value % 2) != 0)
231
    * errmsg = _(not_aligned);
232
 
233
  value >>= 1;
234
 
235
  return insn | (value & 0x7f);
236
}
237
 
238
static unsigned long
239
extract_d8_7 (unsigned long insn, int * invalid)
240
{
241
  unsigned long ret = (insn & 0x7f);
242
 
243
  ret <<= 1;
244
 
245
  if (invalid != 0)
246
    *invalid = 0;
247
  return ret;
248
}
249
 
250
static unsigned long
251
insert_v8 (unsigned long insn, long value, const char ** errmsg)
252
{
253
  if (value > 0xff || value < 0)
254
    * errmsg = _(immediate_out_of_range);
255
 
256
  return insn | (value & 0x1f) | ((value & 0xe0) << (27-5));
257
}
258
 
259
static unsigned long
260
extract_v8 (unsigned long insn, int * invalid)
261
{
262
  unsigned long ret = (insn & 0x1f) | ((insn & 0x38000000) >> (27-5));
263
 
264
  if (invalid != 0)
265
    *invalid = 0;
266
  return ret;
267
}
268
 
269
static unsigned long
270
insert_d9 (unsigned long insn, long value, const char ** errmsg)
271
{
272
  if (value > 0xff || value < -0x100)
273
    {
274
      if ((value % 2) != 0)
275
        * errmsg = branch_out_of_range_and_odd_offset;
276
      else
277
        * errmsg = branch_out_of_range;
278
    }
279
  else if ((value % 2) != 0)
280
    * errmsg = branch_to_odd_offset;
281
 
282
  return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
283
}
284
 
285
static unsigned long
286
extract_d9 (unsigned long insn, int * invalid)
287
{
288
  unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
289
 
290
  if ((insn & 0x8000) != 0)
291
    ret -= 0x0200;
292
 
293
  if (invalid != 0)
294
    *invalid = 0;
295
  return ret;
296
}
297
 
298
static unsigned long
299
insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
300
{
301
  if (value < -0xffff || value > 0)
302
    {
303
      if ((value % 2) != 0)
304
        * errmsg = branch_out_of_range_and_odd_offset;
305
      else
306
        * errmsg = branch_out_of_range;
307
    }
308
  else if ((value % 2) != 0)
309
    * errmsg = branch_to_odd_offset;
310
 
311
  return insn | ((-value & 0xfffe) << 16);
312
}
313
 
314
static unsigned long
315
extract_u16_loop (unsigned long insn, int * invalid)
316
{
317
  long ret = (insn >> 16) & 0xfffe;
318
  ret = -ret;
319
 
320
  if (invalid != 0)
321
    *invalid = 0;
322
  return ret;
323
}
324
 
325
static unsigned long
326
insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
327
{
328
  if (value > 0x7fff || value < -0x8000)
329
    {
330
      if ((value % 2) != 0)
331
        * errmsg = _(not_valid);
332
      else
333
        * errmsg = _(out_of_range);
334
    }
335
  else if ((value % 2) != 0)
336
    * errmsg = _(not_aligned);
337
 
338
  return insn | ((value & 0xfffe) << 16);
339
}
340
 
341
static unsigned long
342
extract_d16_15 (unsigned long insn, int * invalid)
343
{
344
  signed long ret = (insn & 0xfffe0000);
345
  ret >>= 16;
346
 
347
  if (invalid != 0)
348
    *invalid = 0;
349
  return ret;
350
}
351
 
352
static unsigned long
353
insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
354
{
355
  if (value > 0x7fff || value < -0x8000)
356
    * errmsg = _(out_of_range);
357
 
358
  return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
359
}
360
 
361
static unsigned long
362
extract_d16_16 (unsigned long insn, int * invalid)
363
{
364
  signed long ret = insn & 0xfffe0000;
365
  ret >>= 16;
366
  ret |= ((insn & 0x20) >> 5);
367
 
368
  if (invalid != 0)
369
    *invalid = 0;
370
  return ret;
371
}
372
 
373
static unsigned long
374
insert_d17_16 (unsigned long insn, long value, const char ** errmsg)
375
{
376
  if (value > 0xffff || value < -0x10000)
377
    * errmsg = _(out_of_range);
378
 
379
  return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4));
380
}
381
 
382
static unsigned long
383
extract_d17_16 (unsigned long insn, int * invalid)
384
{
385
  signed long ret = (insn >> 16) & 0xfffe;
386
  ret |= (insn << (16 - 4)) & 0x10000;
387
  ret = (ret << ((sizeof ret)*8 - 17)) >> ((sizeof ret)*8 - 17);
388
 
389
  if (invalid != 0)
390
    *invalid = 0;
391
  return (unsigned long)ret;
392
}
393
 
394
static unsigned long
395
insert_d22 (unsigned long insn, long value, const char ** errmsg)
396
{
397
  if (value > 0x1fffff || value < -0x200000)
398
    {
399
      if ((value % 2) != 0)
400
        * errmsg = branch_out_of_range_and_odd_offset;
401
      else
402
        * errmsg = branch_out_of_range;
403
    }
404
  else if ((value % 2) != 0)
405
    * errmsg = branch_to_odd_offset;
406
 
407
  return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
408
}
409
 
410
static unsigned long
411
extract_d22 (unsigned long insn, int * invalid)
412
{
413
  signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
414
 
415
  ret = (ret << ((sizeof ret)*8 - 22)) >> ((sizeof ret)*8 - 22);
416
 
417
  if (invalid != 0)
418
    *invalid = 0;
419
  return (unsigned long) ret;
420
}
421
 
422
static unsigned long
423
insert_d23 (unsigned long insn, long value, const char ** errmsg)
424
{
425
  if (value > 0x3fffff || value < -0x400000)
426
        * errmsg = out_of_range;
427
 
428
  return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7));
429
}
430
 
431
static unsigned long
432
extract_d23 (unsigned long insn, int * invalid)
433
{
434
  signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fffff80);
435
 
436
  ret = ((ret << ((sizeof ret)*8 - 23)) >> ((sizeof ret)*8 - 23));
437
 
438
  if (invalid != 0)
439
    *invalid = 0;
440
  return (unsigned long) ret;
441
}
442
 
443
static unsigned long
444
insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
445
{
446
  if (value > 0xff || value < -0x100)
447
    * errmsg = _(immediate_out_of_range);
448
 
449
  return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
450
}
451
 
452
static unsigned long
453
extract_i9 (unsigned long insn, int * invalid)
454
{
455
  signed long ret = insn & 0x003c0000;
456
 
457
  ret <<= 10;
458
  ret >>= 23;
459
  ret |= (insn & 0x1f);
460
 
461
  if (invalid != 0)
462
    *invalid = 0;
463
  return ret;
464
}
465
 
466
static unsigned long
467
insert_u9 (unsigned long insn, long v, const char ** errmsg)
468
{
469
  unsigned long value = (unsigned long) v;
470
 
471
  if (value > 0x1ff)
472
    * errmsg = _(immediate_out_of_range);
473
 
474
  return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
475
}
476
 
477
static unsigned long
478
extract_u9 (unsigned long insn, int * invalid)
479
{
480
  unsigned long ret = insn & 0x003c0000;
481
 
482
  ret >>= 13;
483
 
484
  ret |= (insn & 0x1f);
485
 
486
  if (invalid != 0)
487
    *invalid = 0;
488
  return ret;
489
}
490
 
491
static unsigned long
492
insert_spe (unsigned long insn, long v, const char ** errmsg)
493
{
494
  unsigned long value = (unsigned long) v;
495
 
496
  if (value != 3)
497
    * errmsg = _("invalid register for stack adjustment");
498
 
499
  return insn & (~ 0x180000);
500
}
501
 
502
static unsigned long
503
extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid)
504
{
505
  if (invalid != 0)
506
    *invalid = 0;
507
 
508
  return 3;
509
}
510
 
511
static unsigned long
512
insert_r4 (unsigned long insn, long v, const char ** errmsg)
513
{
514
  unsigned long value = (unsigned long) v;
515
 
516
  if (value >= 32)
517
    {
518
      * errmsg = _("invalid register name");
519
    }
520
 
521
  return insn | ((value & 0x10) << (23-4)) | ((value & 0x0f) << (17));
522
}
523
 
524
static unsigned long
525
extract_r4 (unsigned long insn, int * invalid)
526
{
527
  unsigned long ret;
528
  ret = (insn >> 17) & 0xf;
529
  ret |= (insn >> (23-4)) & 0x10;
530
 
531
  if (invalid != 0)
532
    *invalid = 0;
533
  return ret;
534
}
535
 
536
/* Warning: code in gas/config/tc-v850.c examines the contents of this array.
537
   If you change any of the values here, be sure to look for side effects in
538
   that code.  */
539
const struct v850_operand v850_operands[] =
540
{
541
#define UNUSED  0
542
  { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE },
543
 
544
/* The R1 field in a format 1, 6, 7, 9, C insn.  */
545
#define R1      (UNUSED + 1)
546
  { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
547
 
548
/* As above, but register 0 is not allowed.  */
549
#define R1_NOTR0 (R1 + 1)
550
  { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
551
 
552
/* Even register is allowed.  */
553
#define R1_EVEN (R1_NOTR0 + 1)
554
  { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
555
 
556
/* Bang (bit reverse).  */
557
#define R1_BANG (R1_EVEN + 1)
558
  { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE },
559
 
560
/* Percent (modulo).  */
561
#define R1_PERCENT (R1_BANG + 1)
562
  { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE },
563
 
564
/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn.  */
565
#define R2 (R1_PERCENT + 1)
566
  { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
567
 
568
/* As above, but register 0 is not allowed.  */
569
#define R2_NOTR0 (R2 + 1)
570
  { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
571
 
572
/* Even register is allowed.  */
573
#define R2_EVEN (R2_NOTR0 + 1)
574
  { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
575
 
576
/* Reg2 in dispose instruction.  */
577
#define R2_DISPOSE      (R2_EVEN + 1)
578
  { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
579
 
580
/* The R3 field in a format 11, 12, C insn.  */
581
#define R3      (R2_DISPOSE + 1)
582
  { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
583
 
584
/* As above, but register 0 is not allowed.  */
585
#define R3_NOTR0        (R3 + 1)
586
  { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
587
 
588
/* As above, but odd number registers are not allowed.  */
589
#define R3_EVEN (R3_NOTR0 + 1)
590
  { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
591
 
592
/* As above, but register 0 is not allowed.  */
593
#define R3_EVEN_NOTR0   (R3_EVEN + 1)
594
  { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE },
595
 
596
/* Forth register in FPU Instruction.  */
597
#define R4      (R3_EVEN_NOTR0 + 1)
598
  { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE },
599
 
600
/* As above, but odd number registers are not allowed.  */
601
#define R4_EVEN (R4 + 1)
602
  { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
603
 
604
/* Stack pointer in prepare instruction.  */
605
#define SP      (R4_EVEN + 1)
606
  { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE },
607
 
608
/* EP Register.  */
609
#define EP      (SP + 1)
610
  { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE },
611
 
612
/* A list of registers in a prepare/dispose instruction.  */
613
#define LIST12  (EP + 1)
614
  { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
615
 
616
/* System register operands.  */
617
#define SR1     (LIST12 + 1)
618
  { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
619
 
620
/* The R2 field as a system register.  */
621
#define SR2     (SR1 + 1)
622
  { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
623
 
624
/* FPU CC bit position.  */
625
#define FFF (SR2 + 1)
626
  { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
627
 
628
/* The 4 bit condition code in a setf instruction.  */
629
#define CCCC    (FFF + 1)
630
  { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
631
 
632
/* Condition code in adf,sdf.  */
633
#define CCCC_NOTSA      (CCCC + 1)
634
  { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE },
635
 
636
/* Condition code in conditional moves.  */
637
#define MOVCC   (CCCC_NOTSA + 1)
638
  { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
639
 
640
/* Condition code in FPU.  */
641
#define FLOAT_CCCC      (MOVCC + 1)
642
  { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE },
643
 
644
/* The 1 bit immediate field in format C insn.  */
645
#define VI1     (FLOAT_CCCC + 1)
646
  { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE },
647
 
648
/* The 1 bit immediate field in format C insn.  */
649
#define VC1     (VI1 + 1)
650
  { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE },
651
 
652
/* The 2 bit immediate field in format C insn.  */
653
#define DI2     (VC1 + 1)
654
  { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE },
655
 
656
/* The 2 bit immediate field in format C insn.  */
657
#define VI2     (DI2 + 1)
658
  { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE },
659
 
660
/* The 2 bit immediate field in format C - DUP insn.  */
661
#define VI2DUP  (VI2 + 1)
662
  { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE },
663
 
664
/* The 3 bit immediate field in format 8 insn.  */
665
#define B3      (VI2DUP + 1)
666
  { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE },
667
 
668
/* The 3 bit immediate field in format C insn.  */
669
#define DI3     (B3 + 1)
670
  { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
671
 
672
/* The 3 bit immediate field in format C insn.  */
673
#define I3U     (DI3 + 1)
674
  { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE },
675
 
676
/* The 4 bit immediate field in format C insn.  */
677
#define I4U     (I3U + 1)
678
  { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
679
 
680
/* The 4 bit immediate field in fetrap.  */
681
#define I4U_NOTIMM0     (I4U + 1)
682
  { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE },
683
 
684
/* The unsigned disp4 field in a sld.bu.  */
685
#define D4U     (I4U_NOTIMM0 + 1)
686
  { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET },
687
 
688
/* The imm5 field in a format 2 insn.  */
689
#define I5      (D4U + 1)
690
  { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
691
 
692
/* The imm5 field in a format 11 insn.  */
693
#define I5DIV1  (I5 + 1)
694
  { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE },
695
 
696
#define I5DIV2  (I5DIV1 + 1)
697
  { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE },
698
 
699
#define I5DIV3  (I5DIV2 + 1)
700
  { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE },
701
 
702
/* The unsigned imm5 field in a format 2 insn.  */
703
#define I5U     (I5DIV3 + 1)
704
  { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE },
705
 
706
/* The imm5 field in a prepare/dispose instruction.  */
707
#define IMM5    (I5U + 1)
708
  { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE },
709
 
710
/* The unsigned disp5 field in a sld.hu.  */
711
#define D5_4U   (IMM5 + 1)
712
  { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET },
713
 
714
/* The IMM6 field in a callt instruction.  */
715
#define IMM6    (D5_4U + 1)
716
  { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET },
717
 
718
/* The signed disp7 field in a format 4 insn.  */
719
#define D7U     (IMM6 + 1)
720
  { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET },
721
 
722
/* The unsigned DISP8 field in a format 4 insn.  */
723
#define D8_7U   (D7U + 1)
724
  { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET },
725
 
726
/* The unsigned DISP8 field in a format 4 insn.  */
727
#define D8_6U   (D8_7U + 1)
728
  { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET },
729
 
730
/* The unsigned DISP8 field in a format 4 insn.  */
731
#define V8      (D8_6U + 1)
732
  { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE },
733
 
734
/* The imm9 field in a multiply word.  */
735
#define I9      (V8 + 1)
736
  { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
737
 
738
/* The unsigned imm9 field in a multiply word.  */
739
#define U9      (I9 + 1)
740
  { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE },
741
 
742
/* The DISP9 field in a format 3 insn.  */
743
#define D9      (U9 + 1)
744
  { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
745
 
746
/* The DISP9 field in a format 3 insn, relaxable.  */
747
#define D9_RELAX        (D9 + 1)
748
  { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
749
 
750
/* The imm16 field in a format 6 insn.  */
751
#define I16     (D9_RELAX + 1)
752
  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
753
 
754
/* The 16 bit immediate following a 32 bit instruction.  */
755
#define IMM16   (I16 + 1)
756
  { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_16 },
757
 
758
/* The 16 bit immediate following a 32 bit instruction.  */
759
#define IMM16LO (IMM16 + 1)
760
  { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_LO16 },
761
 
762
/* The hi 16 bit immediate following a 32 bit instruction.  */
763
#define IMM16HI (IMM16LO + 1)
764
  { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 },
765
 
766
/* The unsigned imm16 in a format 6 insn.  */
767
#define I16U    (IMM16HI + 1)
768
  { 16, 16, NULL, NULL, 0, BFD_RELOC_16 },
769
 
770
/* The disp16 field in a format 8 insn.  */
771
#define D16     (I16U + 1)
772
  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 },
773
 
774
/* The disp16 field in an format 7 unsigned byte load insn.  */
775
#define D16_16  (D16 + 1)
776
  { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET },
777
 
778
/* The disp16 field in a format 6 insn.  */
779
#define D16_15  (D16_16 + 1)
780
  { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 },
781
 
782
/* The unsigned DISP16 field in a format 7 insn.  */
783
#define D16_LOOP        (D16_15 + 1)
784
  { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL },
785
 
786
/* The DISP17 field in a format 7 insn.  */
787
#define D17_16  (D16_LOOP + 1)
788
  { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL },
789
 
790
/* The DISP22 field in a format 4 insn, relaxable.
791
   This _must_ follow D9_RELAX; the assembler assumes that the longer
792
   version immediately follows the shorter version for relaxing.  */
793
#define D22     (D17_16 + 1)
794
  { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL },
795
 
796
#define D23     (D22 + 1)
797
  { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
798
 
799
/* The 32 bit immediate following a 32 bit instruction.  */
800
#define IMM32   (D23 + 1)
801
  { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
802
 
803
#define D32_31  (IMM32 + 1)
804
  { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS },
805
 
806
#define D32_31_PCREL    (D32_31 + 1)
807
  { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
808
 
809
};
810
 
811
 
812
/* Reg - Reg instruction format (Format I).  */
813
#define IF1     {R1, R2}
814
 
815
/* Imm - Reg instruction format (Format II).  */
816
#define IF2     {I5, R2}
817
 
818
/* Conditional branch instruction format (Format III).  */
819
#define IF3     {D9_RELAX}
820
 
821
/* 3 operand instruction (Format VI).  */
822
#define IF6     {I16, R1, R2}
823
 
824
/* 3 operand instruction (Format VI).  */
825
#define IF6U    {I16U, R1, R2}
826
 
827
/* Conditional branch instruction format (Format VII).  */
828
#define IF7     {D17_16}
829
 
830
 
831
/* The opcode table.
832
 
833
   The format of the opcode table is:
834
 
835
   NAME         OPCODE                  MASK                   { OPERANDS }        MEMOP    PROCESSOR
836
 
837
   NAME is the name of the instruction.
838
   OPCODE is the instruction opcode.
839
   MASK is the opcode mask; this is used to tell the disassembler
840
     which bits in the actual opcode must match OPCODE.
841
   OPERANDS is the list of operands.
842
   MEMOP specifies which operand (if any) is a memory operand.
843
   PROCESSORS specifies which CPU(s) support the opcode.
844
 
845
   The disassembler reads the table in order and prints the first
846
   instruction which matches, so this table is sorted to put more
847
   specific instructions before more general instructions.  It is also
848
   sorted by major opcode.
849
 
850
   The table is also sorted by name.  This is used by the assembler.
851
   When parsing an instruction the assembler finds the first occurance
852
   of the name of the instruciton in this table and then attempts to
853
   match the instruction's arguments with description of the operands
854
   associated with the entry it has just found in this table.  If the
855
   match fails the assembler looks at the next entry in this table.
856
   If that entry has the same name as the previous entry, then it
857
   tries to match the instruction against that entry and so on.  This
858
   is how the assembler copes with multiple, different formats of the
859
   same instruction.  */
860
 
861
const struct v850_opcode v850_opcodes[] =
862
{
863
/* Standard instructions.  */
864
{ "add",        OP  (0x0e),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
865
{ "add",        OP  (0x12),             OP_MASK,                IF2,                    0, PROCESSOR_ALL },
866
 
867
{ "addi",       OP  (0x30),             OP_MASK,                IF6,                    0, PROCESSOR_ALL },
868
 
869
{ "adf",        two (0x07e0, 0x03a0),   two (0x07e0, 0x07e1),   {CCCC_NOTSA, R1, R2, R3},       0, PROCESSOR_V850E2_ALL },
870
 
871
{ "and",        OP (0x0a),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
872
 
873
{ "andi",       OP (0x36),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
874
 
875
        /* Signed integer.  */
876
{ "bge",        BOP (0xe),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
877
{ "bgt",        BOP (0xf),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
878
{ "ble",        BOP (0x7),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
879
{ "blt",        BOP (0x6),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
880
        /* Unsigned integer.  */
881
{ "bh",         BOP (0xb),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
882
{ "bl",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
883
{ "bnh",        BOP (0x3),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
884
{ "bnl",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
885
        /* Common.  */
886
{ "be",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
887
{ "bne",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
888
        /* Others.  */
889
{ "bc",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
890
{ "bf",         BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
891
{ "bn",         BOP (0x4),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
892
{ "bnc",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
893
{ "bnv",        BOP (0x8),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
894
{ "bnz",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
895
{ "bp",         BOP (0xc),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
896
{ "br",         BOP (0x5),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
897
{ "bsa",        BOP (0xd),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
898
{ "bt",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
899
{ "bv",         BOP (0x0),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
900
{ "bz",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
901
 
902
{ "bsh",        two (0x07e0, 0x0342),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
903
 
904
{ "bsw",        two (0x07e0, 0x0340),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
905
 
906
{ "callt",      one (0x0200),           one (0xffc0),           {IMM6},                 0, PROCESSOR_NOT_V850 },
907
 
908
{ "caxi",       two (0x07e0, 0x00ee),   two (0x07e0, 0x07ff),   {R1, R2, R3},           1, PROCESSOR_V850E2_ALL },
909
 
910
{ "clr1",       two (0x87c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          3, PROCESSOR_ALL },
911
{ "clr1",       two (0x07e0, 0x00e4),   two (0x07e0, 0xffff),   {R2, R1},               3, PROCESSOR_NOT_V850 },
912
 
913
{ "cmov",       two (0x07e0, 0x0320),   two (0x07e0, 0x07e1),   {MOVCC, R1, R2, R3},    0, PROCESSOR_NOT_V850 },
914
{ "cmov",       two (0x07e0, 0x0300),   two (0x07e0, 0x07e1),   {MOVCC, I5, R2, R3},    0, PROCESSOR_NOT_V850 },
915
 
916
{ "cmp",        OP  (0x0f),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
917
{ "cmp",        OP  (0x13),             OP_MASK,                IF2,                    0, PROCESSOR_ALL },
918
 
919
{ "ctret",      two (0x07e0, 0x0144),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_NOT_V850 },
920
 
921
{ "dbret",      two (0x07e0, 0x0146),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_NOT_V850 },
922
 
923
{ "dbtrap",     one (0xf840),           one (0xffff),           {0},                     0, PROCESSOR_NOT_V850 },
924
 
925
{ "di",         two (0x07e0, 0x0160),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_ALL },
926
 
927
{ "dispose",    two (0x0640, 0x0000),   two (0xffc0, 0x0000),   {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
928
{ "dispose",    two (0x0640, 0x0000),   two (0xffc0, 0x001f),   {IMM5, LIST12},         0, PROCESSOR_NOT_V850 },
929
 
930
{ "div",        two (0x07e0, 0x02c0),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
931
 
932
{ "divh",       two (0x07e0, 0x0280),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
933
{ "divh",       OP  (0x02),             OP_MASK,                {R1_NOTR0, R2_NOTR0},   0, PROCESSOR_ALL },
934
 
935
{ "divhn",      two (0x07e0, 0x0280),   two (0x07e0, 0x07c3),   {I5DIV1, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
936
 
937
{ "divhu",      two (0x07e0, 0x0282),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
938
 
939
{ "divhun",     two (0x07e0, 0x0282),   two (0x07e0, 0x07c3),   {I5DIV1, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
940
{ "divn",       two (0x07e0, 0x02c0),   two (0x07e0, 0x07c3),   {I5DIV2, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
941
 
942
{ "divq",       two (0x07e0, 0x02fc),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
943
 
944
{ "divqu",      two (0x07e0, 0x02fe),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
945
 
946
{ "divu",       two (0x07e0, 0x02c2),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
947
 
948
{ "divun",      two (0x07e0, 0x02c2),   two (0x07e0, 0x07c3),   {I5DIV2, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
949
 
950
{ "ei",         two (0x87e0, 0x0160),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_ALL },
951
 
952
{ "eiret",      two (0x07e0, 0x0148),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_V850E2_ALL },
953
 
954
{ "feret",      two (0x07e0, 0x014a),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_V850E2_ALL },
955
 
956
{ "fetrap",     one (0x0040),           one (0x87ff),           {I4U_NOTIMM0},          0, PROCESSOR_V850E2_ALL },
957
 
958
{ "halt",       two (0x07e0, 0x0120),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_ALL },
959
 
960
{ "hsh",        two (0x07e0, 0x0346),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_V850E2_ALL },
961
 
962
{ "hsw",        two (0x07e0, 0x0344),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
963
 
964
{ "jarl",       two (0x0780, 0x0000),   two (0x07c0, 0x0001),   {D22, R2_NOTR0},        0, PROCESSOR_ALL},
965
{ "jarl",       one (0x02e0),           one (0xffe0),           {D32_31_PCREL, R1_NOTR0},       0, PROCESSOR_V850E2_ALL },
966
/* Gas local alias of mov imm22(not defined in spec).  */
967
{ "jarl22",     two (0x0780, 0x0000),   two (0x07c0, 0x0001),   {D22, R2_NOTR0},        0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS},
968
/* Gas local alias of mov imm32(not defined in spec).  */
969
{ "jarl32",     one (0x02e0),           one (0xffe0),           {D32_31_PCREL, R1_NOTR0},       0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
970
{ "jarlw",      one (0x02e0),           one (0xffe0),           {D32_31_PCREL, R1_NOTR0},       0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
971
 
972
{ "jmp",        one (0x06e0),           one (0xffe0),           {D32_31, R1},           2, PROCESSOR_V850E2_ALL },
973
{ "jmp",        one (0x0060),           one (0xffe0),           {R1},                   1, PROCESSOR_ALL },
974
/* Gas local alias of jmp disp22(not defined in spec).  */
975
{ "jmp22",      one (0x0060),           one (0xffe0),           {R1},                   1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
976
/* Gas local alias of jmp disp32(not defined in spec).  */
977
{ "jmp32",      one (0x06e0),           one (0xffe0),           {D32_31, R1},           2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
978
{ "jmpw",       one (0x06e0),           one (0xffe0),           {D32_31, R1},           2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
979
 
980
{ "jr",         two (0x0780, 0x0000),   two (0xffc0, 0x0001),   {D22},                  0, PROCESSOR_ALL },
981
{ "jr",         one (0x02e0),           one (0xffff),           {D32_31_PCREL},         0, PROCESSOR_V850E2_ALL },
982
/* Gas local alias of mov imm22(not defined in spec).  */
983
{ "jr22",       two (0x0780, 0x0000),   two (0xffc0, 0x0001),   {D22},                  0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
984
/* Gas local alias of mov imm32(not defined in spec).  */
985
{ "jr32",       one (0x02e0),           one (0xffff),           {D32_31_PCREL},         0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
986
 
987
/* Alias of bcond (same as CA850).  */
988
{ "jgt",        BOP (0xf),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
989
{ "jge",        BOP (0xe),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
990
{ "jlt",        BOP (0x6),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
991
{ "jle",        BOP (0x7),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
992
        /* Unsigned integer.  */
993
{ "jh",         BOP (0xb),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
994
{ "jnh",        BOP (0x3),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
995
{ "jl",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
996
{ "jnl",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
997
        /* Common.  */
998
{ "je",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
999
{ "jne",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1000
        /* Others.  */
1001
{ "jv",         BOP (0x0),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1002
{ "jnv",        BOP (0x8),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1003
{ "jn",         BOP (0x4),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1004
{ "jp",         BOP (0xc),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1005
{ "jc",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1006
{ "jnc",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1007
{ "jz",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1008
{ "jnz",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1009
{ "jbr",        BOP (0x5),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
1010
 
1011
 
1012
{ "ldacc",      two (0x07e0, 0x0bc4),   two (0x07e0, 0xffff),   {R1, R2},               0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
1013
 
1014
{ "ld.b",       two (0x0700, 0x0000),   two (0x07e0, 0x0000),   {D16, R1, R2},          2, PROCESSOR_ALL },
1015
{ "ld.b",       two (0x0780, 0x0005),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL },
1016
{ "ld.b23",     two (0x0780, 0x0005),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1017
 
1018
{ "ld.bu",      two (0x0780, 0x0001),   two (0x07c0, 0x0001),   {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1019
{ "ld.bu",      two (0x07a0, 0x0005),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL },
1020
{ "ld.bu23",    two (0x07a0, 0x0005),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1021
 
1022
{ "ld.h",       two (0x0720, 0x0000),   two (0x07e0, 0x0001),   {D16_15, R1, R2},       2, PROCESSOR_ALL },
1023
{ "ld.h",       two (0x0780, 0x0007),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL },
1024
{ "ld.h23",     two (0x0780, 0x0007),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1025
 
1026
{ "ld.hu",      two (0x07e0, 0x0001),   two (0x07e0, 0x0001),   {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1027
{ "ld.hu",      two (0x07a0, 0x0007),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL },
1028
{ "ld.hu23",    two (0x07a0, 0x0007),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1029
 
1030
 
1031
{ "ld.w",       two (0x0720, 0x0001),   two (0x07e0, 0x0001),   {D16_15, R1, R2},       2, PROCESSOR_ALL },
1032
{ "ld.w",       two (0x0780, 0x0009),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL },
1033
{ "ld.w23",     two (0x0780, 0x0009),   two (0x07e0, 0x000f),   {D23, R1, R3},          2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1034
 
1035
{ "ldsr",       two (0x07e0, 0x0020),   two (0x07e0, 0xffff),   {R1, SR2},              0, PROCESSOR_ALL },
1036
 
1037
{ "macacc",     two (0x07e0, 0x0bc0),   two (0x07e0, 0xffff),   {R1, R2},               0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
1038
 
1039
{ "mac",        two (0x07e0, 0x03c0),   two (0x07e0, 0x0fe1),   {R1, R2, R3_EVEN, R4_EVEN},     0, PROCESSOR_V850E2_ALL },
1040
 
1041
{ "macu",       two (0x07e0, 0x03e0),   two (0x07e0, 0x0fe1),   {R1, R2, R3_EVEN, R4_EVEN},     0, PROCESSOR_V850E2_ALL },
1042
 
1043
{ "macuacc",    two (0x07e0, 0x0bc2),   two (0x07e0, 0xffff),   {R1, R2},               0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
1044
 
1045
{ "mov",        OP  (0x00),             OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
1046
{ "mov",        OP  (0x10),             OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
1047
{ "mov",        one (0x0620),           one (0xffe0),           {IMM32, R1},            0, PROCESSOR_NOT_V850 },
1048
/* Gas local alias of mov imm32(not defined in spec).  */
1049
{ "movl",       one (0x0620),           one (0xffe0),           {IMM32, R1},            0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS },
1050
 
1051
{ "movea",      OP  (0x31),             OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
1052
 
1053
{ "movhi",      OP  (0x32),             OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
1054
 
1055
{ "mul",        two (0x07e0, 0x0220),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
1056
{ "mul",        two (0x07e0, 0x0240),   two (0x07e0, 0x07c3),   {I9, R2, R3},           0, PROCESSOR_NOT_V850 },
1057
 
1058
{ "mulh",       OP  (0x17),             OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
1059
{ "mulh",       OP  (0x07),             OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
1060
 
1061
{ "mulhi",      OP  (0x37),             OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
1062
 
1063
{ "mulu",       two (0x07e0, 0x0222),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
1064
{ "mulu",       two (0x07e0, 0x0242),   two (0x07e0, 0x07c3),   {U9, R2, R3},           0, PROCESSOR_NOT_V850 },
1065
 
1066
{ "nop",        one (0x00),             one (0xffff),           {0},                     0, PROCESSOR_ALL },
1067
 
1068
{ "not",        OP (0x01),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1069
 
1070
{ "not1",       two (0x47c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          3, PROCESSOR_ALL },
1071
{ "not1",       two (0x07e0, 0x00e2),   two (0x07e0, 0xffff),   {R2, R1},               3, PROCESSOR_NOT_V850 },
1072
 
1073
{ "or",         OP (0x08),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1074
 
1075
{ "ori",        OP (0x34),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
1076
 
1077
{ "prepare",    two (0x0780, 0x0003),   two (0xffc0, 0x001f),   {LIST12, IMM5, SP},     0, PROCESSOR_NOT_V850 },
1078
{ "prepare",    two (0x0780, 0x000b),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 },
1079
{ "prepare",    two (0x0780, 0x0013),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 },
1080
{ "prepare",    two (0x0780, 0x001b),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM32},  0, PROCESSOR_NOT_V850 },
1081
{ "prepare",    two (0x0780, 0x0001),   two (0xffc0, 0x001f),   {LIST12, IMM5},         0, PROCESSOR_NOT_V850 },
1082
 
1083
{ "reti",       two (0x07e0, 0x0140),   two (0xffff, 0xffff),   {0},                     0, PROCESSOR_ALL },
1084
 
1085
{ "sar",        two (0x07e0, 0x00a2),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
1086
{ "sar",        OP (0x15),              OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
1087
{ "sar",        two (0x07e0, 0x00a0),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
1088
 
1089
{ "sasf",       two (0x07e0, 0x0200),   two (0x07f0, 0xffff),   {CCCC, R2},             0, PROCESSOR_NOT_V850 },
1090
 
1091
{ "satadd",     two (0x07e0, 0x03ba),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
1092
{ "satadd",     OP (0x11),              OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
1093
{ "satadd",     OP (0x06),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
1094
 
1095
{ "satsub",     two (0x07e0, 0x039a),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
1096
{ "satsub",     OP (0x05),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
1097
 
1098
{ "satsubi",    OP (0x33),              OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
1099
 
1100
{ "satsubr",    OP (0x04),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
1101
 
1102
{ "sbf",        two (0x07e0, 0x0380),   two (0x07e0, 0x07e1),   {CCCC_NOTSA, R1, R2, R3},       0, PROCESSOR_V850E2_ALL },
1103
 
1104
{ "sch0l",      two (0x07e0, 0x0364),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_V850E2_ALL },
1105
 
1106
{ "sch0r",      two (0x07e0, 0x0360),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_V850E2_ALL },
1107
 
1108
{ "sch1l",      two (0x07e0, 0x0366),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_V850E2_ALL },
1109
 
1110
{ "sch1r",      two (0x07e0, 0x0362),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_V850E2_ALL },
1111
 
1112
{ "sdivhn",     two (0x07e0, 0x0180),   two (0x07e0, 0x07c3),   {I5DIV3, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1113
{ "sdivhun",    two (0x07e0, 0x0182),   two (0x07e0, 0x07c3),   {I5DIV3, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1114
{ "sdivn",      two (0x07e0, 0x01c0),   two (0x07e0, 0x07c3),   {I5DIV3, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1115
{ "sdivun",     two (0x07e0, 0x01c2),   two (0x07e0, 0x07c3),   {I5DIV3, R1, R2, R3},   0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1116
 
1117
{ "set1",       two (0x07c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          3, PROCESSOR_ALL },
1118
{ "set1",       two (0x07e0, 0x00e0),   two (0x07e0, 0xffff),   {R2, R1},               3, PROCESSOR_NOT_V850 },
1119
 
1120
{ "setf",       two (0x07e0, 0x0000),   two (0x07f0, 0xffff),   {CCCC, R2},             0, PROCESSOR_ALL },
1121
 
1122
{ "shl",        two (0x07e0, 0x00c2),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
1123
{ "shl",        OP  (0x16),             OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
1124
{ "shl",        two (0x07e0, 0x00c0),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
1125
 
1126
{ "shr",        two (0x07e0, 0x0082),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_V850E2_ALL },
1127
{ "shr",        OP  (0x14),             OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
1128
{ "shr",        two (0x07e0, 0x0080),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
1129
 
1130
{ "sld.b",      one (0x0300),           one (0x0780),           {D7U,  EP,   R2},       2, PROCESSOR_ALL },
1131
 
1132
{ "sld.bu",     one (0x0060),           one (0x07f0),           {D4U,  EP,   R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1133
 
1134
{ "sld.h",      one (0x0400),           one (0x0780),           {D8_7U,EP,   R2},       2, PROCESSOR_ALL },
1135
 
1136
{ "sld.hu",     one (0x0070),           one (0x07f0),           {D5_4U,EP,   R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1137
 
1138
{ "sld.w",      one (0x0500),           one (0x0781),           {D8_6U,EP,   R2},       2, PROCESSOR_ALL },
1139
 
1140
{ "sst.b",      one (0x0380),           one (0x0780),           {R2,   D7U,  EP},       3, PROCESSOR_ALL },
1141
 
1142
{ "sst.h",      one (0x0480),           one (0x0780),           {R2,   D8_7U,EP},       3, PROCESSOR_ALL },
1143
 
1144
{ "sst.w",      one (0x0501),           one (0x0781),           {R2,   D8_6U,EP},       3, PROCESSOR_ALL },
1145
 
1146
{ "stacch",     two (0x07e0, 0x0bca),   two (0x07ff, 0xffff),   {R2},                   0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
1147
{ "staccl",     two (0x07e0, 0x0bc8),   two (0x07ff, 0xffff),   {R2},                   0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
1148
 
1149
{ "st.b",       two (0x0740, 0x0000),   two (0x07e0, 0x0000),   {R2, D16, R1},          3, PROCESSOR_ALL },
1150
{ "st.b",       two (0x0780, 0x000d),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL },
1151
{ "st.b23",     two (0x0780, 0x000d),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1152
 
1153
{ "st.h",       two (0x0760, 0x0000),   two (0x07e0, 0x0001),   {R2, D16_15, R1},       3, PROCESSOR_ALL },
1154
{ "st.h",       two (0x07a0, 0x000d),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL },
1155
{ "st.h23",     two (0x07a0, 0x000d),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1156
 
1157
{ "st.w",       two (0x0760, 0x0001),   two (0x07e0, 0x0001),   {R2, D16_15, R1},       3, PROCESSOR_ALL },
1158
{ "st.w",       two (0x0780, 0x000f),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL },
1159
{ "st.w23",     two (0x0780, 0x000f),   two (0x07e0, 0x000f),   {R3, D23, R1},          3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
1160
 
1161
{ "stsr",       two (0x07e0, 0x0040),   two (0x07e0, 0xffff),   {SR1, R2},              0, PROCESSOR_ALL },
1162
 
1163
{ "sub",        OP  (0x0d),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1164
 
1165
{ "subr",       OP  (0x0c),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1166
 
1167
{ "switch",     one (0x0040),           one (0xffe0),           {R1_NOTR0},             0, PROCESSOR_NOT_V850 },
1168
 
1169
{ "sxb",        one (0x00a0),           one (0xffe0),           {R1},                   0, PROCESSOR_NOT_V850 },
1170
 
1171
{ "sxh",        one (0x00e0),           one (0xffe0),           {R1},                   0, PROCESSOR_NOT_V850 },
1172
 
1173
{ "trap",       two (0x07e0, 0x0100),   two (0xffe0, 0xffff),   {I5U},                  0, PROCESSOR_ALL },
1174
 
1175
{ "tst",        OP (0x0b),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1176
 
1177
{ "tst1",       two (0xc7c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          3, PROCESSOR_ALL },
1178
{ "tst1",       two (0x07e0, 0x00e6),   two (0x07e0, 0xffff),   {R2, R1},               3, PROCESSOR_NOT_V850 },
1179
 
1180
{ "xor",        OP (0x09),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
1181
 
1182
{ "xori",       OP (0x35),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
1183
 
1184
{ "zxb",        one (0x0080),           one (0xffe0),           {R1},                   0, PROCESSOR_NOT_V850 },
1185
 
1186
{ "zxh",        one (0x00c0),           one (0xffe0),           {R1},                   0, PROCESSOR_NOT_V850 },
1187
 
1188
/* Floating point operation.  */
1189
{ "absf.d",     two (0x07e0, 0x0458),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1190
{ "absf.s",     two (0x07e0, 0x0448),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1191
{ "addf.d",     two (0x07e0, 0x0470),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1192
{ "addf.s",     two (0x07e0, 0x0460),   two (0x07e0, 0x07ff),   {R1, R2, R3},                           0, PROCESSOR_V850E2V3 },
1193
{ "ceilf.dl",   two (0x07e2, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1194
{ "ceilf.dul",  two (0x07f2, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1195
{ "ceilf.duw",  two (0x07f2, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1196
{ "ceilf.dw",   two (0x07e2, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1197
{ "ceilf.sl",   two (0x07e2, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1198
{ "ceilf.sul",  two (0x07f2, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1199
{ "ceilf.suw",  two (0x07f2, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1200
{ "ceilf.sw",   two (0x07e2, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1201
{ "ceilf.sw",   two (0x07e2, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1202
{ "cmovf.d",    two (0x07e0, 0x0410),   two (0x0fe1, 0x0ff1),   {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3 },
1203
/* Default value for FFF is 0(not defined in spec).  */
1204
{ "cmovf.d",    two (0x07e0, 0x0410),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0},      0, PROCESSOR_V850E2V3 },
1205
{ "cmovf.s",    two (0x07e0, 0x0400),   two (0x07e0, 0x07f1),   {FFF, R1, R2, R3_NOTR0},                0, PROCESSOR_V850E2V3 },
1206
/* Default value for FFF is 0(not defined in spec).  */
1207
{ "cmovf.s",    two (0x07e0, 0x0400),   two (0x07e0, 0x07ff),   {R1, R2, R3_NOTR0},                     0, PROCESSOR_V850E2V3 },
1208
{ "cmpf.d",     two (0x07e0, 0x0430),   two (0x0fe1, 0x87f1),   {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF},    0, PROCESSOR_V850E2V3 },
1209
{ "cmpf.d",     two (0x07e0, 0x0430),   two (0x0fe1, 0x87ff),   {FLOAT_CCCC, R2_EVEN, R1_EVEN},         0, PROCESSOR_V850E2V3 },
1210
{ "cmpf.s",     two (0x07e0, 0x0420),   two (0x07e0, 0x87f1),   {FLOAT_CCCC, R2, R1, FFF},              0, PROCESSOR_V850E2V3 },
1211
{ "cmpf.s",     two (0x07e0, 0x0420),   two (0x07e0, 0x87ff),   {FLOAT_CCCC, R2, R1},                   0, PROCESSOR_V850E2V3 },
1212
{ "cvtf.dl",    two (0x07e4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1213
{ "cvtf.ds",    two (0x07e3, 0x0452),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1214
{ "cvtf.dul",   two (0x07f4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1215
{ "cvtf.duw",   two (0x07f4, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1216
{ "cvtf.dw",    two (0x07e4, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1217
{ "cvtf.ld",    two (0x07e1, 0x0452),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1218
{ "cvtf.ls",    two (0x07e1, 0x0442),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1219
{ "cvtf.sd",    two (0x07e2, 0x0452),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1220
{ "cvtf.sl",    two (0x07e4, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1221
{ "cvtf.sul",   two (0x07f4, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1222
{ "cvtf.suw",   two (0x07f4, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1223
{ "cvtf.sw",    two (0x07e4, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1224
{ "cvtf.uld",   two (0x07f1, 0x0452),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1225
{ "cvtf.uls",   two (0x07f1, 0x0442),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1226
{ "cvtf.uwd",   two (0x07f0, 0x0452),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1227
{ "cvtf.uws",   two (0x07f0, 0x0442),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1228
{ "cvtf.wd",    two (0x07e0, 0x0452),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1229
{ "cvtf.ws",    two (0x07e0, 0x0442),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1230
{ "divf.d",     two (0x07e0, 0x047e),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1231
{ "divf.s",     two (0x07e0, 0x046e),   two (0x07e0, 0x07ff),   {R1_NOTR0, R2, R3},                     0, PROCESSOR_V850E2V3 },
1232
{ "floorf.dl",  two (0x07e3, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1233
{ "floorf.dul", two (0x07f3, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1234
{ "floorf.duw", two (0x07f3, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1235
{ "floorf.dw",  two (0x07e3, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1236
{ "floorf.sl",  two (0x07e3, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1237
{ "floorf.sul", two (0x07f3, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1238
{ "floorf.suw", two (0x07f3, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1239
{ "floorf.sw",  two (0x07e3, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1240
{ "maddf.s",    two (0x07e0, 0x0500),   two (0x07e0, 0x0761),   {R1, R2, R3, R4},                       0, PROCESSOR_V850E2V3 },
1241
{ "maxf.d",     two (0x07e0, 0x0478),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1242
{ "maxf.s",     two (0x07e0, 0x0468),   two (0x07e0, 0x07ff),   {R1, R2, R3},                           0, PROCESSOR_V850E2V3 },
1243
{ "minf.d",     two (0x07e0, 0x047a),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1244
{ "minf.s",     two (0x07e0, 0x046a),   two (0x07e0, 0x07ff),   {R1, R2, R3},                           0, PROCESSOR_V850E2V3 },
1245
{ "msubf.s",    two (0x07e0, 0x0520),   two (0x07e0, 0x0761),   {R1, R2, R3, R4},                       0, PROCESSOR_V850E2V3 },
1246
{ "mulf.d",     two (0x07e0, 0x0474),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1247
{ "mulf.s",     two (0x07e0, 0x0464),   two (0x07e0, 0x07ff),   {R1, R2, R3},                           0, PROCESSOR_V850E2V3 },
1248
{ "negf.d",     two (0x07e1, 0x0458),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1249
{ "negf.s",     two (0x07e1, 0x0448),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1250
{ "nmaddf.s",   two (0x07e0, 0x0540),   two (0x07e0, 0x0761),   {R1, R2, R3, R4},                       0, PROCESSOR_V850E2V3 },
1251
{ "nmsubf.s",   two (0x07e0, 0x0560),   two (0x07e0, 0x0761),   {R1, R2, R3, R4},                       0, PROCESSOR_V850E2V3 },
1252
{ "recipf.d",   two (0x07e1, 0x045e),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1253
{ "recipf.s",   two (0x07e1, 0x044e),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1254
 
1255
{ "roundf.dl",  two (0x07e0, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1256
{ "roundf.dul", two (0x07f0, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1257
{ "roundf.duw", two (0x07f0, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1258
{ "roundf.dw",  two (0x07e0, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1259
{ "roundf.sl",  two (0x07e0, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1260
{ "roundf.sul", two (0x07f0, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1261
{ "roundf.suw", two (0x07f0, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1262
{ "roundf.sw",  two (0x07e0, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
1263
 
1264
{ "rsqrtf.d",   two (0x07e2, 0x045e),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1265
{ "rsqrtf.s",   two (0x07e2, 0x044e),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1266
{ "sqrtf.d",    two (0x07e0, 0x045e),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1267
{ "sqrtf.s",    two (0x07e0, 0x044e),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1268
{ "subf.d",     two (0x07e0, 0x0472),   two (0x0fe1, 0x0fff),   {R1_EVEN, R2_EVEN, R3_EVEN},            0, PROCESSOR_V850E2V3 },
1269
{ "subf.s",     two (0x07e0, 0x0462),   two (0x07e0, 0x07ff),   {R1, R2, R3},                           0, PROCESSOR_V850E2V3 },
1270
{ "trfsr",      two (0x07e0, 0x0400),   two (0xffff, 0xfff1),   {FFF},                                  0, PROCESSOR_V850E2V3 },
1271
{ "trfsr",      two (0x07e0, 0x0400),   two (0xffff, 0xffff),   {0},                                     0, PROCESSOR_V850E2V3 },
1272
{ "trncf.dl",   two (0x07e1, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1273
{ "trncf.dul",  two (0x07f1, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
1274
{ "trncf.duw",  two (0x07f1, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1275
{ "trncf.dw",   two (0x07e1, 0x0450),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
1276
{ "trncf.sl",   two (0x07e1, 0x0444),   two (0x07ff, 0x0fff),   {R2, R3_EVEN},                          0, PROCESSOR_V850E2V3 },
1277
{ "trncf.sul",  two (0x07f1, 0x0444),   two (0x07ff, 0x07ff),   {R2, R3},                       0, PROCESSOR_V850E2V3 },
1278
{ "trncf.suw",  two (0x07f1, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1279
{ "trncf.sw",   two (0x07e1, 0x0440),   two (0x07ff, 0x07ff),   {R2, R3},                               0, PROCESSOR_V850E2V3 },
1280
 
1281
  /* Special instruction (from gdb) mov 1, r0.  */
1282
{ "breakpoint", one (0x0001),           one (0xffff),           {UNUSED},                               0, PROCESSOR_ALL },
1283
 
1284
  /* V850e2-v3.  */
1285
{ "synce",      one (0x001d),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 },
1286
{ "syncm",      one (0x001e),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 },
1287
{ "syncp",      one (0x001f),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 },
1288
{ "syscall",    two (0xd7e0, 0x0160),   two (0xffe0, 0xc7ff),   {V8},                                   0, PROCESSOR_V850E2V3 },
1289
  /* Alias of syncp.  */
1290
{ "sync",       one (0x001f),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_ALIAS },
1291
{ "rmtrap",     one (0xf040),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 },
1292
 
1293
 
1294
{ "rie",        one (0x0040),           one (0xffff),           {0},                                     0, PROCESSOR_V850E2V3 },
1295
{ "rie",        two (0x07f0, 0x0000),   two (0x07f0, 0xffff),   {0},                                     0, PROCESSOR_V850E2V3 },
1296
 
1297
{ 0, 0, 0, {0}, 0, 0 },
1298
} ;
1299
 
1300
const int v850_num_opcodes =
1301
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);

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