Subversion Repositories openarty

////////////////////////////////////////////////////////////////////////////////

//

// Filename:    wbddrsdram.v

//

// Project:     A wishbone controlled DDR3 SDRAM memory controller.

// Used in:     OpenArty, an entirely open SoC based upon the Arty platform

//

// Purpose:     To control a DDR3-1333 (9-9-9) memory from a wishbone bus.

//              In our particular implementation, there will be two command

//      clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred

//      per FPGA clock.  However, since the memory is focused around 128-bit

//      word transfers, attempts to transfer other than adjacent 64-bit words

//      will (of necessity) suffer stalls.  Please see the documentation for

//      more details of how this controller works.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory, run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

// Possible commands to the DDR3 memory.  These consist of settings for the

// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.

`define DDR_MRSET       4'b0000

`define DDR_REFRESH     4'b0001

`define DDR_PRECHARGE   4'b0010

`define DDR_ACTIVATE    4'b0011

`define DDR_WRITE       4'b0100

`define DDR_READ        4'b0101

`define DDR_ZQS         4'b0110

`define DDR_NOOP        4'b0111

//`define       DDR_DESELECT    4'b1???

//

// In this controller, 24-bit commands tend to be passed around.  These 

// 'commands' are bit fields.  Here we specify the bits associated with

// the bit fields.

`define DDR_RSTDONE     24      // End the reset sequence?

`define DDR_RSTTIMER    23      // Does this reset command take multiple clocks?

`define DDR_RSTBIT      22      // Value to place on reset_n

`define DDR_CKEBIT      21      // Should this reset command set CKE?

//

// Refresh command bit fields

`define DDR_NEEDREFRESH 23

`define DDR_RFTIMER     22

`define DDR_RFBEGIN     21

//

`define DDR_CMDLEN      21

`define DDR_CSBIT       20

`define DDR_RASBIT      19

`define DDR_CASBIT      18

`define DDR_WEBIT       17

`define DDR_NOPTIMER    16      // Steal this from BA bits

`define DDR_BABITS      3       // BABITS are really from 18:16, they are 3 bits

`define DDR_ADDR_BITS   14

//

//

module  wbddrsdram(i_clk, i_reset,

                // Wishbone inputs

                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,

                        i_wb_sel,

                // Wishbone outputs

                o_wb_ack, o_wb_stall, o_wb_data,

                // Memory command wires

                o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,

                o_ddr_cmd_a, o_ddr_cmd_b,

                // And the data wires to go with them ....

                o_ddr_data, i_ddr_data);

        // These parameters are not really meant for adjusting from the

        // top level.  These are more internal variables, recorded here

        // so that things can be automatically adjusted without much

        // problem.

        parameter       CKRP = 3;

        parameter       BUSNOW = 4, BUSREG = BUSNOW-1;

        // The commands (above) include (in this order):

        //      o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,

        //      o_ddr_dqs, o_ddr_dm, o_ddr_odt

        input           i_clk,  // *MUST* be at 200 MHz for this to work

                        i_reset;

        // Wishbone inputs

        input           i_wb_cyc, i_wb_stb, i_wb_we;

        input   [24:0]   i_wb_addr;      // Identifies a 64-bit word of interest

        input   [63:0]   i_wb_data;

        input   [7:0]    i_wb_sel;

        // Wishbone responses/outputs

        output  reg             o_wb_ack, o_wb_stall;

        output  reg     [63:0]   o_wb_data;

        // DDR memory command wires

        output  reg     o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe;

        // CMDs are:

        //       4 bits of CS, RAS, CAS, WE

        //       3 bits of bank

        //      14 bits of Address

        //       1 bit  of DQS (strobe active, or not)

        //       4 bits of mask (one per byte)

        //       1 bit  of ODT

        //      ----

        //      27 bits total

        output  wire    [26:0]   o_ddr_cmd_a, o_ddr_cmd_b;

        output  reg     [63:0]   o_ddr_data;

        input           [63:0]   i_ddr_data;

//////////

//

//

//      Reset Logic

//

//

//////////

//

//

// Reset logic should be simple, and is given as follows:

// note that it depends upon a ROM memory, reset_mem, and an address into that

// memory: reset_address.  Each memory location provides either a "command" to

// the DDR3 SDRAM, or a timer to wait until the next command.  Further, the

// timer commands indicate whether or not the command during the timer is to

// be set to idle, or whether the command is instead left as it was.

        reg             reset_override, reset_ztimer, maintenance_override;

        reg     [4:0]    reset_address;

        reg     [(`DDR_CMDLEN-1):0]      reset_cmd, cmd_a, cmd_b, refresh_cmd,

                                        maintenance_cmd;

        reg     [24:0]   reset_instruction;

        reg     [16:0]   reset_timer;

        initial reset_override = 1'b1;

        initial reset_address  = 5'h0;

        always @(posedge i_clk)

                if (i_reset)

                begin

                        reset_override <= 1'b1;

                        reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};

                end else if (reset_ztimer)

                begin

                        if (reset_instruction[`DDR_RSTDONE])

                                reset_override <= 1'b0;

                        reset_cmd <= reset_instruction[20:0];

                end

        initial reset_ztimer = 1'b0;    // Is the timer zero?

        initial reset_timer = 17'h02;

        always @(posedge i_clk)

                if (i_reset)

                begin

                        reset_ztimer <= 1'b0;

                        reset_timer <= 17'd2;

                end else if (!reset_ztimer)

                begin

                        reset_ztimer <= (reset_timer == 17'h01);

                        reset_timer <= reset_timer - 17'h01;

                end else if (reset_instruction[`DDR_RSTTIMER])

                begin

                        reset_ztimer <= 1'b0;

                        reset_timer <= reset_instruction[16:0];

                end

        wire    [16:0]   w_ckXPR, w_ckRFC_first;

        wire    [13:0]   w_MR0, w_MR1, w_MR2;

        assign w_MR0 = 14'h0420;

        assign w_MR1 = 14'h0044;

        assign w_MR2 = 14'h0040;

        assign w_ckXPR = 17'd68;  // Table 68, p186

        assign  w_ckRFC_first = 17'd30; // i.e. 64 nCK, or ckREFI

        always @(posedge i_clk)

                // DONE, TIMER, RESET, CKE, 

                if (i_reset)

                        reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };

                else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??

                // 1. Reset asserted (active low) for 200 us. (@200MHz)

                5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };

                // 2. Reset de-asserted, wait 500 us before asserting CKE

                5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };

                // 3. Assert CKE, wait minimum of Reset CKE Exit time

                5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };

                // 4. Set MR2.  (4 nCK, no TIMER, but needs a NOOP cycle)

                5'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };

                5'h4: reset_instruction <= { 4'h3, `DDR_NOOP,  17'h00 };

                // 5. Set MR1.  (4 nCK, no TIMER, but needs a NOOP cycle)

                5'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };

                5'h6: reset_instruction <= { 4'h3, `DDR_NOOP,  17'h00 };

                // 6. Set MR0

                5'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };

                // 7. Wait 12 clocks

                5'h8: reset_instruction <= { 4'h7, `DDR_NOOP,  17'd10 };

                // 8. Issue a ZQCL command to start ZQ calibration, A10 is high

                5'h9: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};

                //11.Wait for both tDLLK and tZQinit completed, both are

                // 512 cks. Of course, since every one of these commands takes

                // two clocks, we wait for half as many clocks (minus two for

                // our timer logic)

                5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd254 };

                // 12. Precharge all command

                5'hb: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };

                // 13. Wait for the precharge to complete.  A count of one,

                // will have us waiting (1+2)*2 or 6 clocks, so we should be

                // good here.

                5'hc: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd1 };

                // 14. A single Auto Refresh commands

                5'hd: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };

                // 15. Wait for the auto refresh to complete

                5'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };

                default:

                        reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };

                endcase

        initial reset_address = 5'h0;

        always @(posedge i_clk)

                if (i_reset)

                        reset_address <= 5'h1;

                else if ((reset_ztimer)&&(reset_override))

                        reset_address <= reset_address + 5'h1;

//////////

//

//

//      Refresh Logic

//

//

//////////

//

//

//

// Okay, let's investigate when we need to do a refresh.  Our plan will be to

// do a single refreshes every tREFI seconds.  We will not push off refreshes,

// nor pull them in--for simplicity.  tREFI = 7.8us, but it is a parameter

// in the number of clocks.  In our case, 7.8us / 5ns = 1560 clocks (not nCK!)

//

// Note that 160ns are needed between refresh commands (JEDEC, p172), or

// 32 clocks @200MHz.  After this time, no more refreshes will be needed for

// (1560-32) clocks (@ 200 MHz).

//

// This logic is very similar to the refresh logic, both use a memory as a 

// script.

//

        reg             need_refresh;

        reg             refresh_ztimer;

        reg     [16:0]   refresh_counter;

        reg     [2:0]    refresh_addr;

        reg     [23:0]   refresh_instruction;

        always @(posedge i_clk)

                if (reset_override)

                        refresh_addr <= 3'hf;

                else if (refresh_ztimer)

                        refresh_addr <= refresh_addr + 3'h1;

                else if (refresh_instruction[`DDR_RFBEGIN])

                        refresh_addr <= 3'h0;

        always @(posedge i_clk)

                if (reset_override)

                begin

                        refresh_ztimer <= 1'b1;

                        refresh_counter <= 17'd0;

                end else if (!refresh_ztimer)

                begin

                        refresh_ztimer <= (refresh_counter == 17'h1);

                        refresh_counter <= (refresh_counter - 17'h1);

                end else if (refresh_instruction[`DDR_RFTIMER])

                begin

                        refresh_ztimer <= 1'b0;

                        refresh_counter <= refresh_instruction[16:0];

                end

        wire    [16:0]   w_ckREFI;

        assign  w_ckREFI = 17'd1560; // == 6240/4

        wire    [16:0]   w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,

                        w_precharge_to_refresh;

        // We need to wait for the bus to become idle from whatever state

        // it is in.  The difficult time for this measurement is assuming

        // a write was just given.  In that case, we need to wait for the

        // write to complete, and then to wait an additional tWR (write

        // recovery time) or 6 nCK clocks from the end of the write.  This

        // works out to seven idle bus cycles from the time of the write

        // command, or a count of 5 (7-2).

        assign  w_wait_for_idle = 17'd5;        //

        assign  w_precharge_to_refresh = 17'd1; // = 3-2

        assign  w_ckREFI_left[16:0] = 17'd1560   // The full interval

                                -17'd32         // Min what we've already waited

                                -w_wait_for_idle

                                -w_precharge_to_refresh-17'd12;

        assign  w_ckRFC_nxt[16:0] = 17'd32-17'd2;

        always @(posedge i_clk)

        if (refresh_ztimer)

                case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)

                // First, a number of clocks needing no refresh

                3'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFI_left };

                // Then, we take command of the bus and wait for it to be

                // guaranteed idle

                3'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, w_wait_for_idle };

                // Once the bus is idle, all commands complete, and a minimum

                // recovery time given, we can issue a precharge all command

                3'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };

                // Now we need to wait tRP = 3 clocks (6 nCK)

                3'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, w_precharge_to_refresh };

                3'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };

                3'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC_nxt };

                default:

                        refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };

                endcase

        // Note that we don't need to check if (reset_override) here since

        // refresh_ztimer will always be true if (reset_override)--in other

        // words, it will be true for many, many, clocks--enough for this

        // logic to settle out.

        always @(posedge i_clk)

                if (refresh_ztimer)

                        refresh_cmd <= refresh_instruction[20:0];

        always @(posedge i_clk)

                if (refresh_ztimer)

                        need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];

/*

        input                   i_clk, i_reset;

        // Wishbone inputs

        input                   i_wb_cyc, i_wb_stb, i_wb_we;

        input           [25:0]  i_wb_addr;

        input           [31:0]  i_wb_data;

        // Wishbone outputs

        output  reg             o_wb_ack;

        output  reg             o_wb_stall;

        output  reg     [31:0]  o_wb_data;

        // DDR3 RAM Controller

        output  reg             o_ddr_reset_n, o_ddr_cke;

        // Control outputs

        output  wire            o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;

        // DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow

        output  wire            o_ddr_dqs;

        output  reg             o_ddr_odt;

        output  wire            o_ddr_bus_oe;

        // Address outputs

        output  wire    [13:0]  o_ddr_addr;

        output  wire    [2:0]   o_ddr_ba;

        // And the data inputs and outputs

        output  reg     [31:0]  o_ddr_data;

        input           [31:0]  i_ddr_data;

*/

        reg     [1:0]    drive_dqs;

        // Our chosen timing doesn't require any more resolution than one

        // bus clock for ODT.  (Of course, this really isn't necessary, since

        // we aren't using ODT as per the MRx registers ... but we keep it

        // around in case we change our minds later.)

        reg             ddr_odt;

        reg     [7:0]    ddr_dm;

        // The pending transaction

        reg     [63:0]   r_data;

        reg             r_pending, r_we;

        reg     [24:0]   r_addr;

        reg     [13:0]   r_row;

        reg     [2:0]    r_bank;

        reg     [9:0]    r_col;

        reg             r_sub;

        reg     [7:0]    r_sel;

        // The pending transaction, one further into the pipeline.  This is

        // the stage where the read/write command is actually given to the

        // interface if we haven't stalled.

        reg     [63:0]   s_data;

        reg             s_pending, s_we; // , s_match;

        reg     [24:0]   s_addr;

        reg     [13:0]   s_row, s_nxt_row;

        reg     [2:0]    s_bank, s_nxt_bank;

        reg     [9:0]    s_col;

        reg             s_sub;

        reg     [7:0]    s_sel;

        // Can the pending transaction be satisfied with the current (ongoing)

        // transaction?

        reg             m_move, m_match, m_pending, m_we;

        reg     [24:0]   m_addr;

        reg     [13:0]   m_row;

        reg     [2:0]    m_bank;

        reg     [9:0]    m_col;

        reg     [1:0]    m_sub;

        // Can we preload the next bank?

        reg     [13:0]   r_nxt_row;

        reg     [2:0]    r_nxt_bank;

        reg     need_close_bank, need_close_this_bank,

                        last_close_bank, maybe_close_next_bank,

                        last_maybe_close,

                need_open_bank, last_open_bank, maybe_open_next_bank,

                        last_maybe_open,

                valid_bank;

        reg     [(`DDR_CMDLEN-1):0]      close_bank_cmd, activate_bank_cmd,

                                        maybe_close_cmd, maybe_open_cmd, rw_cmd;

        reg             rw_sub;

        reg             rw_we;

        wire    w_this_closing_bank, w_this_opening_bank,

                w_this_maybe_close, w_this_maybe_open,

                w_this_rw_move;

        reg     last_closing_bank, last_opening_bank;

        wire    w_need_close_this_bank, w_need_open_bank,

                w_r_valid, w_s_valid, w_s_match;

//////////

//

//

//      Open Banks

//

//

//////////

//

//

//

// Let's keep track of any open banks.  There are 8 of them to keep track of.

//

//      A precharge requires 3 clocks at 200MHz to complete.

//      An activate also requires 3 clocks at 200MHz to complete.

//      Precharges are not allowed until the maximum of:

//              2 clocks (200 MHz) after a read command

//              8 clocks after a write command

//

//

        wire    w_precharge_all;

        reg     [CKRP:0] bank_status     [0:7];

        reg     [13:0]   bank_address    [0:7];

        reg     [3:0]    bank_wr_ck      [0:7]; // tWTR

        reg             bank_wr_ckzro   [0:7]; // tWTR

        reg     [7:0]    bank_open;

        reg     [7:0]    bank_closed;

        wire    [3:0]    write_recycle_clocks;

        assign  write_recycle_clocks = 4'h8;

        initial bank_open   = 0;

        initial bank_closed = 8'hff;

        always @(posedge i_clk)

        begin

                bank_status[0] <= { bank_status[0][(CKRP-1):0], bank_status[0][0] };

                bank_status[1] <= { bank_status[1][(CKRP-1):0], bank_status[1][0] };

                bank_status[2] <= { bank_status[2][(CKRP-1):0], bank_status[2][0] };

                bank_status[3] <= { bank_status[3][(CKRP-1):0], bank_status[3][0] };

                bank_status[4] <= { bank_status[4][(CKRP-1):0], bank_status[4][0] };

                bank_status[5] <= { bank_status[5][(CKRP-1):0], bank_status[5][0] };

                bank_status[6] <= { bank_status[6][(CKRP-1):0], bank_status[6][0] };

                bank_status[7] <= { bank_status[7][(CKRP-1):0], bank_status[7][0] };

                bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-4'h1):4'h0;

                bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-4'h1):4'h0;

                bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-4'h1):4'h0;

                bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-4'h1):4'h0;

                bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-4'h1):4'h0;

                bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-4'h1):4'h0;

                bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-4'h1):4'h0;

                bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-4'h1):4'h0;

                bank_wr_ckzro[0] <= (bank_wr_ck[0][3:1]==3'b00);

                bank_wr_ckzro[1] <= (bank_wr_ck[1][3:1]==3'b00);

                bank_wr_ckzro[2] <= (bank_wr_ck[2][3:1]==3'b00);

                bank_wr_ckzro[3] <= (bank_wr_ck[3][3:1]==3'b00);

                bank_wr_ckzro[4] <= (bank_wr_ck[4][3:1]==3'b00);

                bank_wr_ckzro[5] <= (bank_wr_ck[5][3:1]==3'b00);

                bank_wr_ckzro[6] <= (bank_wr_ck[6][3:1]==3'b00);

                bank_wr_ckzro[7] <= (bank_wr_ck[7][3:1]==3'b00);

                bank_open[0] <= (bank_status[0][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[1] <= (bank_status[1][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[2] <= (bank_status[2][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[3] <= (bank_status[3][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[4] <= (bank_status[4][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[5] <= (bank_status[5][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[6] <= (bank_status[6][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_open[7] <= (bank_status[7][(CKRP-2):0] =={(CKRP-1){1'b1}});

                bank_closed[0] <= (bank_status[0][(CKRP-3):0] == 0);

                bank_closed[1] <= (bank_status[1][(CKRP-3):0] == 0);

                bank_closed[2] <= (bank_status[2][(CKRP-3):0] == 0);

                bank_closed[3] <= (bank_status[3][(CKRP-3):0] == 0);

                bank_closed[4] <= (bank_status[4][(CKRP-3):0] == 0);

                bank_closed[5] <= (bank_status[5][(CKRP-3):0] == 0);

                bank_closed[6] <= (bank_status[6][(CKRP-3):0] == 0);

                bank_closed[7] <= (bank_status[7][(CKRP-3):0] == 0);

                if (w_this_rw_move)

                        bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 4'h0

                                : write_recycle_clocks;

                if (maintenance_override)

                begin

                        bank_status[0][0] <= 1'b0;

                        bank_status[1][0] <= 1'b0;

                        bank_status[2][0] <= 1'b0;

                        bank_status[3][0] <= 1'b0;

                        bank_status[4][0] <= 1'b0;

                        bank_status[5][0] <= 1'b0;

                        bank_status[6][0] <= 1'b0;

                        bank_status[7][0] <= 1'b0;

                        bank_open   <= 0;

                        bank_closed <= 8'hff;

                end else if (need_close_bank)

                begin

                        bank_status[close_bank_cmd[16:14]]

                                <= { bank_status[close_bank_cmd[16:14]][(CKRP-1):0], 1'b0 };

                        bank_open[close_bank_cmd[16:14]] <= 1'b0;

                end else if (need_open_bank)

                begin

                        bank_status[activate_bank_cmd[16:14]]

                                <= { bank_status[activate_bank_cmd[16:14]][(CKRP-1):0], 1'b1 };

                        bank_closed[activate_bank_cmd[16:14]] <= 1'b0;

                end else if (valid_bank)

                        ; // Read/write command was issued.  This neither opens

                        // nor closes any banks, and hence it needs no logic

                        // here

                else if (maybe_close_next_bank)

                begin

                        bank_status[maybe_close_cmd[16:14]]

                                <= { bank_status[maybe_close_cmd[16:14]][(CKRP-1):0], 1'b0 };

                        bank_open[maybe_close_cmd[16:14]] <= 1'b0;

                end else if (maybe_open_next_bank)

                begin

                        bank_status[maybe_open_cmd[16:14]]

                                <= { bank_status[maybe_open_cmd[16:14]][(CKRP-1):0], 1'b1 };

                        bank_closed[maybe_open_cmd[16:14]] <= 1'b0;

                end

        end