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toni32 |
/* MODULE: openfire_cpu
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DESCRIPTION: This is the top module for the openfire processor, instantiating
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the fetch, decode, execute, pipeline_ctrl, and register file modules.
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AUTHOR:
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Stephen Douglas Craven
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Configurable Computing Lab
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Virginia Tech
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scraven@vt.edu
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REVISION HISTORY:
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Revision 0.2, 8/10/2005 SDC
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Initial release
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Revision 0.3, 12/17/2005 SDC
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Fixed PC size bug
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Revision 0.4 27/03/2007 Antonio J. Anton
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Improved (interrupts, exceptions, msr)
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Ripup of memory signals
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COPYRIGHT:
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Copyright (c) 2005 Stephen Douglas Craven
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE. */
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`include "openfire_define.v"
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module openfire_cpu (
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clock, reset,
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`ifdef ENABLE_INTERRUPTS
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interrupt,
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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dmem_alignment_exception,
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`endif
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dmem_addr, dmem_data_in, dmem_data_out, // ins/data ports
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dmem_we, dmem_re, dmem_input_sel, dmem_done,
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imem_addr, imem_data_in, imem_re, imem_done
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);
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input clock;
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input reset;
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input [31:0] dmem_data_in;
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input [31:0] imem_data_in;
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input dmem_done;
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input imem_done;
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`ifdef ENABLE_INTERRUPTS
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input interrupt;
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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input dmem_alignment_exception;
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`endif
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output [31:0] dmem_data_out;
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output [31:0] dmem_addr;
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output [31:0] imem_addr;
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output imem_re;
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output dmem_we;
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output dmem_re;
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output [1:0] dmem_input_sel; //0=byte, 1=hw, 2=word
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wire branch_taken;
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wire [`A_SPACE+1:0] pc_branch;
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wire [`A_SPACE+1:0] pc_decode;
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wire [`A_SPACE+1:0] pc_exe_rf;
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wire [31:0] instruction;
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wire [4:0] regA_addr;
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wire [4:0] regB_addr;
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wire [4:0] regD_addr;
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wire [31:0] immediate;
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wire [2:0] alu_inputA_sel;
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wire [1:0] alu_inputB_sel;
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wire [1:0] alu_inputC_sel;
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wire [3:0] alu_fns_sel;
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wire [2:0] comparator_fns_sel;
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wire we_alu_branch;
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wire we_load;
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wire we_store;
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wire we_regfile;
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wire [3:0] regfile_input_sel;
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wire delay_bit;
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wire [31:0] result;
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wire [31:0] regA;
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wire [31:0] regB;
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wire [31:0] regD;
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wire update_carry;
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wire stall_exe;
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wire stall_decode;
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wire stall_fetch;
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wire instr_complete;
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wire flush;
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wire branch_instr;
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`ifdef ENABLE_MSR_BIP
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wire update_msr_bip;
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wire value_msr_bip;
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`endif
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`ifdef ENABLE_INTERRUPTS
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wire int_ip;
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wire int_dc;
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wire set_msr_ie;
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`endif
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`ifdef ENABLE_EXCEPTIONS
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wire reset_msr_eip;
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wire insert_exception;
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`endif
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`ifdef ENABLE_OPCODE_EXCEPTION
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wire opcode_exception;
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`endif
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`ifdef ENABLE_MSR_OPCODES
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wire rS_update;
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`endif
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openfire_fetch FETCH (
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.stall(stall_fetch),
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.clock(clock),
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.reset(reset),
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.branch_taken(branch_taken),
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.pc_branch(pc_branch),
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.idata(imem_data_in),
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.imem_addr(imem_addr),
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.imem_re(imem_re),
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.pc_decode(pc_decode),
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.instruction(instruction)
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);
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openfire_decode DECODE (
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`ifdef ENABLE_MSR_BIP
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.update_msr_bip(update_msr_bip),
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.value_msr_bip(value_msr_bip),
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`endif
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`ifdef ENABLE_INTERRUPTS
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.int_ip(int_ip),
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.int_dc(int_dc),
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.set_msr_ie(set_msr_ie),
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`endif
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`ifdef ENABLE_EXCEPTIONS
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.reset_msr_eip(reset_msr_eip),
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.insert_exception(insert_exception),
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`endif
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`ifdef ENABLE_OPCODE_EXCEPTION
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.opcode_exception(opcode_exception),
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`endif
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`ifdef ENABLE_MSR_OPCODES
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.rS_update(rs_update),
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`endif
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.clock(clock),
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.stall(stall_decode),
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.reset(reset),
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.pc_decode(pc_decode),
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.instruction(instruction),
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.regA_addr(regA_addr),
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.regB_addr(regB_addr),
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.regD_addr(regD_addr),
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.immediate(immediate),
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.pc_exe(pc_exe_rf),
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.alu_inputA_sel(alu_inputA_sel),
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.alu_inputB_sel(alu_inputB_sel),
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.alu_inputC_sel(alu_inputC_sel),
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.alu_fns_sel(alu_fns_sel),
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.comparator_fns_sel(comparator_fns_sel),
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.branch_instr(branch_instr),
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.we_alu_branch(we_alu_branch),
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.we_load(we_load),
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.we_store(we_store),
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.regfile_input_sel(regfile_input_sel),
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.dmem_input_sel(dmem_input_sel),
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.flush(flush),
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.delay_bit(delay_bit),
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.update_carry(update_carry)
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);
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openfire_execute EXECUTE (
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`ifdef ENABLE_MSR_BIP
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.update_msr_bip(update_msr_bip),
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.value_msr_bip(value_msr_bip),
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`endif
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`ifdef ENABLE_INTERRUPTS
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.interrupt(interrupt),
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.int_ip(int_ip),
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.int_dc(int_dc),
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.set_msr_ie(set_msr_ie),
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`endif
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`ifdef ENABLE_EXCEPTIONS
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.reset_msr_eip(reset_msr_eip),
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.insert_exception(insert_exception),
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`endif
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`ifdef ENABLE_OPCODE_EXCEPTION
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.opcode_exception(opcode_exception),
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`endif
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`ifdef ENABLE_ALIGNMENT_EXCEPTION
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.dmem_alignment_exception(dmem_alignment_exception),
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`endif
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`ifdef ENABLE_MSR_OPCODES
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.rS_update(rs_update),
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`endif
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.clock(clock),
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.reset(reset),
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.stall(stall_exe),
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.immediate(immediate),
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.pc_exe(pc_exe_rf),
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.alu_inputA_sel(alu_inputA_sel),
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.alu_inputB_sel(alu_inputB_sel),
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.alu_inputC_sel(alu_inputC_sel),
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.alu_fns_sel(alu_fns_sel),
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.comparator_fns_sel(comparator_fns_sel),
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.we_load(we_load),
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.we_store(we_store),
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.update_carry(update_carry),
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.regA(regA),
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.regB(regB),
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.regD(regD),
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.alu_result(result),
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.pc_branch(pc_branch),
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.branch_instr(branch_instr),
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.branch_taken(branch_taken),
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.instr_complete(instr_complete),
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.dmem_addr(dmem_addr),
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.dmem_data_out(dmem_data_out),
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.dmem_done(dmem_done),
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.we_regfile(we_regfile),
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.dmem_we(dmem_we),
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.dmem_re(dmem_re)
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);
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openfire_regfile REGFILE (
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.reset(reset),
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.clock(clock),
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.regA_addr(regA_addr),
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.regB_addr(regB_addr),
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.regD_addr(regD_addr),
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.result(result),
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.pc_regfile(pc_exe_rf),
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.dmem_data(dmem_data_in),
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.regfile_input_sel(regfile_input_sel),
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.we_regfile(we_regfile),
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.we_alu_branch(we_alu_branch),
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.regA(regA),
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.regB(regB),
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.regD(regD),
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.enable(~stall_exe)
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);
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openfire_pipeline_ctrl PIPELINE (
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.clock(clock),
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.reset(reset),
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.flush(flush),
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.imem_done(imem_done),
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.imem_re(imem_re),
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.branch_taken(branch_taken),
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.instr_complete(instr_complete),
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.delay_bit(delay_bit),
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.stall_fetch(stall_fetch),
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.stall_decode(stall_decode),
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.stall_exe(stall_exe)
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);
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endmodule
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