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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [openmsp430/] [omsp_wakeup_cell.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_wakeup_cell.v
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//
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// *Module Description:
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//                       Generic Wakeup cell
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module  omsp_wakeup_cell (
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// OUTPUTs
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    wkup_out,                  // Wakup signal (asynchronous)
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// INPUTs
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    scan_clk,                  // Scan clock
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    scan_mode,                 // Scan mode
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    scan_rst,                  // Scan reset
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    wkup_clear,                // Glitch free wakeup event clear
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    wkup_event                 // Glitch free asynchronous wakeup event
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);
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// OUTPUTs
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//=========
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output         wkup_out;       // Wakup signal (asynchronous)
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// INPUTs
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//=========
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input          scan_clk;       // Scan clock
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input          scan_mode;      // Scan mode
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input          scan_rst;       // Scan reset
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input          wkup_clear;     // Glitch free wakeup event clear
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input          wkup_event;     // Glitch free asynchronous wakeup event
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//=============================================================================
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// 1)  AND GATE
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//=============================================================================
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// Scan stuff for the ASIC mode
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`ifdef ASIC
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   wire wkup_rst;
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   omsp_scan_mux scan_mux_rst (
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                               .scan_mode    (scan_mode),
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                               .data_in_scan (scan_rst),
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                               .data_in_func (wkup_clear),
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                               .data_out     (wkup_rst)
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   );
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   wire wkup_clk;
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   omsp_scan_mux scan_mux_clk (
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                               .scan_mode    (scan_mode),
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                               .data_in_scan (scan_clk),
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                               .data_in_func (wkup_event),
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                               .data_out     (wkup_clk)
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   );
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`else
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   wire wkup_rst  =  wkup_clear;
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   wire wkup_clk  =  wkup_event;
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`endif
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// Wakeup capture
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reg    wkup_out;
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always @(posedge wkup_clk or posedge wkup_rst)
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  if (wkup_rst) wkup_out <= 1'b0;
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  else          wkup_out <= 1'b1;
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endmodule // omsp_wakeup_cell
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_undefines.v"
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`endif

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