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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 17

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430.inc
// 
// *Module Description:
//                      openMSP430 Configuration file
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 17 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
//----------------------------------------------------------------------------
 
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// ROM Size:
//                    9 ->  1kB
//                   10 ->  2kB
//                   11 ->  4kB
//                   12 ->  8kB
//                   13 -> 16kB
`define ROM_AWIDTH   10
 
// RAM Size:
//                    6 ->  128 B
//                    7 ->  256 B
//                    8 ->  512 B
//                    9 ->    1 kB
//                   10 ->    2 kB
`define RAM_AWIDTH    6
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`define DBG_EN
 
// Debug interface selection
//             `define DBG_UART -> Enable UART (8N1) debug interface
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
//             `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//             `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//             `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//             `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
`define  DBG_HWBRK_0
`define  DBG_HWBRK_1
`define  DBG_HWBRK_2
`define  DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// ROM and RAM sizes
`define ROM_SIZE  (2 << `ROM_AWIDTH)
`define RAM_SIZE  (2 << `RAM_AWIDTH)
 
// RAM Base Adresses
`define RAM_BASE      16'h0200  // RAM base address
 
// ROM & RAM most significant address bit (for 16 bit words)
`define ROM_MSB   `ROM_AWIDTH-1
`define RAM_MSB   `RAM_AWIDTH-1
 
 
// Instructions type
`define INST_SO  0
`define INST_JMP 1
`define INST_TO  2
 
// Single-operand arithmetic
`define RRC    0
`define SWPB   1
`define RRA    2
`define SXT    3
`define PUSH   4
`define CALL   5
`define RETI   6
`define IRQ    7
 
// Conditional jump
`define JNE    0
`define JEQ    1
`define JNC    2
`define JC     3
`define JN     4
`define JGE    5
`define JL     6
`define JMP    7
 
// Two-operand arithmetic
`define MOV    0
`define ADD    1
`define ADDC   2
`define SUBC   3
`define SUB    4
`define CMP    5
`define DADD   6
`define BIT    7
`define BIC    8
`define BIS    9
`define XOR   10
`define AND   11
 
// Addressing modes
`define DIR      0
`define IDX      1
`define INDIR    2
`define INDIR_I  3
`define SYMB     4
`define IMM      5
`define ABS      6
`define CONST    7
 
// Execution state machine
`define E_IRQ_0    4'h0
`define E_IRQ_1    4'h1
`define E_IRQ_2    4'h2
`define E_IRQ_3    4'h3
`define E_IRQ_4    4'h4
`define E_SRC_AD   4'h5
`define E_SRC_RD   4'h6
`define E_SRC_WR   4'h7
`define E_DST_AD   4'h8
`define E_DST_RD   4'h9
`define E_DST_WR   4'hA
`define E_EXEC     4'hB
`define E_JUMP     4'hC
`define E_IDLE     4'hD
 
// ALU control signals
`define ALU_SRC_INV   0
`define ALU_INC       1
`define ALU_INC_C     2
`define ALU_ADD       3
`define ALU_AND       4
`define ALU_OR        5
`define ALU_XOR       6
`define ALU_DADD      7
`define ALU_STAT_7    8
`define ALU_STAT_F    9
`define ALU_SHIFT    10
`define EXEC_NO_WR   11
 
// Debug interface
`define DBG_UART_WR   18
`define DBG_UART_BW   17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT        0
`define RUN         1
`define ISTEP       2
`define SW_BRK_EN   3
`define FRZ_BRK_EN  4
`define RST_BRK_EN  5
`define CPU_RST     6
 
// Debug interface CPU_STAT register
`define HALT_RUN    0
`define PUC_PND     1
`define SWBRK_PND   3
`define HWBRK0_PND  4
`define HWBRK1_PND  5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE    1:0
`define BRK_EN      2
`define BRK_I_EN    3
`define BRK_RANGE   4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx       5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS        3
`define DIVSx       2:1
 
// Timer A: TACTL Control Register
`define TASSELx     9:8
`define TAIDx       7:6
`define TAMCx       5:4
`define TACLR       2
`define TAIE        1
`define TAIFG       0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx      15:14
`define TACCISx    13:12
`define TASCS      11
`define TASCCI     10
`define TACAP       8
`define TAOUTMODx   7:5
`define TACCIE      4
`define TACCI       3
`define TAOUT       2
`define TACOV       1
`define TACCIFG     0
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug interface ID
`define DBG_ID  24'h4D5350
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
//      In order to properly setup the UART debug interface, you
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
//      the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD    9600
//`define DBG_UART_BAUD   19200
//`define DBG_UART_BAUD   38400
//`define DBG_UART_BAUD   57600
//`define DBG_UART_BAUD  115200
//`define DBG_UART_BAUD  230400
//`define DBG_UART_BAUD  460800
//`define DBG_UART_BAUD  576000
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Check configuration
`ifdef DBG_EN
 `ifdef DBG_UART
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
   `endif
 `else
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET
   `else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
   `endif
 `endif
`endif

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	2	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: openMSP430.inc`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 Configuration file`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34	17	olivier.gi	`// $Rev: 17 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $`
37			`//----------------------------------------------------------------------------`
38	2	olivier.gi
39
40			`//----------------------------------------------------------------------------`
41			`// SYSTEM CONFIGURATION`
42			`//----------------------------------------------------------------------------`
43
44			`// ROM Size:`
45			`// 9 -> 1kB`
46			`// 10 -> 2kB`
47			`// 11 -> 4kB`
48			`// 12 -> 8kB`
49			`// 13 -> 16kB`
50			`define ROM_AWIDTH 10
51
52			`// RAM Size:`
53			`// 6 -> 128 B`
54			`// 7 -> 256 B`
55			`// 8 -> 512 B`
56			`// 9 -> 1 kB`
57			`// 10 -> 2 kB`
58			`define RAM_AWIDTH 6
59
60			`//----------------------------------------------------------------------------`
61			`// REMOTE DEBUGGING INTERFACE CONFIGURATION`
62			`//----------------------------------------------------------------------------`
63
64			`// Include Debug interface`
65			`define DBG_EN
66
67			`// Debug interface selection`
68			// `define DBG_UART -> Enable UART (8N1) debug interface
69			// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
70			`//`
71			`define DBG_UART
72			//`define DBG_JTAG
73
74			`// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)`
75			// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
76			// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
77			// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
78			// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
79			`//`
80			`define DBG_HWBRK_0
81			`define DBG_HWBRK_1
82			`define DBG_HWBRK_2
83			`define DBG_HWBRK_3
84
85
86			`//==========================================================================//`
87			`//==========================================================================//`
88			`//==========================================================================//`
89			`//==========================================================================//`
90			`//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//`
91			`//==========================================================================//`
92			`//==========================================================================//`
93			`//==========================================================================//`
94			`//==========================================================================//`
95
96			`// ROM and RAM sizes`
97			`define ROM_SIZE (2 << `ROM_AWIDTH)
98			`define RAM_SIZE (2 << `RAM_AWIDTH)
99
100			`// RAM Base Adresses`
101			`define RAM_BASE 16'h0200 // RAM base address
102
103			`// ROM & RAM most significant address bit (for 16 bit words)`
104			`define ROM_MSB `ROM_AWIDTH-1
105			`define RAM_MSB `RAM_AWIDTH-1
106
107
108			`// Instructions type`
109			`define INST_SO 0
110			`define INST_JMP 1
111			`define INST_TO 2
112
113			`// Single-operand arithmetic`
114			`define RRC 0
115			`define SWPB 1
116			`define RRA 2
117			`define SXT 3
118			`define PUSH 4
119			`define CALL 5
120			`define RETI 6
121			`define IRQ 7
122
123			`// Conditional jump`
124			`define JNE 0
125			`define JEQ 1
126			`define JNC 2
127			`define JC 3
128			`define JN 4
129			`define JGE 5
130			`define JL 6
131			`define JMP 7
132
133			`// Two-operand arithmetic`
134			`define MOV 0
135			`define ADD 1
136			`define ADDC 2
137			`define SUBC 3
138			`define SUB 4
139			`define CMP 5
140			`define DADD 6
141			`define BIT 7
142			`define BIC 8
143			`define BIS 9
144			`define XOR 10
145			`define AND 11
146
147			`// Addressing modes`
148			`define DIR 0
149			`define IDX 1
150			`define INDIR 2
151			`define INDIR_I 3
152			`define SYMB 4
153			`define IMM 5
154			`define ABS 6
155			`define CONST 7
156
157			`// Execution state machine`
158			`define E_IRQ_0 4'h0
159			`define E_IRQ_1 4'h1
160			`define E_IRQ_2 4'h2
161			`define E_IRQ_3 4'h3
162			`define E_IRQ_4 4'h4
163			`define E_SRC_AD 4'h5
164			`define E_SRC_RD 4'h6
165			`define E_SRC_WR 4'h7
166			`define E_DST_AD 4'h8
167			`define E_DST_RD 4'h9
168			`define E_DST_WR 4'hA
169			`define E_EXEC 4'hB
170			`define E_JUMP 4'hC
171			`define E_IDLE 4'hD
172
173			`// ALU control signals`
174			`define ALU_SRC_INV 0
175			`define ALU_INC 1
176			`define ALU_INC_C 2
177			`define ALU_ADD 3
178			`define ALU_AND 4
179			`define ALU_OR 5
180			`define ALU_XOR 6
181			`define ALU_DADD 7
182			`define ALU_STAT_7 8
183			`define ALU_STAT_F 9
184			`define ALU_SHIFT 10
185			`define EXEC_NO_WR 11
186
187			`// Debug interface`
188			`define DBG_UART_WR 18
189			`define DBG_UART_BW 17
190			`define DBG_UART_ADDR 16:11
191
192			`// Debug interface CPU_CTL register`
193			`define HALT 0
194			`define RUN 1
195			`define ISTEP 2
196			`define SW_BRK_EN 3
197			`define FRZ_BRK_EN 4
198			`define RST_BRK_EN 5
199			`define CPU_RST 6
200
201			`// Debug interface CPU_STAT register`
202			`define HALT_RUN 0
203			`define PUC_PND 1
204			`define SWBRK_PND 3
205			`define HWBRK0_PND 4
206			`define HWBRK1_PND 5
207
208			`// Debug interface BRKx_CTL register`
209			`define BRK_MODE_RD 0
210			`define BRK_MODE_WR 1
211			`define BRK_MODE 1:0
212			`define BRK_EN 2
213			`define BRK_I_EN 3
214			`define BRK_RANGE 4
215
216			`// Basic clock module: BCSCTL1 Control Register`
217			`define DIVAx 5:4
218
219			`// Basic clock module: BCSCTL2 Control Register`
220			`define SELS 3
221			`define DIVSx 2:1
222
223			`// Timer A: TACTL Control Register`
224			`define TASSELx 9:8
225			`define TAIDx 7:6
226			`define TAMCx 5:4
227			`define TACLR 2
228			`define TAIE 1
229			`define TAIFG 0
230
231			`// Timer A: TACCTLx Capture/Compare Control Register`
232			`define TACMx 15:14
233			`define TACCISx 13:12
234			`define TASCS 11
235			`define TASCCI 10
236			`define TACAP 8
237			`define TAOUTMODx 7:5
238			`define TACCIE 4
239			`define TACCI 3
240			`define TAOUT 2
241			`define TACOV 1
242			`define TACCIFG 0
243
244			`//`
245			`// DEBUG INTERFACE EXTRA CONFIGURATION`
246			`//======================================`
247
248			`// Debug interface: Software breakpoint opcode`
249			`define DBG_SWBRK_OP 16'h4343
250
251			`// Debug interface ID`
252			`define DBG_ID 24'h4D5350
253
254			`// Debug UART interface auto data synchronization`
255			`// If the following define is commented out, then`
256			`// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly`
257			`// defined.`
258			`define DBG_UART_AUTO_SYNC
259
260			`// Debug UART interface data rate`
261			`// In order to properly setup the UART debug interface, you`
262			`// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and`
263			`// the chosen BAUD rate from the UART interface.`
264			`//`
265			//`define DBG_UART_BAUD 9600
266			//`define DBG_UART_BAUD 19200
267			//`define DBG_UART_BAUD 38400
268			//`define DBG_UART_BAUD 57600
269			//`define DBG_UART_BAUD 115200
270			//`define DBG_UART_BAUD 230400
271			//`define DBG_UART_BAUD 460800
272			//`define DBG_UART_BAUD 576000
273			//`define DBG_UART_BAUD 921600
274			`define DBG_UART_BAUD 2000000
275			`define DBG_DCO_FREQ 20000000
276			`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
277
278			`// Check configuration`
279			`ifdef DBG_EN
280			`ifdef DBG_UART
281			`ifdef DBG_JTAG
282			`CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED`
283			`endif
284			`else
285			`ifdef DBG_JTAG
286			`CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET`
287			`else
288			`CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED`
289			`endif
290			`endif
291			`endif