OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [gdb/] [sh-tdep.h] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Target-specific definition for a Renesas Super-H.
2
   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3
   2003, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#ifndef SH_TDEP_H
21
#define SH_TDEP_H
22
 
23
/* Contributed by Steve Chamberlain sac@cygnus.com */
24
 
25
/* Registers for all SH variants.  Used also by sh3-rom.c. */
26
enum
27
  {
28
    R0_REGNUM = 0,
29
    STRUCT_RETURN_REGNUM = 2,
30
    ARG0_REGNUM = 4,
31
    ARGLAST_REGNUM = 7,
32
    FP_REGNUM = 14,
33
    PR_REGNUM = 17,
34
    GBR_REGNUM = 18,
35
    VBR_REGNUM = 19,
36
    MACH_REGNUM = 20,
37
    MACL_REGNUM = 21,
38
    SR_REGNUM = 22,
39
    FPUL_REGNUM = 23,
40
    /* Floating point registers */
41
    FPSCR_REGNUM = 24,
42
    FR0_REGNUM = 25,
43
    FLOAT_ARG0_REGNUM = 29,
44
    FLOAT_ARGLAST_REGNUM = 36,
45
    FP_LAST_REGNUM = 40,
46
    /* sh3,sh4 registers */
47
    SSR_REGNUM = 41,
48
    SPC_REGNUM = 42,
49
    /* DSP registers */
50
    DSR_REGNUM = 24,
51
    A0G_REGNUM = 25,
52
    A0_REGNUM = 26,
53
    A1G_REGNUM = 27,
54
    A1_REGNUM = 28,
55
    M0_REGNUM = 29,
56
    M1_REGNUM = 30,
57
    X0_REGNUM = 31,
58
    X1_REGNUM = 32,
59
    Y0_REGNUM = 33,
60
    Y1_REGNUM = 34,
61
    MOD_REGNUM = 40,
62
    RS_REGNUM = 43,
63
    RE_REGNUM = 44,
64
    DSP_R0_BANK_REGNUM = 51,
65
    DSP_R7_BANK_REGNUM = 58,
66
    /* sh2a register */
67
    R0_BANK0_REGNUM = 43,
68
    MACHB_REGNUM = 58,
69
    IVNB_REGNUM = 59,
70
    PRB_REGNUM = 60,
71
    GBRB_REGNUM = 61,
72
    MACLB_REGNUM = 62,
73
    BANK_REGNUM = 63,
74
    IBCR_REGNUM = 64,
75
    IBNR_REGNUM = 65,
76
    TBR_REGNUM = 66,
77
    PSEUDO_BANK_REGNUM = 67,
78
    /* Floating point pseudo registers */
79
    DR0_REGNUM = 68,
80
    DR_LAST_REGNUM = 75,
81
    FV0_REGNUM = 76,
82
    FV_LAST_REGNUM = 79
83
  };
84
 
85
extern gdbarch_init_ftype sh64_gdbarch_init;
86
extern void sh64_show_regs (struct frame_info *);
87
 
88
#endif /* SH_TDEP_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.