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        .macro start
        .text
        .align 2
        .globl _start
_start:
        ldi r0, 0
        .endm
 
 
        .macro exit47
        ldi r4, 1
        ldi r0, 47
        trap 15
        .endm
 
 
        .macro exit0
        ldi r4, 1
        ldi r0, 0
        trap 15
        .endm
 
 
        .macro exit1
        ldi r4, 1
        ldi r0, 1
        trap 15
        .endm
 
 
        .macro exit2
        ldi r4, 1
        ldi r0, 2
        trap 15
        .endm
 
 
        .macro load reg val
        ldi \reg, #\val
        .endm
 
 
        .macro load2w reg hi lo
        ld2w \reg, @(1f,r0)
        .data
        .align 2
1:      .short \hi
        .short \lo
        .text
        .endm
 
 
        .macro check exit reg val
        cmpeqi  \reg, #\val
        brf0t 1f
0:      ldi r4, 1
        ldi r0, \exit
        trap 15
1:
        .endm
 
 
        .macro check2w2 exit reg hi lo
        st2w    \reg, @(1f,r0)
        ld      r2, @(1f, r0)
        cmpeqi  r2, #\hi
        brf0f   0f
        ld      r2, @(1f + 2, r0)
        cmpeqi  r2, #\lo
        brf0f   0f
        bra     2f
0:      ldi r4, 1
        ldi r0, \exit
        trap 15
        .data
        .align 2
1:      .long 0
        .text
2:
        .endm
 
 
        .macro loadacc2 acc guard hi lo
        ldi     r2, #\lo
        mvtaclo r2, \acc
        ldi     r2, #\hi
        mvtachi r2, \acc
        ldi     r2, #\guard
        mvtacg  r2, \acc
        .endm
 
 
        .macro checkacc2 exit acc guard hi lo
        ldi     r2, #\guard
        mvfacg  r3, \acc
        cmpeq   r2, r3
        brf0f   0f
        ldi     r2, #\hi
        mvfachi r3, \acc
        cmpeq   r2, r3
        brf0f   0f
        ldi     r2, #\lo
        mvfaclo r3, \acc
        cmpeq   r2, r3
        brf0f   0f
        bra     4f
0:      ldi r4, 1
        ldi r0, \exit
        trap 15
4:
        .endm
 
 
        .macro loadpsw2 val
        ldi r2, #\val
        mvtc    r2, cr0
        .endm
 
 
        .macro checkpsw2 exit val
        mvfc    r2, cr0
        cmpeqi  r2, #\val
        brf0t   1f
        ldi r4, 1
        ldi r0, \exit
        trap 15
1:
        .endm
 
 
        .macro hello
        ;; 4:write (1, string, strlen (string))
        ldi r4, 4
        ldi r0, 1
        ldi r1, 1f
        ldi r2, 2f-1f-1
        trap 15
        .section        .rodata
1:      .string "Hello World!\n"
2:      .align 2
        .text
        .endm
 
 
;;; Blat our DMAP registers so that they point at on-chip imem
        .macro point_dmap_at_imem
        .text
        ldi r2, MAP_INSN | 0xf
        st r2, @(DMAP_REG,r0)
        ldi r2, MAP_INSN
        st r2, @(IMAP1_REG,r0)
        .endm
 
;;; Patch VEC so that it jumps back to code that checks PSW
;;; and then exits with success.
        .macro check_interrupt vec psw src
;;; Patch the interrupt vector's AE entry with a jmp to success
        .text
        ldi r4, #1f
        ldi r5, \vec
        ;;
        ld2w r2, @(0,r4)
        st2w r2, @(0,r5)
        ld2w r2, @(4,r4)
        st2w r2, @(4,r5)
        ;;
        bra 9f
        nop
;;; Code that gets patched into the interrupt vector
        .data
1:      ldi r1, 2f@word
        jmp r1
;;; Successfull trap jumps back to here
        .text
;;; Verify the PSW
2:      mvfc    r2, cr0
        cmpeqi  r2, #\psw
        brf0t   3f
        nop
        exit1
;;; Verify the original addr
3:      mvfc    r2, bpc
        cmpeqi  r2, #\src@word
        brf0t   4f
        exit2
4:      exit0
;;; continue as normal
9:
        .endm
 
 
        PSW_SM = 0x8000
        PSW_01 = 0x4000
        PSW_EA = 0x2000
        PSW_DB = 0x1000
        PSW_DM = 0x0800
        PSW_IE = 0x0400
        PSW_RP = 0x0200
        PSW_MD = 0x0100
        PSW_FX = 0x0080
        PSW_ST = 0x0040
        PSW_10 = 0x0020
        PSW_11 = 0x0010
        PSW_F0 = 0x0008
        PSW_F1 = 0x0004
        PSW_14 = 0x0002
        PSW_C  = 0x0001
 
 
;;;
 
        DMAP_MASK = 0x3fff
        DMAP_BASE = 0x8000
        DMAP_REG = 0xff04
 
        IMAP0_REG = 0xff00
        IMAP1_REG = 0xff02
 
        MAP_INSN = 0x1000
 
;;;
 
        VEC_RI   = 0x3ff00
        VEC_BAE  = 0x3ff04
        VEC_RIE  = 0x3ff08
        VEC_AE   = 0x3ff0c
        VEC_TRAP = 0x3ff10
        VEC_DBT  = 0x3ff50
        VEC_SDBT = 0x3fff4
        VEC_DBI  = 0x3ff58
        VEC_EI   = 0x3ff5c
 
 

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Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-macros.i] - Blame information for rev 441

Line No.	Rev	Author	Line
1	24	jeremybenn	`.macro start`
2			`.text`
3			`.align 2`
4			`.globl _start`
5			`_start:`
6			`ldi r0, 0`
7			`.endm`
8
9
10			`.macro exit47`
11			`ldi r4, 1`
12			`ldi r0, 47`
13			`trap 15`
14			`.endm`
15
16
17			`.macro exit0`
18			`ldi r4, 1`
19			`ldi r0, 0`
20			`trap 15`
21			`.endm`
22
23
24			`.macro exit1`
25			`ldi r4, 1`
26			`ldi r0, 1`
27			`trap 15`
28			`.endm`
29
30
31			`.macro exit2`
32			`ldi r4, 1`
33			`ldi r0, 2`
34			`trap 15`
35			`.endm`
36
37
38			`.macro load reg val`
39			`ldi \reg, #\val`
40			`.endm`
41
42
43			`.macro load2w reg hi lo`
44			`ld2w \reg, @(1f,r0)`
45			`.data`
46			`.align 2`
47			`1: .short \hi`
48			`.short \lo`
49			`.text`
50			`.endm`
51
52
53			`.macro check exit reg val`
54			`cmpeqi \reg, #\val`
55			`brf0t 1f`
56			`0: ldi r4, 1`
57			`ldi r0, \exit`
58			`trap 15`
59			`1:`
60			`.endm`
61
62
63			`.macro check2w2 exit reg hi lo`
64			`st2w \reg, @(1f,r0)`
65			`ld r2, @(1f, r0)`
66			`cmpeqi r2, #\hi`
67			`brf0f 0f`
68			`ld r2, @(1f + 2, r0)`
69			`cmpeqi r2, #\lo`
70			`brf0f 0f`
71			`bra 2f`
72			`0: ldi r4, 1`
73			`ldi r0, \exit`
74			`trap 15`
75			`.data`
76			`.align 2`
77			`1: .long 0`
78			`.text`
79			`2:`
80			`.endm`
81
82
83			`.macro loadacc2 acc guard hi lo`
84			`ldi r2, #\lo`
85			`mvtaclo r2, \acc`
86			`ldi r2, #\hi`
87			`mvtachi r2, \acc`
88			`ldi r2, #\guard`
89			`mvtacg r2, \acc`
90			`.endm`
91
92
93			`.macro checkacc2 exit acc guard hi lo`
94			`ldi r2, #\guard`
95			`mvfacg r3, \acc`
96			`cmpeq r2, r3`
97			`brf0f 0f`
98			`ldi r2, #\hi`
99			`mvfachi r3, \acc`
100			`cmpeq r2, r3`
101			`brf0f 0f`
102			`ldi r2, #\lo`
103			`mvfaclo r3, \acc`
104			`cmpeq r2, r3`
105			`brf0f 0f`
106			`bra 4f`
107			`0: ldi r4, 1`
108			`ldi r0, \exit`
109			`trap 15`
110			`4:`
111			`.endm`
112
113
114			`.macro loadpsw2 val`
115			`ldi r2, #\val`
116			`mvtc r2, cr0`
117			`.endm`
118
119
120			`.macro checkpsw2 exit val`
121			`mvfc r2, cr0`
122			`cmpeqi r2, #\val`
123			`brf0t 1f`
124			`ldi r4, 1`
125			`ldi r0, \exit`
126			`trap 15`
127			`1:`
128			`.endm`
129
130
131			`.macro hello`
132			`;; 4:write (1, string, strlen (string))`
133			`ldi r4, 4`
134			`ldi r0, 1`
135			`ldi r1, 1f`
136			`ldi r2, 2f-1f-1`
137			`trap 15`
138			`.section .rodata`
139			`1: .string "Hello World!\n"`
140			`2: .align 2`
141			`.text`
142			`.endm`
143
144
145			`;;; Blat our DMAP registers so that they point at on-chip imem`
146			`.macro point_dmap_at_imem`
147			`.text`
148			`ldi r2, MAP_INSN \| 0xf`
149			`st r2, @(DMAP_REG,r0)`
150			`ldi r2, MAP_INSN`
151			`st r2, @(IMAP1_REG,r0)`
152			`.endm`
153
154			`;;; Patch VEC so that it jumps back to code that checks PSW`
155			`;;; and then exits with success.`
156			`.macro check_interrupt vec psw src`
157			`;;; Patch the interrupt vector's AE entry with a jmp to success`
158			`.text`
159			`ldi r4, #1f`
160			`ldi r5, \vec`
161			`;;`
162			`ld2w r2, @(0,r4)`
163			`st2w r2, @(0,r5)`
164			`ld2w r2, @(4,r4)`
165			`st2w r2, @(4,r5)`
166			`;;`
167			`bra 9f`
168			`nop`
169			`;;; Code that gets patched into the interrupt vector`
170			`.data`
171			`1: ldi r1, 2f@word`
172			`jmp r1`
173			`;;; Successfull trap jumps back to here`
174			`.text`
175			`;;; Verify the PSW`
176			`2: mvfc r2, cr0`
177			`cmpeqi r2, #\psw`
178			`brf0t 3f`
179			`nop`
180			`exit1`
181			`;;; Verify the original addr`
182			`3: mvfc r2, bpc`
183			`cmpeqi r2, #\src@word`
184			`brf0t 4f`
185			`exit2`
186			`4: exit0`
187			`;;; continue as normal`
188			`9:`
189			`.endm`
190
191
192			`PSW_SM = 0x8000`
193			`PSW_01 = 0x4000`
194			`PSW_EA = 0x2000`
195			`PSW_DB = 0x1000`
196			`PSW_DM = 0x0800`
197			`PSW_IE = 0x0400`
198			`PSW_RP = 0x0200`
199			`PSW_MD = 0x0100`
200			`PSW_FX = 0x0080`
201			`PSW_ST = 0x0040`
202			`PSW_10 = 0x0020`
203			`PSW_11 = 0x0010`
204			`PSW_F0 = 0x0008`
205			`PSW_F1 = 0x0004`
206			`PSW_14 = 0x0002`
207			`PSW_C = 0x0001`
208
209
210			`;;;`
211
212			`DMAP_MASK = 0x3fff`
213			`DMAP_BASE = 0x8000`
214			`DMAP_REG = 0xff04`
215
216			`IMAP0_REG = 0xff00`
217			`IMAP1_REG = 0xff02`
218
219			`MAP_INSN = 0x1000`
220
221			`;;;`
222
223			`VEC_RI = 0x3ff00`
224			`VEC_BAE = 0x3ff04`
225			`VEC_RIE = 0x3ff08`
226			`VEC_AE = 0x3ff0c`
227			`VEC_TRAP = 0x3ff10`
228			`VEC_DBT = 0x3ff50`
229			`VEC_SDBT = 0x3fff4`
230			`VEC_DBI = 0x3ff58`
231			`VEC_EI = 0x3ff5c`
232
233