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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [cris/] [cris-desc.c] - Blame information for rev 380

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Line No. Rev Author Line
1 330 jeremybenn 
/* CPU data for cris.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2010 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <stdio.h>
27 
#include <stdarg.h>
28 
#include "ansidecl.h"
29 
#include "bfd.h"
30 
#include "symcat.h"
31 
#include "cris-desc.h"
32 
#include "cris-opc.h"
33 
#include "opintl.h"
34 
#include "libiberty.h"
35 
#include "xregex.h"
36 
 
37 
/* Attributes.  */
38 
 
39 
static const CGEN_ATTR_ENTRY bool_attr[] =
40 
{
41 
  { "#f", 0 },
42 
  { "#t", 1 },
43 
  { 0, 0 }
44 
};
45 
 
46 
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 
{
48 
  { "base", MACH_BASE },
49 
  { "crisv0", MACH_CRISV0 },
50 
  { "crisv3", MACH_CRISV3 },
51 
  { "crisv8", MACH_CRISV8 },
52 
  { "crisv10", MACH_CRISV10 },
53 
  { "crisv32", MACH_CRISV32 },
54 
  { "max", MACH_MAX },
55 
  { 0, 0 }
56 
};
57 
 
58 
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
59 
{
60 
  { "cris", ISA_CRIS },
61 
  { "max", ISA_MAX },
62 
  { 0, 0 }
63 
};
64 
 
65 
const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] =
66 
{
67 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
68 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
69 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
70 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
71 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
72 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
73 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
74 
  { 0, 0, 0 }
75 
};
76 
 
77 
const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] =
78 
{
79 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
80 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
81 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
82 
  { "PC", &bool_attr[0], &bool_attr[0] },
83 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 
  { 0, 0, 0 }
85 
};
86 
 
87 
const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] =
88 
{
89 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
90 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
91 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
92 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
93 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
94 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
95 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
96 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
97 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
98 
  { 0, 0, 0 }
99 
};
100 
 
101 
const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] =
102 
{
103 
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
104 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
105 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
106 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
107 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
108 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
109 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
110 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
111 
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
112 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
113 
  { "PBB", &bool_attr[0], &bool_attr[0] },
114 
  { 0, 0, 0 }
115 
};
116 
 
117 
/* Instruction set variants.  */
118 
 
119 
static const CGEN_ISA cris_cgen_isa_table[] = {
120 
  { "cris", 16, 16, 16, 48 },
121 
  { 0, 0, 0, 0, 0 }
122 
};
123 
 
124 
/* Machine variants.  */
125 
 
126 
static const CGEN_MACH cris_cgen_mach_table[] = {
127 
  { "crisv0", "cris", MACH_CRISV0, 0 },
128 
  { "crisv3", "cris", MACH_CRISV3, 0 },
129 
  { "crisv8", "cris", MACH_CRISV8, 0 },
130 
  { "crisv10", "cris", MACH_CRISV10, 0 },
131 
  { "crisv32", "crisv32", MACH_CRISV32, 0 },
132 
  { 0, 0, 0, 0 }
133 
};
134 
 
135 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] =
136 
{
137 
  { "PC", 15, {0, {{{0, 0}}}}, 0, 0 },
138 
  { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
139 
  { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
140 
  { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
141 
  { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
142 
  { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
143 
  { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
144 
  { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
145 
  { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
146 
  { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
147 
  { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
148 
  { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
149 
  { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
150 
  { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
151 
  { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
152 
  { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
153 
  { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
154 
};
155 
 
156 
CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg =
157 
{
158 
  & cris_cgen_opval_gr_names_pcreg_entries[0],
159 
  17,
160 
  0, 0, 0, 0, ""
161 
};
162 
 
163 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] =
164 
{
165 
  { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 },
166 
  { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
167 
  { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
168 
  { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
169 
  { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
170 
  { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
171 
  { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
172 
  { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
173 
  { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
174 
  { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
175 
  { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
176 
  { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
177 
  { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
178 
  { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
179 
  { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
180 
  { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
181 
  { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
182 
};
183 
 
184 
CGEN_KEYWORD cris_cgen_opval_gr_names_acr =
185 
{
186 
  & cris_cgen_opval_gr_names_acr_entries[0],
187 
  17,
188 
  0, 0, 0, 0, ""
189 
};
190 
 
191 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] =
192 
{
193 
  { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 },
194 
  { "SP", 14, {0, {{{0, 0}}}}, 0, 0 },
195 
  { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
196 
  { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
197 
  { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
198 
  { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
199 
  { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
200 
  { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
201 
  { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
202 
  { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
203 
  { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
204 
  { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
205 
  { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
206 
  { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
207 
  { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
208 
  { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
209 
  { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }
210 
};
211 
 
212 
CGEN_KEYWORD cris_cgen_opval_gr_names_v32 =
213 
{
214 
  & cris_cgen_opval_gr_names_v32_entries[0],
215 
  17,
216 
  0, 0, 0, 0, ""
217 
};
218 
 
219 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] =
220 
{
221 
  { "CCR", 5, {0, {{{0, 0}}}}, 0, 0 },
222 
  { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
223 
  { "IBR", 9, {0, {{{0, 0}}}}, 0, 0 },
224 
  { "IRP", 10, {0, {{{0, 0}}}}, 0, 0 },
225 
  { "BAR", 12, {0, {{{0, 0}}}}, 0, 0 },
226 
  { "DCCR", 13, {0, {{{0, 0}}}}, 0, 0 },
227 
  { "BRP", 14, {0, {{{0, 0}}}}, 0, 0 },
228 
  { "USP", 15, {0, {{{0, 0}}}}, 0, 0 },
229 
  { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
230 
  { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
231 
  { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
232 
  { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
233 
  { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
234 
  { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
235 
  { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
236 
  { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
237 
  { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
238 
  { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
239 
  { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
240 
  { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
241 
  { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
242 
  { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
243 
  { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
244 
  { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
245 
  { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
246 
};
247 
 
248 
CGEN_KEYWORD cris_cgen_opval_p_names_v10 =
249 
{
250 
  & cris_cgen_opval_p_names_v10_entries[0],
251 
  25,
252 
  0, 0, 0, 0, ""
253 
};
254 
 
255 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] =
256 
{
257 
  { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 },
258 
  { "PID", 2, {0, {{{0, 0}}}}, 0, 0 },
259 
  { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 },
260 
  { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 },
261 
  { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 },
262 
  { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 },
263 
  { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
264 
  { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 },
265 
  { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 },
266 
  { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 },
267 
  { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 },
268 
  { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 },
269 
  { "USP", 14, {0, {{{0, 0}}}}, 0, 0 },
270 
  { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 },
271 
  { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
272 
  { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
273 
  { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
274 
  { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
275 
  { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
276 
  { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
277 
  { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
278 
  { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
279 
  { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
280 
  { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
281 
  { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
282 
  { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
283 
  { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
284 
  { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
285 
  { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
286 
  { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
287 
  { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
288 
};
289 
 
290 
CGEN_KEYWORD cris_cgen_opval_p_names_v32 =
291 
{
292 
  & cris_cgen_opval_p_names_v32_entries[0],
293 
  31,
294 
  0, 0, 0, 0, ""
295 
};
296 
 
297 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] =
298 
{
299 
  { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 },
300 
  { "PID", 2, {0, {{{0, 0}}}}, 0, 0 },
301 
  { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 },
302 
  { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 },
303 
  { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 },
304 
  { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 },
305 
  { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 },
306 
  { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 },
307 
  { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 },
308 
  { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 },
309 
  { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 },
310 
  { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 },
311 
  { "USP", 14, {0, {{{0, 0}}}}, 0, 0 },
312 
  { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 },
313 
  { "VR", 1, {0, {{{0, 0}}}}, 0, 0 },
314 
  { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 },
315 
  { "P0", 0, {0, {{{0, 0}}}}, 0, 0 },
316 
  { "P1", 1, {0, {{{0, 0}}}}, 0, 0 },
317 
  { "P2", 2, {0, {{{0, 0}}}}, 0, 0 },
318 
  { "P3", 3, {0, {{{0, 0}}}}, 0, 0 },
319 
  { "P4", 4, {0, {{{0, 0}}}}, 0, 0 },
320 
  { "P5", 5, {0, {{{0, 0}}}}, 0, 0 },
321 
  { "P6", 6, {0, {{{0, 0}}}}, 0, 0 },
322 
  { "P7", 7, {0, {{{0, 0}}}}, 0, 0 },
323 
  { "P8", 8, {0, {{{0, 0}}}}, 0, 0 },
324 
  { "P9", 9, {0, {{{0, 0}}}}, 0, 0 },
325 
  { "P10", 10, {0, {{{0, 0}}}}, 0, 0 },
326 
  { "P11", 11, {0, {{{0, 0}}}}, 0, 0 },
327 
  { "P12", 12, {0, {{{0, 0}}}}, 0, 0 },
328 
  { "P13", 13, {0, {{{0, 0}}}}, 0, 0 },
329 
  { "P14", 14, {0, {{{0, 0}}}}, 0, 0 }
330 
};
331 
 
332 
CGEN_KEYWORD cris_cgen_opval_p_names_v32_x =
333 
{
334 
  & cris_cgen_opval_p_names_v32_x_entries[0],
335 
  31,
336 
  0, 0, 0, 0, ""
337 
};
338 
 
339 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] =
340 
{
341 
  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
342 
  { "+", 1, {0, {{{0, 0}}}}, 0, 0 }
343 
};
344 
 
345 
CGEN_KEYWORD cris_cgen_opval_h_inc =
346 
{
347 
  & cris_cgen_opval_h_inc_entries[0],
348 
  2,
349 
  0, 0, 0, 0, ""
350 
};
351 
 
352 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] =
353 
{
354 
  { "cc", 0, {0, {{{0, 0}}}}, 0, 0 },
355 
  { "cs", 1, {0, {{{0, 0}}}}, 0, 0 },
356 
  { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
357 
  { "eq", 3, {0, {{{0, 0}}}}, 0, 0 },
358 
  { "vc", 4, {0, {{{0, 0}}}}, 0, 0 },
359 
  { "vs", 5, {0, {{{0, 0}}}}, 0, 0 },
360 
  { "pl", 6, {0, {{{0, 0}}}}, 0, 0 },
361 
  { "mi", 7, {0, {{{0, 0}}}}, 0, 0 },
362 
  { "ls", 8, {0, {{{0, 0}}}}, 0, 0 },
363 
  { "hi", 9, {0, {{{0, 0}}}}, 0, 0 },
364 
  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
365 
  { "lt", 11, {0, {{{0, 0}}}}, 0, 0 },
366 
  { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
367 
  { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
368 
  { "a", 14, {0, {{{0, 0}}}}, 0, 0 },
369 
  { "wf", 15, {0, {{{0, 0}}}}, 0, 0 }
370 
};
371 
 
372 
CGEN_KEYWORD cris_cgen_opval_h_ccode =
373 
{
374 
  & cris_cgen_opval_h_ccode_entries[0],
375 
  16,
376 
  0, 0, 0, 0, ""
377 
};
378 
 
379 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] =
380 
{
381 
  { " ", 0, {0, {{{0, 0}}}}, 0, 0 },
382 
  { "r", 1, {0, {{{0, 0}}}}, 0, 0 },
383 
  { "b", 2, {0, {{{0, 0}}}}, 0, 0 },
384 
  { "br", 3, {0, {{{0, 0}}}}, 0, 0 },
385 
  { "w", 4, {0, {{{0, 0}}}}, 0, 0 },
386 
  { "wr", 5, {0, {{{0, 0}}}}, 0, 0 },
387 
  { "wb", 6, {0, {{{0, 0}}}}, 0, 0 },
388 
  { "wbr", 7, {0, {{{0, 0}}}}, 0, 0 },
389 
  { "n", 8, {0, {{{0, 0}}}}, 0, 0 },
390 
  { "nr", 9, {0, {{{0, 0}}}}, 0, 0 },
391 
  { "nb", 10, {0, {{{0, 0}}}}, 0, 0 },
392 
  { "nbr", 11, {0, {{{0, 0}}}}, 0, 0 },
393 
  { "nw", 12, {0, {{{0, 0}}}}, 0, 0 },
394 
  { "nwr", 13, {0, {{{0, 0}}}}, 0, 0 },
395 
  { "nwb", 14, {0, {{{0, 0}}}}, 0, 0 },
396 
  { "nwbr", 15, {0, {{{0, 0}}}}, 0, 0 }
397 
};
398 
 
399 
CGEN_KEYWORD cris_cgen_opval_h_swap =
400 
{
401 
  & cris_cgen_opval_h_swap_entries[0],
402 
  16,
403 
  0, 0, 0, 0, ""
404 
};
405 
 
406 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] =
407 
{
408 
  { "_", 0, {0, {{{0, 0}}}}, 0, 0 },
409 
  { "c", 1, {0, {{{0, 0}}}}, 0, 0 },
410 
  { "v", 2, {0, {{{0, 0}}}}, 0, 0 },
411 
  { "cv", 3, {0, {{{0, 0}}}}, 0, 0 },
412 
  { "z", 4, {0, {{{0, 0}}}}, 0, 0 },
413 
  { "cz", 5, {0, {{{0, 0}}}}, 0, 0 },
414 
  { "vz", 6, {0, {{{0, 0}}}}, 0, 0 },
415 
  { "cvz", 7, {0, {{{0, 0}}}}, 0, 0 },
416 
  { "n", 8, {0, {{{0, 0}}}}, 0, 0 },
417 
  { "cn", 9, {0, {{{0, 0}}}}, 0, 0 },
418 
  { "vn", 10, {0, {{{0, 0}}}}, 0, 0 },
419 
  { "cvn", 11, {0, {{{0, 0}}}}, 0, 0 },
420 
  { "zn", 12, {0, {{{0, 0}}}}, 0, 0 },
421 
  { "czn", 13, {0, {{{0, 0}}}}, 0, 0 },
422 
  { "vzn", 14, {0, {{{0, 0}}}}, 0, 0 },
423 
  { "cvzn", 15, {0, {{{0, 0}}}}, 0, 0 },
424 
  { "x", 16, {0, {{{0, 0}}}}, 0, 0 },
425 
  { "cx", 17, {0, {{{0, 0}}}}, 0, 0 },
426 
  { "vx", 18, {0, {{{0, 0}}}}, 0, 0 },
427 
  { "cvx", 19, {0, {{{0, 0}}}}, 0, 0 },
428 
  { "zx", 20, {0, {{{0, 0}}}}, 0, 0 },
429 
  { "czx", 21, {0, {{{0, 0}}}}, 0, 0 },
430 
  { "vzx", 22, {0, {{{0, 0}}}}, 0, 0 },
431 
  { "cvzx", 23, {0, {{{0, 0}}}}, 0, 0 },
432 
  { "nx", 24, {0, {{{0, 0}}}}, 0, 0 },
433 
  { "cnx", 25, {0, {{{0, 0}}}}, 0, 0 },
434 
  { "vnx", 26, {0, {{{0, 0}}}}, 0, 0 },
435 
  { "cvnx", 27, {0, {{{0, 0}}}}, 0, 0 },
436 
  { "znx", 28, {0, {{{0, 0}}}}, 0, 0 },
437 
  { "cznx", 29, {0, {{{0, 0}}}}, 0, 0 },
438 
  { "vznx", 30, {0, {{{0, 0}}}}, 0, 0 },
439 
  { "cvznx", 31, {0, {{{0, 0}}}}, 0, 0 },
440 
  { "i", 32, {0, {{{0, 0}}}}, 0, 0 },
441 
  { "ci", 33, {0, {{{0, 0}}}}, 0, 0 },
442 
  { "vi", 34, {0, {{{0, 0}}}}, 0, 0 },
443 
  { "cvi", 35, {0, {{{0, 0}}}}, 0, 0 },
444 
  { "zi", 36, {0, {{{0, 0}}}}, 0, 0 },
445 
  { "czi", 37, {0, {{{0, 0}}}}, 0, 0 },
446 
  { "vzi", 38, {0, {{{0, 0}}}}, 0, 0 },
447 
  { "cvzi", 39, {0, {{{0, 0}}}}, 0, 0 },
448 
  { "ni", 40, {0, {{{0, 0}}}}, 0, 0 },
449 
  { "cni", 41, {0, {{{0, 0}}}}, 0, 0 },
450 
  { "vni", 42, {0, {{{0, 0}}}}, 0, 0 },
451 
  { "cvni", 43, {0, {{{0, 0}}}}, 0, 0 },
452 
  { "zni", 44, {0, {{{0, 0}}}}, 0, 0 },
453 
  { "czni", 45, {0, {{{0, 0}}}}, 0, 0 },
454 
  { "vzni", 46, {0, {{{0, 0}}}}, 0, 0 },
455 
  { "cvzni", 47, {0, {{{0, 0}}}}, 0, 0 },
456 
  { "xi", 48, {0, {{{0, 0}}}}, 0, 0 },
457 
  { "cxi", 49, {0, {{{0, 0}}}}, 0, 0 },
458 
  { "vxi", 50, {0, {{{0, 0}}}}, 0, 0 },
459 
  { "cvxi", 51, {0, {{{0, 0}}}}, 0, 0 },
460 
  { "zxi", 52, {0, {{{0, 0}}}}, 0, 0 },
461 
  { "czxi", 53, {0, {{{0, 0}}}}, 0, 0 },
462 
  { "vzxi", 54, {0, {{{0, 0}}}}, 0, 0 },
463 
  { "cvzxi", 55, {0, {{{0, 0}}}}, 0, 0 },
464 
  { "nxi", 56, {0, {{{0, 0}}}}, 0, 0 },
465 
  { "cnxi", 57, {0, {{{0, 0}}}}, 0, 0 },
466 
  { "vnxi", 58, {0, {{{0, 0}}}}, 0, 0 },
467 
  { "cvnxi", 59, {0, {{{0, 0}}}}, 0, 0 },
468 
  { "znxi", 60, {0, {{{0, 0}}}}, 0, 0 },
469 
  { "cznxi", 61, {0, {{{0, 0}}}}, 0, 0 },
470 
  { "vznxi", 62, {0, {{{0, 0}}}}, 0, 0 },
471 
  { "cvznxi", 63, {0, {{{0, 0}}}}, 0, 0 },
472 
  { "u", 64, {0, {{{0, 0}}}}, 0, 0 },
473 
  { "cu", 65, {0, {{{0, 0}}}}, 0, 0 },
474 
  { "vu", 66, {0, {{{0, 0}}}}, 0, 0 },
475 
  { "cvu", 67, {0, {{{0, 0}}}}, 0, 0 },
476 
  { "zu", 68, {0, {{{0, 0}}}}, 0, 0 },
477 
  { "czu", 69, {0, {{{0, 0}}}}, 0, 0 },
478 
  { "vzu", 70, {0, {{{0, 0}}}}, 0, 0 },
479 
  { "cvzu", 71, {0, {{{0, 0}}}}, 0, 0 },
480 
  { "nu", 72, {0, {{{0, 0}}}}, 0, 0 },
481 
  { "cnu", 73, {0, {{{0, 0}}}}, 0, 0 },
482 
  { "vnu", 74, {0, {{{0, 0}}}}, 0, 0 },
483 
  { "cvnu", 75, {0, {{{0, 0}}}}, 0, 0 },
484 
  { "znu", 76, {0, {{{0, 0}}}}, 0, 0 },
485 
  { "cznu", 77, {0, {{{0, 0}}}}, 0, 0 },
486 
  { "vznu", 78, {0, {{{0, 0}}}}, 0, 0 },
487 
  { "cvznu", 79, {0, {{{0, 0}}}}, 0, 0 },
488 
  { "xu", 80, {0, {{{0, 0}}}}, 0, 0 },
489 
  { "cxu", 81, {0, {{{0, 0}}}}, 0, 0 },
490 
  { "vxu", 82, {0, {{{0, 0}}}}, 0, 0 },
491 
  { "cvxu", 83, {0, {{{0, 0}}}}, 0, 0 },
492 
  { "zxu", 84, {0, {{{0, 0}}}}, 0, 0 },
493 
  { "czxu", 85, {0, {{{0, 0}}}}, 0, 0 },
494 
  { "vzxu", 86, {0, {{{0, 0}}}}, 0, 0 },
495 
  { "cvzxu", 87, {0, {{{0, 0}}}}, 0, 0 },
496 
  { "nxu", 88, {0, {{{0, 0}}}}, 0, 0 },
497 
  { "cnxu", 89, {0, {{{0, 0}}}}, 0, 0 },
498 
  { "vnxu", 90, {0, {{{0, 0}}}}, 0, 0 },
499 
  { "cvnxu", 91, {0, {{{0, 0}}}}, 0, 0 },
500 
  { "znxu", 92, {0, {{{0, 0}}}}, 0, 0 },
501 
  { "cznxu", 93, {0, {{{0, 0}}}}, 0, 0 },
502 
  { "vznxu", 94, {0, {{{0, 0}}}}, 0, 0 },
503 
  { "cvznxu", 95, {0, {{{0, 0}}}}, 0, 0 },
504 
  { "iu", 96, {0, {{{0, 0}}}}, 0, 0 },
505 
  { "ciu", 97, {0, {{{0, 0}}}}, 0, 0 },
506 
  { "viu", 98, {0, {{{0, 0}}}}, 0, 0 },
507 
  { "cviu", 99, {0, {{{0, 0}}}}, 0, 0 },
508 
  { "ziu", 100, {0, {{{0, 0}}}}, 0, 0 },
509 
  { "cziu", 101, {0, {{{0, 0}}}}, 0, 0 },
510 
  { "vziu", 102, {0, {{{0, 0}}}}, 0, 0 },
511 
  { "cvziu", 103, {0, {{{0, 0}}}}, 0, 0 },
512 
  { "niu", 104, {0, {{{0, 0}}}}, 0, 0 },
513 
  { "cniu", 105, {0, {{{0, 0}}}}, 0, 0 },
514 
  { "vniu", 106, {0, {{{0, 0}}}}, 0, 0 },
515 
  { "cvniu", 107, {0, {{{0, 0}}}}, 0, 0 },
516 
  { "zniu", 108, {0, {{{0, 0}}}}, 0, 0 },
517 
  { "czniu", 109, {0, {{{0, 0}}}}, 0, 0 },
518 
  { "vzniu", 110, {0, {{{0, 0}}}}, 0, 0 },
519 
  { "cvzniu", 111, {0, {{{0, 0}}}}, 0, 0 },
520 
  { "xiu", 112, {0, {{{0, 0}}}}, 0, 0 },
521 
  { "cxiu", 113, {0, {{{0, 0}}}}, 0, 0 },
522 
  { "vxiu", 114, {0, {{{0, 0}}}}, 0, 0 },
523 
  { "cvxiu", 115, {0, {{{0, 0}}}}, 0, 0 },
524 
  { "zxiu", 116, {0, {{{0, 0}}}}, 0, 0 },
525 
  { "czxiu", 117, {0, {{{0, 0}}}}, 0, 0 },
526 
  { "vzxiu", 118, {0, {{{0, 0}}}}, 0, 0 },
527 
  { "cvzxiu", 119, {0, {{{0, 0}}}}, 0, 0 },
528 
  { "nxiu", 120, {0, {{{0, 0}}}}, 0, 0 },
529 
  { "cnxiu", 121, {0, {{{0, 0}}}}, 0, 0 },
530 
  { "vnxiu", 122, {0, {{{0, 0}}}}, 0, 0 },
531 
  { "cvnxiu", 123, {0, {{{0, 0}}}}, 0, 0 },
532 
  { "znxiu", 124, {0, {{{0, 0}}}}, 0, 0 },
533 
  { "cznxiu", 125, {0, {{{0, 0}}}}, 0, 0 },
534 
  { "vznxiu", 126, {0, {{{0, 0}}}}, 0, 0 },
535 
  { "cvznxiu", 127, {0, {{{0, 0}}}}, 0, 0 },
536 
  { "p", 128, {0, {{{0, 0}}}}, 0, 0 },
537 
  { "cp", 129, {0, {{{0, 0}}}}, 0, 0 },
538 
  { "vp", 130, {0, {{{0, 0}}}}, 0, 0 },
539 
  { "cvp", 131, {0, {{{0, 0}}}}, 0, 0 },
540 
  { "zp", 132, {0, {{{0, 0}}}}, 0, 0 },
541 
  { "czp", 133, {0, {{{0, 0}}}}, 0, 0 },
542 
  { "vzp", 134, {0, {{{0, 0}}}}, 0, 0 },
543 
  { "cvzp", 135, {0, {{{0, 0}}}}, 0, 0 },
544 
  { "np", 136, {0, {{{0, 0}}}}, 0, 0 },
545 
  { "cnp", 137, {0, {{{0, 0}}}}, 0, 0 },
546 
  { "vnp", 138, {0, {{{0, 0}}}}, 0, 0 },
547 
  { "cvnp", 139, {0, {{{0, 0}}}}, 0, 0 },
548 
  { "znp", 140, {0, {{{0, 0}}}}, 0, 0 },
549 
  { "cznp", 141, {0, {{{0, 0}}}}, 0, 0 },
550 
  { "vznp", 142, {0, {{{0, 0}}}}, 0, 0 },
551 
  { "cvznp", 143, {0, {{{0, 0}}}}, 0, 0 },
552 
  { "xp", 144, {0, {{{0, 0}}}}, 0, 0 },
553 
  { "cxp", 145, {0, {{{0, 0}}}}, 0, 0 },
554 
  { "vxp", 146, {0, {{{0, 0}}}}, 0, 0 },
555 
  { "cvxp", 147, {0, {{{0, 0}}}}, 0, 0 },
556 
  { "zxp", 148, {0, {{{0, 0}}}}, 0, 0 },
557 
  { "czxp", 149, {0, {{{0, 0}}}}, 0, 0 },
558 
  { "vzxp", 150, {0, {{{0, 0}}}}, 0, 0 },
559 
  { "cvzxp", 151, {0, {{{0, 0}}}}, 0, 0 },
560 
  { "nxp", 152, {0, {{{0, 0}}}}, 0, 0 },
561 
  { "cnxp", 153, {0, {{{0, 0}}}}, 0, 0 },
562 
  { "vnxp", 154, {0, {{{0, 0}}}}, 0, 0 },
563 
  { "cvnxp", 155, {0, {{{0, 0}}}}, 0, 0 },
564 
  { "znxp", 156, {0, {{{0, 0}}}}, 0, 0 },
565 
  { "cznxp", 157, {0, {{{0, 0}}}}, 0, 0 },
566 
  { "vznxp", 158, {0, {{{0, 0}}}}, 0, 0 },
567 
  { "cvznxp", 159, {0, {{{0, 0}}}}, 0, 0 },
568 
  { "ip", 160, {0, {{{0, 0}}}}, 0, 0 },
569 
  { "cip", 161, {0, {{{0, 0}}}}, 0, 0 },
570 
  { "vip", 162, {0, {{{0, 0}}}}, 0, 0 },
571 
  { "cvip", 163, {0, {{{0, 0}}}}, 0, 0 },
572 
  { "zip", 164, {0, {{{0, 0}}}}, 0, 0 },
573 
  { "czip", 165, {0, {{{0, 0}}}}, 0, 0 },
574 
  { "vzip", 166, {0, {{{0, 0}}}}, 0, 0 },
575 
  { "cvzip", 167, {0, {{{0, 0}}}}, 0, 0 },
576 
  { "nip", 168, {0, {{{0, 0}}}}, 0, 0 },
577 
  { "cnip", 169, {0, {{{0, 0}}}}, 0, 0 },
578 
  { "vnip", 170, {0, {{{0, 0}}}}, 0, 0 },
579 
  { "cvnip", 171, {0, {{{0, 0}}}}, 0, 0 },
580 
  { "znip", 172, {0, {{{0, 0}}}}, 0, 0 },
581 
  { "cznip", 173, {0, {{{0, 0}}}}, 0, 0 },
582 
  { "vznip", 174, {0, {{{0, 0}}}}, 0, 0 },
583 
  { "cvznip", 175, {0, {{{0, 0}}}}, 0, 0 },
584 
  { "xip", 176, {0, {{{0, 0}}}}, 0, 0 },
585 
  { "cxip", 177, {0, {{{0, 0}}}}, 0, 0 },
586 
  { "vxip", 178, {0, {{{0, 0}}}}, 0, 0 },
587 
  { "cvxip", 179, {0, {{{0, 0}}}}, 0, 0 },
588 
  { "zxip", 180, {0, {{{0, 0}}}}, 0, 0 },
589 
  { "czxip", 181, {0, {{{0, 0}}}}, 0, 0 },
590 
  { "vzxip", 182, {0, {{{0, 0}}}}, 0, 0 },
591 
  { "cvzxip", 183, {0, {{{0, 0}}}}, 0, 0 },
592 
  { "nxip", 184, {0, {{{0, 0}}}}, 0, 0 },
593 
  { "cnxip", 185, {0, {{{0, 0}}}}, 0, 0 },
594 
  { "vnxip", 186, {0, {{{0, 0}}}}, 0, 0 },
595 
  { "cvnxip", 187, {0, {{{0, 0}}}}, 0, 0 },
596 
  { "znxip", 188, {0, {{{0, 0}}}}, 0, 0 },
597 
  { "cznxip", 189, {0, {{{0, 0}}}}, 0, 0 },
598 
  { "vznxip", 190, {0, {{{0, 0}}}}, 0, 0 },
599 
  { "cvznxip", 191, {0, {{{0, 0}}}}, 0, 0 },
600 
  { "up", 192, {0, {{{0, 0}}}}, 0, 0 },
601 
  { "cup", 193, {0, {{{0, 0}}}}, 0, 0 },
602 
  { "vup", 194, {0, {{{0, 0}}}}, 0, 0 },
603 
  { "cvup", 195, {0, {{{0, 0}}}}, 0, 0 },
604 
  { "zup", 196, {0, {{{0, 0}}}}, 0, 0 },
605 
  { "czup", 197, {0, {{{0, 0}}}}, 0, 0 },
606 
  { "vzup", 198, {0, {{{0, 0}}}}, 0, 0 },
607 
  { "cvzup", 199, {0, {{{0, 0}}}}, 0, 0 },
608 
  { "nup", 200, {0, {{{0, 0}}}}, 0, 0 },
609 
  { "cnup", 201, {0, {{{0, 0}}}}, 0, 0 },
610 
  { "vnup", 202, {0, {{{0, 0}}}}, 0, 0 },
611 
  { "cvnup", 203, {0, {{{0, 0}}}}, 0, 0 },
612 
  { "znup", 204, {0, {{{0, 0}}}}, 0, 0 },
613 
  { "cznup", 205, {0, {{{0, 0}}}}, 0, 0 },
614 
  { "vznup", 206, {0, {{{0, 0}}}}, 0, 0 },
615 
  { "cvznup", 207, {0, {{{0, 0}}}}, 0, 0 },
616 
  { "xup", 208, {0, {{{0, 0}}}}, 0, 0 },
617 
  { "cxup", 209, {0, {{{0, 0}}}}, 0, 0 },
618 
  { "vxup", 210, {0, {{{0, 0}}}}, 0, 0 },
619 
  { "cvxup", 211, {0, {{{0, 0}}}}, 0, 0 },
620 
  { "zxup", 212, {0, {{{0, 0}}}}, 0, 0 },
621 
  { "czxup", 213, {0, {{{0, 0}}}}, 0, 0 },
622 
  { "vzxup", 214, {0, {{{0, 0}}}}, 0, 0 },
623 
  { "cvzxup", 215, {0, {{{0, 0}}}}, 0, 0 },
624 
  { "nxup", 216, {0, {{{0, 0}}}}, 0, 0 },
625 
  { "cnxup", 217, {0, {{{0, 0}}}}, 0, 0 },
626 
  { "vnxup", 218, {0, {{{0, 0}}}}, 0, 0 },
627 
  { "cvnxup", 219, {0, {{{0, 0}}}}, 0, 0 },
628 
  { "znxup", 220, {0, {{{0, 0}}}}, 0, 0 },
629 
  { "cznxup", 221, {0, {{{0, 0}}}}, 0, 0 },
630 
  { "vznxup", 222, {0, {{{0, 0}}}}, 0, 0 },
631 
  { "cvznxup", 223, {0, {{{0, 0}}}}, 0, 0 },
632 
  { "iup", 224, {0, {{{0, 0}}}}, 0, 0 },
633 
  { "ciup", 225, {0, {{{0, 0}}}}, 0, 0 },
634 
  { "viup", 226, {0, {{{0, 0}}}}, 0, 0 },
635 
  { "cviup", 227, {0, {{{0, 0}}}}, 0, 0 },
636 
  { "ziup", 228, {0, {{{0, 0}}}}, 0, 0 },
637 
  { "cziup", 229, {0, {{{0, 0}}}}, 0, 0 },
638 
  { "vziup", 230, {0, {{{0, 0}}}}, 0, 0 },
639 
  { "cvziup", 231, {0, {{{0, 0}}}}, 0, 0 },
640 
  { "niup", 232, {0, {{{0, 0}}}}, 0, 0 },
641 
  { "cniup", 233, {0, {{{0, 0}}}}, 0, 0 },
642 
  { "vniup", 234, {0, {{{0, 0}}}}, 0, 0 },
643 
  { "cvniup", 235, {0, {{{0, 0}}}}, 0, 0 },
644 
  { "zniup", 236, {0, {{{0, 0}}}}, 0, 0 },
645 
  { "czniup", 237, {0, {{{0, 0}}}}, 0, 0 },
646 
  { "vzniup", 238, {0, {{{0, 0}}}}, 0, 0 },
647 
  { "cvzniup", 239, {0, {{{0, 0}}}}, 0, 0 },
648 
  { "xiup", 240, {0, {{{0, 0}}}}, 0, 0 },
649 
  { "cxiup", 241, {0, {{{0, 0}}}}, 0, 0 },
650 
  { "vxiup", 242, {0, {{{0, 0}}}}, 0, 0 },
651 
  { "cvxiup", 243, {0, {{{0, 0}}}}, 0, 0 },
652 
  { "zxiup", 244, {0, {{{0, 0}}}}, 0, 0 },
653 
  { "czxiup", 245, {0, {{{0, 0}}}}, 0, 0 },
654 
  { "vzxiup", 246, {0, {{{0, 0}}}}, 0, 0 },
655 
  { "cvzxiup", 247, {0, {{{0, 0}}}}, 0, 0 },
656 
  { "nxiup", 248, {0, {{{0, 0}}}}, 0, 0 },
657 
  { "cnxiup", 249, {0, {{{0, 0}}}}, 0, 0 },
658 
  { "vnxiup", 250, {0, {{{0, 0}}}}, 0, 0 },
659 
  { "cvnxiup", 251, {0, {{{0, 0}}}}, 0, 0 },
660 
  { "znxiup", 252, {0, {{{0, 0}}}}, 0, 0 },
661 
  { "cznxiup", 253, {0, {{{0, 0}}}}, 0, 0 },
662 
  { "vznxiup", 254, {0, {{{0, 0}}}}, 0, 0 },
663 
  { "cvznxiup", 255, {0, {{{0, 0}}}}, 0, 0 }
664 
};
665 
 
666 
CGEN_KEYWORD cris_cgen_opval_h_flagbits =
667 
{
668 
  & cris_cgen_opval_h_flagbits_entries[0],
669 
  256,
670 
  0, 0, 0, 0, ""
671 
};
672 
 
673 
static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] =
674 
{
675 
  { "S0", 0, {0, {{{0, 0}}}}, 0, 0 },
676 
  { "S1", 1, {0, {{{0, 0}}}}, 0, 0 },
677 
  { "S2", 2, {0, {{{0, 0}}}}, 0, 0 },
678 
  { "S3", 3, {0, {{{0, 0}}}}, 0, 0 },
679 
  { "S4", 4, {0, {{{0, 0}}}}, 0, 0 },
680 
  { "S5", 5, {0, {{{0, 0}}}}, 0, 0 },
681 
  { "S6", 6, {0, {{{0, 0}}}}, 0, 0 },
682 
  { "S7", 7, {0, {{{0, 0}}}}, 0, 0 },
683 
  { "S8", 8, {0, {{{0, 0}}}}, 0, 0 },
684 
  { "S9", 9, {0, {{{0, 0}}}}, 0, 0 },
685 
  { "S10", 10, {0, {{{0, 0}}}}, 0, 0 },
686 
  { "S11", 11, {0, {{{0, 0}}}}, 0, 0 },
687 
  { "S12", 12, {0, {{{0, 0}}}}, 0, 0 },
688 
  { "S13", 13, {0, {{{0, 0}}}}, 0, 0 },
689 
  { "S14", 14, {0, {{{0, 0}}}}, 0, 0 },
690 
  { "S15", 15, {0, {{{0, 0}}}}, 0, 0 }
691 
};
692 
 
693 
CGEN_KEYWORD cris_cgen_opval_h_supr =
694 
{
695 
  & cris_cgen_opval_h_supr_entries[0],
696 
  16,
697 
  0, 0, 0, 0, ""
698 
};
699 
 
700 
 
701 
/* The hardware table.  */
702 
 
703 
#define A(a) (1 << CGEN_HW_##a)
704 
 
705 
const CGEN_HW_ENTRY cris_cgen_hw_table[] =
706 
{
707 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
708 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
709 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
710 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
711 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
712 
  { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
713 
  { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
714 
  { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
715 
  { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
716 
  { "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
717 
  { "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
718 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
719 
  { "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
720 
  { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
721 
  { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
722 
  { "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
723 
  { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
724 
  { "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
725 
  { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
726 
  { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
727 
  { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
728 
  { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
729 
  { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
730 
  { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
731 
  { "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
732 
  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
733 
  { "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
734 
  { "h-cbit-move-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
735 
  { "h-cbit-move-pre-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
736 
  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
737 
  { "h-vbit-move", HW_H_VBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
738 
  { "h-vbit-move-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
739 
  { "h-vbit-move-pre-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
740 
  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
741 
  { "h-zbit-move", HW_H_ZBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
742 
  { "h-zbit-move-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
743 
  { "h-zbit-move-pre-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
744 
  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
745 
  { "h-nbit-move", HW_H_NBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
746 
  { "h-nbit-move-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
747 
  { "h-nbit-move-pre-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
748 
  { "h-xbit", HW_H_XBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
749 
  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
750 
  { "h-ibit-pre-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
751 
  { "h-pbit", HW_H_PBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
752 
  { "h-rbit", HW_H_RBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
753 
  { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
754 
  { "h-ubit-pre-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
755 
  { "h-gbit", HW_H_GBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
756 
  { "h-kernel-sp", HW_H_KERNEL_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
757 
  { "h-ubit-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
758 
  { "h-ibit-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
759 
  { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
760 
  { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
761 
  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
762 
  { "h-insn-prefixed-p", HW_H_INSN_PREFIXED_P, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
763 
  { "h-insn-prefixed-p-pre-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
764 
  { "h-insn-prefixed-p-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
765 
  { "h-prefixreg-pre-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
766 
  { "h-prefixreg-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
767 
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
768 
};
769 
 
770 
#undef A
771 
 
772 
 
773 
/* The instruction field table.  */
774 
 
775 
#define A(a) (1 << CGEN_IFLD_##a)
776 
 
777 
const CGEN_IFLD cris_cgen_ifld_table[] =
778 
{
779 
  { CRIS_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
780 
  { CRIS_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
781 
  { CRIS_F_OPERAND1, "f-operand1", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
782 
  { CRIS_F_SIZE, "f-size", 0, 16, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
783 
  { CRIS_F_OPCODE, "f-opcode", 0, 16, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
784 
  { CRIS_F_MODE, "f-mode", 0, 16, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
785 
  { CRIS_F_OPERAND2, "f-operand2", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
786 
  { CRIS_F_MEMMODE, "f-memmode", 0, 16, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
787 
  { CRIS_F_MEMBIT, "f-membit", 0, 16, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
788 
  { CRIS_F_B5, "f-b5", 0, 16, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
789 
  { CRIS_F_OPCODE_HI, "f-opcode-hi", 0, 16, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
790 
  { CRIS_F_DSTSRC, "f-dstsrc", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
791 
  { CRIS_F_U6, "f-u6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
792 
  { CRIS_F_S6, "f-s6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
793 
  { CRIS_F_U5, "f-u5", 0, 16, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
794 
  { CRIS_F_U4, "f-u4", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
795 
  { CRIS_F_S8, "f-s8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
796 
  { CRIS_F_DISP9_HI, "f-disp9-hi", 0, 16, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
797 
  { CRIS_F_DISP9_LO, "f-disp9-lo", 0, 16, 7, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
798 
  { CRIS_F_DISP9, "f-disp9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
799 
  { CRIS_F_QO, "f-qo", 0, 16, 3, 4, { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } }  },
800 
  { CRIS_F_INDIR_PC__BYTE, "f-indir-pc+-byte", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
801 
  { CRIS_F_INDIR_PC__WORD, "f-indir-pc+-word", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
802 
  { CRIS_F_INDIR_PC__WORD_PCREL, "f-indir-pc+-word-pcrel", 16, 16, 15, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
803 
  { CRIS_F_INDIR_PC__DWORD, "f-indir-pc+-dword", 16, 32, 31, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
804 
  { CRIS_F_INDIR_PC__DWORD_PCREL, "f-indir-pc+-dword-pcrel", 16, 32, 31, 32, { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } }  },
805 
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
806 
};
807 
 
808 
#undef A
809 
 
810 
 
811 
 
812 
/* multi ifield declarations */
813 
 
814 
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [];
815 
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [];
816 
 
817 
 
818 
/* multi ifield definitions */
819 
 
820 
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] =
821 
{
822 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
823 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
824 
    { 0, { (const PTR) 0 } }
825 
};
826 
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] =
827 
{
828 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
829 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
830 
    { 0, { (const PTR) 0 } }
831 
};
832 
 
833 
/* The operand table.  */
834 
 
835 
#define A(a) (1 << CGEN_OPERAND_##a)
836 
#define OPERAND(op) CRIS_OPERAND_##op
837 
 
838 
const CGEN_OPERAND cris_cgen_operand_table[] =
839 
{
840 
/* pc: program counter */
841 
  { "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0,
842 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_NIL] } },
843 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
844 
/* cbit:  */
845 
  { "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0,
846 
    { 0, { (const PTR) 0 } },
847 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
848 
/* cbit-move: cbit for pre-V32, nothing for newer */
849 
  { "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0,
850 
    { 0, { (const PTR) 0 } },
851 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
852 
/* vbit:  */
853 
  { "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0,
854 
    { 0, { (const PTR) 0 } },
855 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
856 
/* vbit-move: vbit for pre-V32, nothing for newer */
857 
  { "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0,
858 
    { 0, { (const PTR) 0 } },
859 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
860 
/* zbit:  */
861 
  { "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
862 
    { 0, { (const PTR) 0 } },
863 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
864 
/* zbit-move: zbit for pre-V32, nothing for newer */
865 
  { "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0,
866 
    { 0, { (const PTR) 0 } },
867 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
868 
/* nbit:  */
869 
  { "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0,
870 
    { 0, { (const PTR) 0 } },
871 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
872 
/* nbit-move: nbit for pre-V32, nothing for newer */
873 
  { "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0,
874 
    { 0, { (const PTR) 0 } },
875 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
876 
/* xbit:  */
877 
  { "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0,
878 
    { 0, { (const PTR) 0 } },
879 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
880 
/* ibit:  */
881 
  { "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0,
882 
    { 0, { (const PTR) 0 } },
883 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
884 
/* ubit:  */
885 
  { "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0,
886 
    { 0, { (const PTR) 0 } },
887 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }  },
888 
/* pbit:  */
889 
  { "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0,
890 
    { 0, { (const PTR) 0 } },
891 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }  },
892 
/* rbit: carry bit for MCP+restore-P flag bit */
893 
  { "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0,
894 
    { 0, { (const PTR) 0 } },
895 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } }  },
896 
/* sbit:  */
897 
  { "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0,
898 
    { 0, { (const PTR) 0 } },
899 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } }  },
900 
/* mbit:  */
901 
  { "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0,
902 
    { 0, { (const PTR) 0 } },
903 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } }  },
904 
/* qbit:  */
905 
  { "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0,
906 
    { 0, { (const PTR) 0 } },
907 
    { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } }  },
908 
/* prefix-set: Instruction-prefixed flag */
909 
  { "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0,
910 
    { 0, { (const PTR) 0 } },
911 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
912 
/* prefixreg: Prefix address */
913 
  { "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0,
914 
    { 0, { (const PTR) 0 } },
915 
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
916 
/* Rs: Source general register */
917 
  { "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4,
918 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
919 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
920 
/* inc: Incrementness of indirect operand */
921 
  { "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1,
922 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
923 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
924 
/* Ps: Source special register */
925 
  { "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4,
926 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
927 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
928 
/* Ss: Source support register */
929 
  { "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4,
930 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
931 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }  },
932 
/* Sd: Destination support register */
933 
  { "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4,
934 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
935 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }  },
936 
/* i: Quick signed 6-bit */
937 
  { "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6,
938 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S6] } },
939 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
940 
/* j: Quick unsigned 6-bit */
941 
  { "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6,
942 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U6] } },
943 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
944 
/* c: Quick unsigned 5-bit */
945 
  { "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5,
946 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U5] } },
947 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
948 
/* qo: Quick unsigned 4-bit, PC-relative */
949 
  { "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4,
950 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_QO] } },
951 
    { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } }  },
952 
/* Rd: Destination general register */
953 
  { "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4,
954 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
955 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
956 
/* sconst8: Signed byte [PC+] */
957 
  { "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16,
958 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
959 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
960 
/* uconst8: Unsigned byte [PC+] */
961 
  { "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16,
962 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
963 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
964 
/* sconst16: Signed word [PC+] */
965 
  { "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16,
966 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
967 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
968 
/* uconst16: Unsigned word [PC+] */
969 
  { "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16,
970 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
971 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
972 
/* const32: Dword [PC+] */
973 
  { "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32,
974 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
975 
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
976 
/* const32-pcrel: Dword [PC+] */
977 
  { "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32,
978 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
979 
    { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } }  },
980 
/* Pd: Destination special register */
981 
  { "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4,
982 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
983 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
984 
/* o: Signed 8-bit */
985 
  { "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8,
986 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S8] } },
987 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
988 
/* o-pcrel: 9-bit signed immediate PC-rel */
989 
  { "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8,
990 
    { 2, { (const PTR) &CRIS_F_DISP9_MULTI_IFIELD[0] } },
991 
    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
992 
/* o-word-pcrel: 16-bit signed immediate PC-rel */
993 
  { "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16,
994 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
995 
    { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
996 
/* cc: Condition codes */
997 
  { "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4,
998 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
999 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
1000 
/* n: Quick unsigned 4-bit */
1001 
  { "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4,
1002 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U4] } },
1003 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
1004 
/* swapoption: Swap option */
1005 
  { "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4,
1006 
    { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
1007 
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
1008 
/* list-of-flags: Flag bits as operand */
1009 
  { "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8,
1010 
    { 2, { (const PTR) &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
1011 
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
1012 
/* sentinel */
1013 
  { 0, 0, 0, 0, 0,
1014 
    { 0, { (const PTR) 0 } },
1015 
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
1016 
};
1017 
 
1018 
#undef A
1019 
 
1020 
 
1021 
/* The instruction table.  */
1022 
 
1023 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1024 
#define A(a) (1 << CGEN_INSN_##a)
1025 
 
1026 
static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] =
1027 
{
1028 
  /* Special null first entry.
1029 
     A `num' value of zero is thus invalid.
1030 
     Also, the special `invalid' insn resides here.  */
1031 
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
1032 
/* nop */
1033 
  {
1034 
    CRIS_INSN_NOP, "nop", "nop", 16,
1035 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1036 
  },
1037 
/* move.b move.m ${Rs},${Rd} */
1038 
  {
1039 
    CRIS_INSN_MOVE_B_R, "move.b-r", "move.b", 16,
1040 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1041 
  },
1042 
/* move.w move.m ${Rs},${Rd} */
1043 
  {
1044 
    CRIS_INSN_MOVE_W_R, "move.w-r", "move.w", 16,
1045 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1046 
  },
1047 
/* move.d move.m ${Rs},${Rd} */
1048 
  {
1049 
    CRIS_INSN_MOVE_D_R, "move.d-r", "move.d", 16,
1050 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1051 
  },
1052 
/* move.d PC,${Rd} */
1053 
  {
1054 
    CRIS_INSN_MOVEPCR, "movepcr", "move.d", 16,
1055 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1056 
  },
1057 
/* moveq $i,$Rd */
1058 
  {
1059 
    CRIS_INSN_MOVEQ, "moveq", "moveq", 16,
1060 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1061 
  },
1062 
/* movs.b movs.m ${Rs},${Rd} */
1063 
  {
1064 
    CRIS_INSN_MOVS_B_R, "movs.b-r", "movs.b", 16,
1065 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1066 
  },
1067 
/* movs.w movs.m ${Rs},${Rd} */
1068 
  {
1069 
    CRIS_INSN_MOVS_W_R, "movs.w-r", "movs.w", 16,
1070 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1071 
  },
1072 
/* movu.b movu.m ${Rs},${Rd} */
1073 
  {
1074 
    CRIS_INSN_MOVU_B_R, "movu.b-r", "movu.b", 16,
1075 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1076 
  },
1077 
/* movu.w movu.m ${Rs},${Rd} */
1078 
  {
1079 
    CRIS_INSN_MOVU_W_R, "movu.w-r", "movu.w", 16,
1080 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1081 
  },
1082 
/* move.b ${sconst8},${Rd} */
1083 
  {
1084 
    CRIS_INSN_MOVECBR, "movecbr", "move.b", 32,
1085 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1086 
  },
1087 
/* move.w ${sconst16},${Rd} */
1088 
  {
1089 
    CRIS_INSN_MOVECWR, "movecwr", "move.w", 32,
1090 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1091 
  },
1092 
/* move.d ${const32},${Rd} */
1093 
  {
1094 
    CRIS_INSN_MOVECDR, "movecdr", "move.d", 48,
1095 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1096 
  },
1097 
/* movs.b ${sconst8},${Rd} */
1098 
  {
1099 
    CRIS_INSN_MOVSCBR, "movscbr", "movs.b", 32,
1100 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1101 
  },
1102 
/* movs.w ${sconst16},${Rd} */
1103 
  {
1104 
    CRIS_INSN_MOVSCWR, "movscwr", "movs.w", 32,
1105 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1106 
  },
1107 
/* movu.b ${uconst8},${Rd} */
1108 
  {
1109 
    CRIS_INSN_MOVUCBR, "movucbr", "movu.b", 32,
1110 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1111 
  },
1112 
/* movu.w ${uconst16},${Rd} */
1113 
  {
1114 
    CRIS_INSN_MOVUCWR, "movucwr", "movu.w", 32,
1115 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1116 
  },
1117 
/* addq $j,$Rd */
1118 
  {
1119 
    CRIS_INSN_ADDQ, "addq", "addq", 16,
1120 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1121 
  },
1122 
/* subq $j,$Rd */
1123 
  {
1124 
    CRIS_INSN_SUBQ, "subq", "subq", 16,
1125 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1126 
  },
1127 
/* cmp-r.b $Rs,$Rd */
1128 
  {
1129 
    CRIS_INSN_CMP_R_B_R, "cmp-r.b-r", "cmp-r.b", 16,
1130 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1131 
  },
1132 
/* cmp-r.w $Rs,$Rd */
1133 
  {
1134 
    CRIS_INSN_CMP_R_W_R, "cmp-r.w-r", "cmp-r.w", 16,
1135 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1136 
  },
1137 
/* cmp-r.d $Rs,$Rd */
1138 
  {
1139 
    CRIS_INSN_CMP_R_D_R, "cmp-r.d-r", "cmp-r.d", 16,
1140 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1141 
  },
1142 
/* cmp-m.b [${Rs}${inc}],${Rd} */
1143 
  {
1144 
    CRIS_INSN_CMP_M_B_M, "cmp-m.b-m", "cmp-m.b", 16,
1145 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1146 
  },
1147 
/* cmp-m.w [${Rs}${inc}],${Rd} */
1148 
  {
1149 
    CRIS_INSN_CMP_M_W_M, "cmp-m.w-m", "cmp-m.w", 16,
1150 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1151 
  },
1152 
/* cmp-m.d [${Rs}${inc}],${Rd} */
1153 
  {
1154 
    CRIS_INSN_CMP_M_D_M, "cmp-m.d-m", "cmp-m.d", 16,
1155 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1156 
  },
1157 
/* cmp.b $sconst8,$Rd */
1158 
  {
1159 
    CRIS_INSN_CMPCBR, "cmpcbr", "cmp.b", 32,
1160 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1161 
  },
1162 
/* cmp.w $sconst16,$Rd */
1163 
  {
1164 
    CRIS_INSN_CMPCWR, "cmpcwr", "cmp.w", 32,
1165 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1166 
  },
1167 
/* cmp.d $const32,$Rd */
1168 
  {
1169 
    CRIS_INSN_CMPCDR, "cmpcdr", "cmp.d", 48,
1170 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1171 
  },
1172 
/* cmpq $i,$Rd */
1173 
  {
1174 
    CRIS_INSN_CMPQ, "cmpq", "cmpq", 16,
1175 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1176 
  },
1177 
/* cmps-m.b [${Rs}${inc}],$Rd */
1178 
  {
1179 
    CRIS_INSN_CMPS_M_B_M, "cmps-m.b-m", "cmps-m.b", 16,
1180 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1181 
  },
1182 
/* cmps-m.w [${Rs}${inc}],$Rd */
1183 
  {
1184 
    CRIS_INSN_CMPS_M_W_M, "cmps-m.w-m", "cmps-m.w", 16,
1185 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1186 
  },
1187 
/* [${Rs}${inc}],$Rd */
1188 
  {
1189 
    CRIS_INSN_CMPSCBR, "cmpscbr", "[", 32,
1190 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1191 
  },
1192 
/* [${Rs}${inc}],$Rd */
1193 
  {
1194 
    CRIS_INSN_CMPSCWR, "cmpscwr", "[", 32,
1195 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1196 
  },
1197 
/* cmpu-m.b [${Rs}${inc}],$Rd */
1198 
  {
1199 
    CRIS_INSN_CMPU_M_B_M, "cmpu-m.b-m", "cmpu-m.b", 16,
1200 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1201 
  },
1202 
/* cmpu-m.w [${Rs}${inc}],$Rd */
1203 
  {
1204 
    CRIS_INSN_CMPU_M_W_M, "cmpu-m.w-m", "cmpu-m.w", 16,
1205 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1206 
  },
1207 
/* [${Rs}${inc}],$Rd */
1208 
  {
1209 
    CRIS_INSN_CMPUCBR, "cmpucbr", "[", 32,
1210 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1211 
  },
1212 
/* [${Rs}${inc}],$Rd */
1213 
  {
1214 
    CRIS_INSN_CMPUCWR, "cmpucwr", "[", 32,
1215 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1216 
  },
1217 
/* move-m.b [${Rs}${inc}],${Rd} */
1218 
  {
1219 
    CRIS_INSN_MOVE_M_B_M, "move-m.b-m", "move-m.b", 16,
1220 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1221 
  },
1222 
/* move-m.w [${Rs}${inc}],${Rd} */
1223 
  {
1224 
    CRIS_INSN_MOVE_M_W_M, "move-m.w-m", "move-m.w", 16,
1225 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1226 
  },
1227 
/* move-m.d [${Rs}${inc}],${Rd} */
1228 
  {
1229 
    CRIS_INSN_MOVE_M_D_M, "move-m.d-m", "move-m.d", 16,
1230 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1231 
  },
1232 
/* movs-m.b [${Rs}${inc}],${Rd} */
1233 
  {
1234 
    CRIS_INSN_MOVS_M_B_M, "movs-m.b-m", "movs-m.b", 16,
1235 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1236 
  },
1237 
/* movs-m.w [${Rs}${inc}],${Rd} */
1238 
  {
1239 
    CRIS_INSN_MOVS_M_W_M, "movs-m.w-m", "movs-m.w", 16,
1240 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1241 
  },
1242 
/* movu-m.b [${Rs}${inc}],${Rd} */
1243 
  {
1244 
    CRIS_INSN_MOVU_M_B_M, "movu-m.b-m", "movu-m.b", 16,
1245 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1246 
  },
1247 
/* movu-m.w [${Rs}${inc}],${Rd} */
1248 
  {
1249 
    CRIS_INSN_MOVU_M_W_M, "movu-m.w-m", "movu-m.w", 16,
1250 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1251 
  },
1252 
/* move ${Rs},${Pd} */
1253 
  {
1254 
    CRIS_INSN_MOVE_R_SPRV0, "move-r-sprv0", "move", 16,
1255 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1256 
  },
1257 
/* move ${Rs},${Pd} */
1258 
  {
1259 
    CRIS_INSN_MOVE_R_SPRV3, "move-r-sprv3", "move", 16,
1260 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1261 
  },
1262 
/* move ${Rs},${Pd} */
1263 
  {
1264 
    CRIS_INSN_MOVE_R_SPRV8, "move-r-sprv8", "move", 16,
1265 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1266 
  },
1267 
/* move ${Rs},${Pd} */
1268 
  {
1269 
    CRIS_INSN_MOVE_R_SPRV10, "move-r-sprv10", "move", 16,
1270 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1271 
  },
1272 
/* move ${Rs},${Pd} */
1273 
  {
1274 
    CRIS_INSN_MOVE_R_SPRV32, "move-r-sprv32", "move", 16,
1275 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1276 
  },
1277 
/* move ${Ps},${Rd-sfield} */
1278 
  {
1279 
    CRIS_INSN_MOVE_SPR_RV0, "move-spr-rv0", "move", 16,
1280 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1281 
  },
1282 
/* move ${Ps},${Rd-sfield} */
1283 
  {
1284 
    CRIS_INSN_MOVE_SPR_RV3, "move-spr-rv3", "move", 16,
1285 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1286 
  },
1287 
/* move ${Ps},${Rd-sfield} */
1288 
  {
1289 
    CRIS_INSN_MOVE_SPR_RV8, "move-spr-rv8", "move", 16,
1290 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1291 
  },
1292 
/* move ${Ps},${Rd-sfield} */
1293 
  {
1294 
    CRIS_INSN_MOVE_SPR_RV10, "move-spr-rv10", "move", 16,
1295 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1296 
  },
1297 
/* move ${Ps},${Rd-sfield} */
1298 
  {
1299 
    CRIS_INSN_MOVE_SPR_RV32, "move-spr-rv32", "move", 16,
1300 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1301 
  },
1302 
/* ret/reti/retb */
1303 
  {
1304 
    CRIS_INSN_RET_TYPE, "ret-type", "ret/reti/retb", 16,
1305 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1306 
  },
1307 
/* move [${Rs}${inc}],${Pd} */
1308 
  {
1309 
    CRIS_INSN_MOVE_M_SPRV0, "move-m-sprv0", "move", 16,
1310 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1311 
  },
1312 
/* move [${Rs}${inc}],${Pd} */
1313 
  {
1314 
    CRIS_INSN_MOVE_M_SPRV3, "move-m-sprv3", "move", 16,
1315 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1316 
  },
1317 
/* move [${Rs}${inc}],${Pd} */
1318 
  {
1319 
    CRIS_INSN_MOVE_M_SPRV8, "move-m-sprv8", "move", 16,
1320 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1321 
  },
1322 
/* move [${Rs}${inc}],${Pd} */
1323 
  {
1324 
    CRIS_INSN_MOVE_M_SPRV10, "move-m-sprv10", "move", 16,
1325 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1326 
  },
1327 
/* move [${Rs}${inc}],${Pd} */
1328 
  {
1329 
    CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16,
1330 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1331 
  },
1332 
/* move ${sconst16},${Pd} */
1333 
  {
1334 
    CRIS_INSN_MOVE_C_SPRV0_P5, "move-c-sprv0-p5", "move", 32,
1335 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1336 
  },
1337 
/* move ${const32},${Pd} */
1338 
  {
1339 
    CRIS_INSN_MOVE_C_SPRV0_P9, "move-c-sprv0-p9", "move", 48,
1340 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1341 
  },
1342 
/* move ${const32},${Pd} */
1343 
  {
1344 
    CRIS_INSN_MOVE_C_SPRV0_P10, "move-c-sprv0-p10", "move", 48,
1345 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1346 
  },
1347 
/* move ${const32},${Pd} */
1348 
  {
1349 
    CRIS_INSN_MOVE_C_SPRV0_P11, "move-c-sprv0-p11", "move", 48,
1350 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1351 
  },
1352 
/* move ${const32},${Pd} */
1353 
  {
1354 
    CRIS_INSN_MOVE_C_SPRV0_P12, "move-c-sprv0-p12", "move", 48,
1355 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1356 
  },
1357 
/* move ${const32},${Pd} */
1358 
  {
1359 
    CRIS_INSN_MOVE_C_SPRV0_P13, "move-c-sprv0-p13", "move", 48,
1360 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1361 
  },
1362 
/* move ${sconst16},${Pd} */
1363 
  {
1364 
    CRIS_INSN_MOVE_C_SPRV0_P6, "move-c-sprv0-p6", "move", 32,
1365 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1366 
  },
1367 
/* move ${sconst16},${Pd} */
1368 
  {
1369 
    CRIS_INSN_MOVE_C_SPRV0_P7, "move-c-sprv0-p7", "move", 32,
1370 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1371 
  },
1372 
/* move ${sconst16},${Pd} */
1373 
  {
1374 
    CRIS_INSN_MOVE_C_SPRV3_P5, "move-c-sprv3-p5", "move", 32,
1375 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1376 
  },
1377 
/* move ${const32},${Pd} */
1378 
  {
1379 
    CRIS_INSN_MOVE_C_SPRV3_P9, "move-c-sprv3-p9", "move", 48,
1380 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1381 
  },
1382 
/* move ${const32},${Pd} */
1383 
  {
1384 
    CRIS_INSN_MOVE_C_SPRV3_P10, "move-c-sprv3-p10", "move", 48,
1385 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1386 
  },
1387 
/* move ${const32},${Pd} */
1388 
  {
1389 
    CRIS_INSN_MOVE_C_SPRV3_P11, "move-c-sprv3-p11", "move", 48,
1390 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1391 
  },
1392 
/* move ${const32},${Pd} */
1393 
  {
1394 
    CRIS_INSN_MOVE_C_SPRV3_P12, "move-c-sprv3-p12", "move", 48,
1395 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1396 
  },
1397 
/* move ${const32},${Pd} */
1398 
  {
1399 
    CRIS_INSN_MOVE_C_SPRV3_P13, "move-c-sprv3-p13", "move", 48,
1400 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1401 
  },
1402 
/* move ${sconst16},${Pd} */
1403 
  {
1404 
    CRIS_INSN_MOVE_C_SPRV3_P6, "move-c-sprv3-p6", "move", 32,
1405 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1406 
  },
1407 
/* move ${sconst16},${Pd} */
1408 
  {
1409 
    CRIS_INSN_MOVE_C_SPRV3_P7, "move-c-sprv3-p7", "move", 32,
1410 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1411 
  },
1412 
/* move ${const32},${Pd} */
1413 
  {
1414 
    CRIS_INSN_MOVE_C_SPRV3_P14, "move-c-sprv3-p14", "move", 48,
1415 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1416 
  },
1417 
/* move ${sconst16},${Pd} */
1418 
  {
1419 
    CRIS_INSN_MOVE_C_SPRV8_P5, "move-c-sprv8-p5", "move", 32,
1420 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1421 
  },
1422 
/* move ${const32},${Pd} */
1423 
  {
1424 
    CRIS_INSN_MOVE_C_SPRV8_P9, "move-c-sprv8-p9", "move", 48,
1425 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1426 
  },
1427 
/* move ${const32},${Pd} */
1428 
  {
1429 
    CRIS_INSN_MOVE_C_SPRV8_P10, "move-c-sprv8-p10", "move", 48,
1430 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1431 
  },
1432 
/* move ${const32},${Pd} */
1433 
  {
1434 
    CRIS_INSN_MOVE_C_SPRV8_P11, "move-c-sprv8-p11", "move", 48,
1435 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1436 
  },
1437 
/* move ${const32},${Pd} */
1438 
  {
1439 
    CRIS_INSN_MOVE_C_SPRV8_P12, "move-c-sprv8-p12", "move", 48,
1440 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1441 
  },
1442 
/* move ${const32},${Pd} */
1443 
  {
1444 
    CRIS_INSN_MOVE_C_SPRV8_P13, "move-c-sprv8-p13", "move", 48,
1445 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1446 
  },
1447 
/* move ${const32},${Pd} */
1448 
  {
1449 
    CRIS_INSN_MOVE_C_SPRV8_P14, "move-c-sprv8-p14", "move", 48,
1450 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1451 
  },
1452 
/* move ${sconst16},${Pd} */
1453 
  {
1454 
    CRIS_INSN_MOVE_C_SPRV10_P5, "move-c-sprv10-p5", "move", 32,
1455 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1456 
  },
1457 
/* move ${const32},${Pd} */
1458 
  {
1459 
    CRIS_INSN_MOVE_C_SPRV10_P9, "move-c-sprv10-p9", "move", 48,
1460 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1461 
  },
1462 
/* move ${const32},${Pd} */
1463 
  {
1464 
    CRIS_INSN_MOVE_C_SPRV10_P10, "move-c-sprv10-p10", "move", 48,
1465 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1466 
  },
1467 
/* move ${const32},${Pd} */
1468 
  {
1469 
    CRIS_INSN_MOVE_C_SPRV10_P11, "move-c-sprv10-p11", "move", 48,
1470 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1471 
  },
1472 
/* move ${const32},${Pd} */
1473 
  {
1474 
    CRIS_INSN_MOVE_C_SPRV10_P12, "move-c-sprv10-p12", "move", 48,
1475 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1476 
  },
1477 
/* move ${const32},${Pd} */
1478 
  {
1479 
    CRIS_INSN_MOVE_C_SPRV10_P13, "move-c-sprv10-p13", "move", 48,
1480 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1481 
  },
1482 
/* move ${const32},${Pd} */
1483 
  {
1484 
    CRIS_INSN_MOVE_C_SPRV10_P7, "move-c-sprv10-p7", "move", 48,
1485 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1486 
  },
1487 
/* move ${const32},${Pd} */
1488 
  {
1489 
    CRIS_INSN_MOVE_C_SPRV10_P14, "move-c-sprv10-p14", "move", 48,
1490 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1491 
  },
1492 
/* move ${const32},${Pd} */
1493 
  {
1494 
    CRIS_INSN_MOVE_C_SPRV10_P15, "move-c-sprv10-p15", "move", 48,
1495 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1496 
  },
1497 
/* move ${const32},${Pd} */
1498 
  {
1499 
    CRIS_INSN_MOVE_C_SPRV32_P2, "move-c-sprv32-p2", "move", 48,
1500 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1501 
  },
1502 
/* move ${const32},${Pd} */
1503 
  {
1504 
    CRIS_INSN_MOVE_C_SPRV32_P3, "move-c-sprv32-p3", "move", 48,
1505 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1506 
  },
1507 
/* move ${const32},${Pd} */
1508 
  {
1509 
    CRIS_INSN_MOVE_C_SPRV32_P5, "move-c-sprv32-p5", "move", 48,
1510 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1511 
  },
1512 
/* move ${const32},${Pd} */
1513 
  {
1514 
    CRIS_INSN_MOVE_C_SPRV32_P6, "move-c-sprv32-p6", "move", 48,
1515 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1516 
  },
1517 
/* move ${const32},${Pd} */
1518 
  {
1519 
    CRIS_INSN_MOVE_C_SPRV32_P7, "move-c-sprv32-p7", "move", 48,
1520 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1521 
  },
1522 
/* move ${const32},${Pd} */
1523 
  {
1524 
    CRIS_INSN_MOVE_C_SPRV32_P9, "move-c-sprv32-p9", "move", 48,
1525 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1526 
  },
1527 
/* move ${const32},${Pd} */
1528 
  {
1529 
    CRIS_INSN_MOVE_C_SPRV32_P10, "move-c-sprv32-p10", "move", 48,
1530 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1531 
  },
1532 
/* move ${const32},${Pd} */
1533 
  {
1534 
    CRIS_INSN_MOVE_C_SPRV32_P11, "move-c-sprv32-p11", "move", 48,
1535 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1536 
  },
1537 
/* move ${const32},${Pd} */
1538 
  {
1539 
    CRIS_INSN_MOVE_C_SPRV32_P12, "move-c-sprv32-p12", "move", 48,
1540 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1541 
  },
1542 
/* move ${const32},${Pd} */
1543 
  {
1544 
    CRIS_INSN_MOVE_C_SPRV32_P13, "move-c-sprv32-p13", "move", 48,
1545 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1546 
  },
1547 
/* move ${const32},${Pd} */
1548 
  {
1549 
    CRIS_INSN_MOVE_C_SPRV32_P14, "move-c-sprv32-p14", "move", 48,
1550 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1551 
  },
1552 
/* move ${const32},${Pd} */
1553 
  {
1554 
    CRIS_INSN_MOVE_C_SPRV32_P15, "move-c-sprv32-p15", "move", 48,
1555 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1556 
  },
1557 
/* move ${Ps},[${Rd-sfield}${inc}] */
1558 
  {
1559 
    CRIS_INSN_MOVE_SPR_MV0, "move-spr-mv0", "move", 16,
1560 
    { 0, { { { (1<<MACH_CRISV0), 0 } } } }
1561 
  },
1562 
/* move ${Ps},[${Rd-sfield}${inc}] */
1563 
  {
1564 
    CRIS_INSN_MOVE_SPR_MV3, "move-spr-mv3", "move", 16,
1565 
    { 0, { { { (1<<MACH_CRISV3), 0 } } } }
1566 
  },
1567 
/* move ${Ps},[${Rd-sfield}${inc}] */
1568 
  {
1569 
    CRIS_INSN_MOVE_SPR_MV8, "move-spr-mv8", "move", 16,
1570 
    { 0, { { { (1<<MACH_CRISV8), 0 } } } }
1571 
  },
1572 
/* move ${Ps},[${Rd-sfield}${inc}] */
1573 
  {
1574 
    CRIS_INSN_MOVE_SPR_MV10, "move-spr-mv10", "move", 16,
1575 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1576 
  },
1577 
/* move ${Ps},[${Rd-sfield}${inc}] */
1578 
  {
1579 
    CRIS_INSN_MOVE_SPR_MV32, "move-spr-mv32", "move", 16,
1580 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1581 
  },
1582 
/* sbfs [${Rd-sfield}${inc}] */
1583 
  {
1584 
    CRIS_INSN_SBFS, "sbfs", "sbfs", 16,
1585 
    { 0, { { { (1<<MACH_CRISV10), 0 } } } }
1586 
  },
1587 
/* move ${Ss},${Rd-sfield} */
1588 
  {
1589 
    CRIS_INSN_MOVE_SS_R, "move-ss-r", "move", 16,
1590 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1591 
  },
1592 
/* move ${Rs},${Sd} */
1593 
  {
1594 
    CRIS_INSN_MOVE_R_SS, "move-r-ss", "move", 16,
1595 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1596 
  },
1597 
/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
1598 
  {
1599 
    CRIS_INSN_MOVEM_R_M, "movem-r-m", "movem", 16,
1600 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1601 
  },
1602 
/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
1603 
  {
1604 
    CRIS_INSN_MOVEM_R_M_V32, "movem-r-m-v32", "movem", 16,
1605 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1606 
  },
1607 
/* movem [${Rs}${inc}],${Rd} */
1608 
  {
1609 
    CRIS_INSN_MOVEM_M_R, "movem-m-r", "movem", 16,
1610 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1611 
  },
1612 
/* movem [${Rs}${inc}],${Rd} */
1613 
  {
1614 
    CRIS_INSN_MOVEM_M_PC, "movem-m-pc", "movem", 16,
1615 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1616 
  },
1617 
/* movem [${Rs}${inc}],${Rd} */
1618 
  {
1619 
    CRIS_INSN_MOVEM_M_R_V32, "movem-m-r-v32", "movem", 16,
1620 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1621 
  },
1622 
/* add.b $Rs,$Rd */
1623 
  {
1624 
    CRIS_INSN_ADD_B_R, "add.b-r", "add.b", 16,
1625 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1626 
  },
1627 
/* add.w $Rs,$Rd */
1628 
  {
1629 
    CRIS_INSN_ADD_W_R, "add.w-r", "add.w", 16,
1630 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1631 
  },
1632 
/* add.d $Rs,$Rd */
1633 
  {
1634 
    CRIS_INSN_ADD_D_R, "add.d-r", "add.d", 16,
1635 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1636 
  },
1637 
/* add-m.b [${Rs}${inc}],${Rd} */
1638 
  {
1639 
    CRIS_INSN_ADD_M_B_M, "add-m.b-m", "add-m.b", 16,
1640 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1641 
  },
1642 
/* add-m.w [${Rs}${inc}],${Rd} */
1643 
  {
1644 
    CRIS_INSN_ADD_M_W_M, "add-m.w-m", "add-m.w", 16,
1645 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1646 
  },
1647 
/* add-m.d [${Rs}${inc}],${Rd} */
1648 
  {
1649 
    CRIS_INSN_ADD_M_D_M, "add-m.d-m", "add-m.d", 16,
1650 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1651 
  },
1652 
/* add.b ${sconst8}],${Rd} */
1653 
  {
1654 
    CRIS_INSN_ADDCBR, "addcbr", "add.b", 32,
1655 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1656 
  },
1657 
/* add.w ${sconst16}],${Rd} */
1658 
  {
1659 
    CRIS_INSN_ADDCWR, "addcwr", "add.w", 32,
1660 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1661 
  },
1662 
/* add.d ${const32}],${Rd} */
1663 
  {
1664 
    CRIS_INSN_ADDCDR, "addcdr", "add.d", 48,
1665 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1666 
  },
1667 
/* add.d ${sconst32},PC */
1668 
  {
1669 
    CRIS_INSN_ADDCPC, "addcpc", "add.d", 48,
1670 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1671 
  },
1672 
/* adds.b $Rs,$Rd */
1673 
  {
1674 
    CRIS_INSN_ADDS_B_R, "adds.b-r", "adds.b", 16,
1675 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1676 
  },
1677 
/* adds.w $Rs,$Rd */
1678 
  {
1679 
    CRIS_INSN_ADDS_W_R, "adds.w-r", "adds.w", 16,
1680 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1681 
  },
1682 
/* adds-m.b [${Rs}${inc}],$Rd */
1683 
  {
1684 
    CRIS_INSN_ADDS_M_B_M, "adds-m.b-m", "adds-m.b", 16,
1685 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1686 
  },
1687 
/* adds-m.w [${Rs}${inc}],$Rd */
1688 
  {
1689 
    CRIS_INSN_ADDS_M_W_M, "adds-m.w-m", "adds-m.w", 16,
1690 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1691 
  },
1692 
/* [${Rs}${inc}],$Rd */
1693 
  {
1694 
    CRIS_INSN_ADDSCBR, "addscbr", "[", 32,
1695 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1696 
  },
1697 
/* [${Rs}${inc}],$Rd */
1698 
  {
1699 
    CRIS_INSN_ADDSCWR, "addscwr", "[", 32,
1700 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1701 
  },
1702 
/* adds.w [PC],PC */
1703 
  {
1704 
    CRIS_INSN_ADDSPCPC, "addspcpc", "adds.w", 16,
1705 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1706 
  },
1707 
/* addu.b $Rs,$Rd */
1708 
  {
1709 
    CRIS_INSN_ADDU_B_R, "addu.b-r", "addu.b", 16,
1710 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1711 
  },
1712 
/* addu.w $Rs,$Rd */
1713 
  {
1714 
    CRIS_INSN_ADDU_W_R, "addu.w-r", "addu.w", 16,
1715 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1716 
  },
1717 
/* addu-m.b [${Rs}${inc}],$Rd */
1718 
  {
1719 
    CRIS_INSN_ADDU_M_B_M, "addu-m.b-m", "addu-m.b", 16,
1720 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1721 
  },
1722 
/* addu-m.w [${Rs}${inc}],$Rd */
1723 
  {
1724 
    CRIS_INSN_ADDU_M_W_M, "addu-m.w-m", "addu-m.w", 16,
1725 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1726 
  },
1727 
/* [${Rs}${inc}],$Rd */
1728 
  {
1729 
    CRIS_INSN_ADDUCBR, "adducbr", "[", 32,
1730 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1731 
  },
1732 
/* [${Rs}${inc}],$Rd */
1733 
  {
1734 
    CRIS_INSN_ADDUCWR, "adducwr", "[", 32,
1735 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1736 
  },
1737 
/* sub.b $Rs,$Rd */
1738 
  {
1739 
    CRIS_INSN_SUB_B_R, "sub.b-r", "sub.b", 16,
1740 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1741 
  },
1742 
/* sub.w $Rs,$Rd */
1743 
  {
1744 
    CRIS_INSN_SUB_W_R, "sub.w-r", "sub.w", 16,
1745 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1746 
  },
1747 
/* sub.d $Rs,$Rd */
1748 
  {
1749 
    CRIS_INSN_SUB_D_R, "sub.d-r", "sub.d", 16,
1750 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1751 
  },
1752 
/* sub-m.b [${Rs}${inc}],${Rd} */
1753 
  {
1754 
    CRIS_INSN_SUB_M_B_M, "sub-m.b-m", "sub-m.b", 16,
1755 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1756 
  },
1757 
/* sub-m.w [${Rs}${inc}],${Rd} */
1758 
  {
1759 
    CRIS_INSN_SUB_M_W_M, "sub-m.w-m", "sub-m.w", 16,
1760 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1761 
  },
1762 
/* sub-m.d [${Rs}${inc}],${Rd} */
1763 
  {
1764 
    CRIS_INSN_SUB_M_D_M, "sub-m.d-m", "sub-m.d", 16,
1765 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1766 
  },
1767 
/* sub.b ${sconst8}],${Rd} */
1768 
  {
1769 
    CRIS_INSN_SUBCBR, "subcbr", "sub.b", 32,
1770 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1771 
  },
1772 
/* sub.w ${sconst16}],${Rd} */
1773 
  {
1774 
    CRIS_INSN_SUBCWR, "subcwr", "sub.w", 32,
1775 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1776 
  },
1777 
/* sub.d ${const32}],${Rd} */
1778 
  {
1779 
    CRIS_INSN_SUBCDR, "subcdr", "sub.d", 48,
1780 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1781 
  },
1782 
/* subs.b $Rs,$Rd */
1783 
  {
1784 
    CRIS_INSN_SUBS_B_R, "subs.b-r", "subs.b", 16,
1785 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1786 
  },
1787 
/* subs.w $Rs,$Rd */
1788 
  {
1789 
    CRIS_INSN_SUBS_W_R, "subs.w-r", "subs.w", 16,
1790 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1791 
  },
1792 
/* subs-m.b [${Rs}${inc}],$Rd */
1793 
  {
1794 
    CRIS_INSN_SUBS_M_B_M, "subs-m.b-m", "subs-m.b", 16,
1795 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1796 
  },
1797 
/* subs-m.w [${Rs}${inc}],$Rd */
1798 
  {
1799 
    CRIS_INSN_SUBS_M_W_M, "subs-m.w-m", "subs-m.w", 16,
1800 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1801 
  },
1802 
/* [${Rs}${inc}],$Rd */
1803 
  {
1804 
    CRIS_INSN_SUBSCBR, "subscbr", "[", 32,
1805 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1806 
  },
1807 
/* [${Rs}${inc}],$Rd */
1808 
  {
1809 
    CRIS_INSN_SUBSCWR, "subscwr", "[", 32,
1810 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1811 
  },
1812 
/* subu.b $Rs,$Rd */
1813 
  {
1814 
    CRIS_INSN_SUBU_B_R, "subu.b-r", "subu.b", 16,
1815 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1816 
  },
1817 
/* subu.w $Rs,$Rd */
1818 
  {
1819 
    CRIS_INSN_SUBU_W_R, "subu.w-r", "subu.w", 16,
1820 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1821 
  },
1822 
/* subu-m.b [${Rs}${inc}],$Rd */
1823 
  {
1824 
    CRIS_INSN_SUBU_M_B_M, "subu-m.b-m", "subu-m.b", 16,
1825 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1826 
  },
1827 
/* subu-m.w [${Rs}${inc}],$Rd */
1828 
  {
1829 
    CRIS_INSN_SUBU_M_W_M, "subu-m.w-m", "subu-m.w", 16,
1830 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1831 
  },
1832 
/* [${Rs}${inc}],$Rd */
1833 
  {
1834 
    CRIS_INSN_SUBUCBR, "subucbr", "[", 32,
1835 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1836 
  },
1837 
/* [${Rs}${inc}],$Rd */
1838 
  {
1839 
    CRIS_INSN_SUBUCWR, "subucwr", "[", 32,
1840 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1841 
  },
1842 
/* addc $Rs,$Rd */
1843 
  {
1844 
    CRIS_INSN_ADDC_R, "addc-r", "addc", 16,
1845 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1846 
  },
1847 
/* addc [${Rs}${inc}],${Rd} */
1848 
  {
1849 
    CRIS_INSN_ADDC_M, "addc-m", "addc", 16,
1850 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1851 
  },
1852 
/* addc ${const32},${Rd} */
1853 
  {
1854 
    CRIS_INSN_ADDC_C, "addc-c", "addc", 48,
1855 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1856 
  },
1857 
/* lapc.d ${const32-pcrel},${Rd} */
1858 
  {
1859 
    CRIS_INSN_LAPC_D, "lapc-d", "lapc.d", 48,
1860 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1861 
  },
1862 
/* lapcq ${qo},${Rd} */
1863 
  {
1864 
    CRIS_INSN_LAPCQ, "lapcq", "lapcq", 16,
1865 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1866 
  },
1867 
/* addi.b ${Rs-dfield}.m,${Rd-sfield} */
1868 
  {
1869 
    CRIS_INSN_ADDI_B_R, "addi.b-r", "addi.b", 16,
1870 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1871 
  },
1872 
/* addi.w ${Rs-dfield}.m,${Rd-sfield} */
1873 
  {
1874 
    CRIS_INSN_ADDI_W_R, "addi.w-r", "addi.w", 16,
1875 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1876 
  },
1877 
/* addi.d ${Rs-dfield}.m,${Rd-sfield} */
1878 
  {
1879 
    CRIS_INSN_ADDI_D_R, "addi.d-r", "addi.d", 16,
1880 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1881 
  },
1882 
/* neg.b $Rs,$Rd */
1883 
  {
1884 
    CRIS_INSN_NEG_B_R, "neg.b-r", "neg.b", 16,
1885 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1886 
  },
1887 
/* neg.w $Rs,$Rd */
1888 
  {
1889 
    CRIS_INSN_NEG_W_R, "neg.w-r", "neg.w", 16,
1890 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1891 
  },
1892 
/* neg.d $Rs,$Rd */
1893 
  {
1894 
    CRIS_INSN_NEG_D_R, "neg.d-r", "neg.d", 16,
1895 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1896 
  },
1897 
/* test-m.b [${Rs}${inc}] */
1898 
  {
1899 
    CRIS_INSN_TEST_M_B_M, "test-m.b-m", "test-m.b", 16,
1900 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1901 
  },
1902 
/* test-m.w [${Rs}${inc}] */
1903 
  {
1904 
    CRIS_INSN_TEST_M_W_M, "test-m.w-m", "test-m.w", 16,
1905 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1906 
  },
1907 
/* test-m.d [${Rs}${inc}] */
1908 
  {
1909 
    CRIS_INSN_TEST_M_D_M, "test-m.d-m", "test-m.d", 16,
1910 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1911 
  },
1912 
/* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
1913 
  {
1914 
    CRIS_INSN_MOVE_R_M_B_M, "move-r-m.b-m", "move-r-m.b", 16,
1915 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1916 
  },
1917 
/* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
1918 
  {
1919 
    CRIS_INSN_MOVE_R_M_W_M, "move-r-m.w-m", "move-r-m.w", 16,
1920 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1921 
  },
1922 
/* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
1923 
  {
1924 
    CRIS_INSN_MOVE_R_M_D_M, "move-r-m.d-m", "move-r-m.d", 16,
1925 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1926 
  },
1927 
/* muls.b $Rs,$Rd */
1928 
  {
1929 
    CRIS_INSN_MULS_B, "muls.b", "muls.b", 16,
1930 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1931 
  },
1932 
/* muls.w $Rs,$Rd */
1933 
  {
1934 
    CRIS_INSN_MULS_W, "muls.w", "muls.w", 16,
1935 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1936 
  },
1937 
/* muls.d $Rs,$Rd */
1938 
  {
1939 
    CRIS_INSN_MULS_D, "muls.d", "muls.d", 16,
1940 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1941 
  },
1942 
/* mulu.b $Rs,$Rd */
1943 
  {
1944 
    CRIS_INSN_MULU_B, "mulu.b", "mulu.b", 16,
1945 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1946 
  },
1947 
/* mulu.w $Rs,$Rd */
1948 
  {
1949 
    CRIS_INSN_MULU_W, "mulu.w", "mulu.w", 16,
1950 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1951 
  },
1952 
/* mulu.d $Rs,$Rd */
1953 
  {
1954 
    CRIS_INSN_MULU_D, "mulu.d", "mulu.d", 16,
1955 
    { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
1956 
  },
1957 
/* mcp $Ps,$Rd */
1958 
  {
1959 
    CRIS_INSN_MCP, "mcp", "mcp", 16,
1960 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
1961 
  },
1962 
/* mstep $Rs,$Rd */
1963 
  {
1964 
    CRIS_INSN_MSTEP, "mstep", "mstep", 16,
1965 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
1966 
  },
1967 
/* dstep $Rs,$Rd */
1968 
  {
1969 
    CRIS_INSN_DSTEP, "dstep", "dstep", 16,
1970 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1971 
  },
1972 
/* abs $Rs,$Rd */
1973 
  {
1974 
    CRIS_INSN_ABS, "abs", "abs", 16,
1975 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1976 
  },
1977 
/* and.b $Rs,$Rd */
1978 
  {
1979 
    CRIS_INSN_AND_B_R, "and.b-r", "and.b", 16,
1980 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1981 
  },
1982 
/* and.w $Rs,$Rd */
1983 
  {
1984 
    CRIS_INSN_AND_W_R, "and.w-r", "and.w", 16,
1985 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1986 
  },
1987 
/* and.d $Rs,$Rd */
1988 
  {
1989 
    CRIS_INSN_AND_D_R, "and.d-r", "and.d", 16,
1990 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1991 
  },
1992 
/* and-m.b [${Rs}${inc}],${Rd} */
1993 
  {
1994 
    CRIS_INSN_AND_M_B_M, "and-m.b-m", "and-m.b", 16,
1995 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1996 
  },
1997 
/* and-m.w [${Rs}${inc}],${Rd} */
1998 
  {
1999 
    CRIS_INSN_AND_M_W_M, "and-m.w-m", "and-m.w", 16,
2000 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2001 
  },
2002 
/* and-m.d [${Rs}${inc}],${Rd} */
2003 
  {
2004 
    CRIS_INSN_AND_M_D_M, "and-m.d-m", "and-m.d", 16,
2005 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2006 
  },
2007 
/* and.b ${sconst8}],${Rd} */
2008 
  {
2009 
    CRIS_INSN_ANDCBR, "andcbr", "and.b", 32,
2010 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2011 
  },
2012 
/* and.w ${sconst16}],${Rd} */
2013 
  {
2014 
    CRIS_INSN_ANDCWR, "andcwr", "and.w", 32,
2015 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2016 
  },
2017 
/* and.d ${const32}],${Rd} */
2018 
  {
2019 
    CRIS_INSN_ANDCDR, "andcdr", "and.d", 48,
2020 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2021 
  },
2022 
/* andq $i,$Rd */
2023 
  {
2024 
    CRIS_INSN_ANDQ, "andq", "andq", 16,
2025 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2026 
  },
2027 
/* orr.b $Rs,$Rd */
2028 
  {
2029 
    CRIS_INSN_ORR_B_R, "orr.b-r", "orr.b", 16,
2030 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2031 
  },
2032 
/* orr.w $Rs,$Rd */
2033 
  {
2034 
    CRIS_INSN_ORR_W_R, "orr.w-r", "orr.w", 16,
2035 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2036 
  },
2037 
/* orr.d $Rs,$Rd */
2038 
  {
2039 
    CRIS_INSN_ORR_D_R, "orr.d-r", "orr.d", 16,
2040 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2041 
  },
2042 
/* or-m.b [${Rs}${inc}],${Rd} */
2043 
  {
2044 
    CRIS_INSN_OR_M_B_M, "or-m.b-m", "or-m.b", 16,
2045 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2046 
  },
2047 
/* or-m.w [${Rs}${inc}],${Rd} */
2048 
  {
2049 
    CRIS_INSN_OR_M_W_M, "or-m.w-m", "or-m.w", 16,
2050 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2051 
  },
2052 
/* or-m.d [${Rs}${inc}],${Rd} */
2053 
  {
2054 
    CRIS_INSN_OR_M_D_M, "or-m.d-m", "or-m.d", 16,
2055 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2056 
  },
2057 
/* or.b ${sconst8}],${Rd} */
2058 
  {
2059 
    CRIS_INSN_ORCBR, "orcbr", "or.b", 32,
2060 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2061 
  },
2062 
/* or.w ${sconst16}],${Rd} */
2063 
  {
2064 
    CRIS_INSN_ORCWR, "orcwr", "or.w", 32,
2065 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2066 
  },
2067 
/* or.d ${const32}],${Rd} */
2068 
  {
2069 
    CRIS_INSN_ORCDR, "orcdr", "or.d", 48,
2070 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2071 
  },
2072 
/* orq $i,$Rd */
2073 
  {
2074 
    CRIS_INSN_ORQ, "orq", "orq", 16,
2075 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2076 
  },
2077 
/* xor $Rs,$Rd */
2078 
  {
2079 
    CRIS_INSN_XOR, "xor", "xor", 16,
2080 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2081 
  },
2082 
/* not ${Rs} */
2083 
  {
2084 
    CRIS_INSN_NOT, "not", "not", 16,
2085 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3), 0 } } } }
2086 
  },
2087 
/* swap${swapoption} ${Rs} */
2088 
  {
2089 
    CRIS_INSN_SWAP, "swap", "swap", 16,
2090 
    { 0, { { { (1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
2091 
  },
2092 
/* asrr.b $Rs,$Rd */
2093 
  {
2094 
    CRIS_INSN_ASRR_B_R, "asrr.b-r", "asrr.b", 16,
2095 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2096 
  },
2097 
/* asrr.w $Rs,$Rd */
2098 
  {
2099 
    CRIS_INSN_ASRR_W_R, "asrr.w-r", "asrr.w", 16,
2100 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2101 
  },
2102 
/* asrr.d $Rs,$Rd */
2103 
  {
2104 
    CRIS_INSN_ASRR_D_R, "asrr.d-r", "asrr.d", 16,
2105 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2106 
  },
2107 
/* asrq $c,${Rd} */
2108 
  {
2109 
    CRIS_INSN_ASRQ, "asrq", "asrq", 16,
2110 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2111 
  },
2112 
/* lsrr.b $Rs,$Rd */
2113 
  {
2114 
    CRIS_INSN_LSRR_B_R, "lsrr.b-r", "lsrr.b", 16,
2115 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2116 
  },
2117 
/* lsrr.w $Rs,$Rd */
2118 
  {
2119 
    CRIS_INSN_LSRR_W_R, "lsrr.w-r", "lsrr.w", 16,
2120 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2121 
  },
2122 
/* lsrr.d $Rs,$Rd */
2123 
  {
2124 
    CRIS_INSN_LSRR_D_R, "lsrr.d-r", "lsrr.d", 16,
2125 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2126 
  },
2127 
/* lsrq $c,${Rd} */
2128 
  {
2129 
    CRIS_INSN_LSRQ, "lsrq", "lsrq", 16,
2130 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2131 
  },
2132 
/* lslr.b $Rs,$Rd */
2133 
  {
2134 
    CRIS_INSN_LSLR_B_R, "lslr.b-r", "lslr.b", 16,
2135 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2136 
  },
2137 
/* lslr.w $Rs,$Rd */
2138 
  {
2139 
    CRIS_INSN_LSLR_W_R, "lslr.w-r", "lslr.w", 16,
2140 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2141 
  },
2142 
/* lslr.d $Rs,$Rd */
2143 
  {
2144 
    CRIS_INSN_LSLR_D_R, "lslr.d-r", "lslr.d", 16,
2145 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2146 
  },
2147 
/* lslq $c,${Rd} */
2148 
  {
2149 
    CRIS_INSN_LSLQ, "lslq", "lslq", 16,
2150 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2151 
  },
2152 
/* $Rs,$Rd */
2153 
  {
2154 
    CRIS_INSN_BTST, "btst", "", 16,
2155 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2156 
  },
2157 
/* btstq $c,${Rd} */
2158 
  {
2159 
    CRIS_INSN_BTSTQ, "btstq", "btstq", 16,
2160 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2161 
  },
2162 
/* setf ${list-of-flags} */
2163 
  {
2164 
    CRIS_INSN_SETF, "setf", "setf", 16,
2165 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2166 
  },
2167 
/* clearf ${list-of-flags} */
2168 
  {
2169 
    CRIS_INSN_CLEARF, "clearf", "clearf", 16,
2170 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2171 
  },
2172 
/* rfe */
2173 
  {
2174 
    CRIS_INSN_RFE, "rfe", "rfe", 16,
2175 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2176 
  },
2177 
/* sfe */
2178 
  {
2179 
    CRIS_INSN_SFE, "sfe", "sfe", 16,
2180 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2181 
  },
2182 
/* rfg */
2183 
  {
2184 
    CRIS_INSN_RFG, "rfg", "rfg", 16,
2185 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2186 
  },
2187 
/* rfn */
2188 
  {
2189 
    CRIS_INSN_RFN, "rfn", "rfn", 16,
2190 
    { 0, { { { (1<<MACH_CRISV32), 0 } } } }
2191 
  },
2192 
/* halt */
2193 
  {
2194 
    CRIS_INSN_HALT, "halt", "halt", 16,
2195 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2196 
  },
2197 
/* b${cc} ${o-pcrel} */
2198 
  {
2199 
    CRIS_INSN_BCC_B, "bcc-b", "b", 16,
2200 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2201 
  },
2202 
/* ba ${o-pcrel} */
2203 
  {
2204 
    CRIS_INSN_BA_B, "ba-b", "ba", 16,
2205 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2206 
  },
2207 
/* b${cc} ${o-word-pcrel} */
2208 
  {
2209 
    CRIS_INSN_BCC_W, "bcc-w", "b", 32,
2210 
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2211 
  },
2212 
/* ba ${o-word-pcrel} */
2213 
  {
2214 
    CRIS_INSN_BA_W, "ba-w", "ba", 32,
2215 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
2216 
  },
2217 
/* jas ${Rs},${Pd} */
2218 
  {
2219 
    CRIS_INSN_JAS_R, "jas-r", "jas", 16,
2220 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2221 
  },
2222 
/* jump/jsr/jir ${Rs} */
2223 
  {
2224 
    CRIS_INSN_JUMP_R, "jump-r", "jump/jsr/jir", 16,
2225 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2226 
  },
2227 
/* jas ${const32},${Pd} */
2228 
  {
2229 
    CRIS_INSN_JAS_C, "jas-c", "jas", 48,
2230 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2231 
  },
2232 
/* jump/jsr/jir [${Rs}${inc}] */
2233 
  {
2234 
    CRIS_INSN_JUMP_M, "jump-m", "jump/jsr/jir", 16,
2235 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2236 
  },
2237 
/* jump/jsr/jir ${const32} */
2238 
  {
2239 
    CRIS_INSN_JUMP_C, "jump-c", "jump/jsr/jir", 48,
2240 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2241 
  },
2242 
/* jump ${Ps} */
2243 
  {
2244 
    CRIS_INSN_JUMP_P, "jump-p", "jump", 16,
2245 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2246 
  },
2247 
/* bas ${const32},${Pd} */
2248 
  {
2249 
    CRIS_INSN_BAS_C, "bas-c", "bas", 48,
2250 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2251 
  },
2252 
/* jasc ${Rs},${Pd} */
2253 
  {
2254 
    CRIS_INSN_JASC_R, "jasc-r", "jasc", 16,
2255 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2256 
  },
2257 
/* jasc ${const32},${Pd} */
2258 
  {
2259 
    CRIS_INSN_JASC_C, "jasc-c", "jasc", 48,
2260 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2261 
  },
2262 
/* basc ${const32},${Pd} */
2263 
  {
2264 
    CRIS_INSN_BASC_C, "basc-c", "basc", 48,
2265 
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } }
2266 
  },
2267 
/* break $n */
2268 
  {
2269 
    CRIS_INSN_BREAK, "break", "break", 16,
2270 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
2271 
  },
2272 
/* bound-r.b ${Rs},${Rd} */
2273 
  {
2274 
    CRIS_INSN_BOUND_R_B_R, "bound-r.b-r", "bound-r.b", 16,
2275 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2276 
  },
2277 
/* bound-r.w ${Rs},${Rd} */
2278 
  {
2279 
    CRIS_INSN_BOUND_R_W_R, "bound-r.w-r", "bound-r.w", 16,
2280 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2281 
  },
2282 
/* bound-r.d ${Rs},${Rd} */
2283 
  {
2284 
    CRIS_INSN_BOUND_R_D_R, "bound-r.d-r", "bound-r.d", 16,
2285 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2286 
  },
2287 
/* bound-m.b [${Rs}${inc}],${Rd} */
2288 
  {
2289 
    CRIS_INSN_BOUND_M_B_M, "bound-m.b-m", "bound-m.b", 16,
2290 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2291 
  },
2292 
/* bound-m.w [${Rs}${inc}],${Rd} */
2293 
  {
2294 
    CRIS_INSN_BOUND_M_W_M, "bound-m.w-m", "bound-m.w", 16,
2295 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2296 
  },
2297 
/* bound-m.d [${Rs}${inc}],${Rd} */
2298 
  {
2299 
    CRIS_INSN_BOUND_M_D_M, "bound-m.d-m", "bound-m.d", 16,
2300 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2301 
  },
2302 
/* bound.b [PC+],${Rd} */
2303 
  {
2304 
    CRIS_INSN_BOUND_CB, "bound-cb", "bound.b", 32,
2305 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2306 
  },
2307 
/* bound.w [PC+],${Rd} */
2308 
  {
2309 
    CRIS_INSN_BOUND_CW, "bound-cw", "bound.w", 32,
2310 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2311 
  },
2312 
/* bound.d [PC+],${Rd} */
2313 
  {
2314 
    CRIS_INSN_BOUND_CD, "bound-cd", "bound.d", 48,
2315 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2316 
  },
2317 
/* s${cc} ${Rd-sfield} */
2318 
  {
2319 
    CRIS_INSN_SCC, "scc", "s", 16,
2320 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2321 
  },
2322 
/* lz ${Rs},${Rd} */
2323 
  {
2324 
    CRIS_INSN_LZ, "lz", "lz", 16,
2325 
    { 0, { { { (1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } }
2326 
  },
2327 
/* addoq $o,$Rs,ACR */
2328 
  {
2329 
    CRIS_INSN_ADDOQ, "addoq", "addoq", 16,
2330 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2331 
  },
2332 
/* bdapq $o,PC */
2333 
  {
2334 
    CRIS_INSN_BDAPQPC, "bdapqpc", "bdapq", 16,
2335 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2336 
  },
2337 
/* bdap ${sconst32},PC */
2338 
  {
2339 
    CRIS_INSN_BDAP_32_PC, "bdap-32-pc", "bdap", 48,
2340 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2341 
  },
2342 
/* move [PC+],P0 */
2343 
  {
2344 
    CRIS_INSN_MOVE_M_PCPLUS_P0, "move-m-pcplus-p0", "move", 16,
2345 
    { 0|A(COND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2346 
  },
2347 
/* move [SP+],P8 */
2348 
  {
2349 
    CRIS_INSN_MOVE_M_SPPLUS_P8, "move-m-spplus-p8", "move", 16,
2350 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2351 
  },
2352 
/* addo-m.b [${Rs}${inc}],$Rd,ACR */
2353 
  {
2354 
    CRIS_INSN_ADDO_M_B_M, "addo-m.b-m", "addo-m.b", 16,
2355 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2356 
  },
2357 
/* addo-m.w [${Rs}${inc}],$Rd,ACR */
2358 
  {
2359 
    CRIS_INSN_ADDO_M_W_M, "addo-m.w-m", "addo-m.w", 16,
2360 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2361 
  },
2362 
/* addo-m.d [${Rs}${inc}],$Rd,ACR */
2363 
  {
2364 
    CRIS_INSN_ADDO_M_D_M, "addo-m.d-m", "addo-m.d", 16,
2365 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2366 
  },
2367 
/* addo.b [PC+],$Rd,ACR */
2368 
  {
2369 
    CRIS_INSN_ADDO_CB, "addo-cb", "addo.b", 32,
2370 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2371 
  },
2372 
/* addo.w [PC+],$Rd,ACR */
2373 
  {
2374 
    CRIS_INSN_ADDO_CW, "addo-cw", "addo.w", 32,
2375 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2376 
  },
2377 
/* addo.d [PC+],$Rd,ACR */
2378 
  {
2379 
    CRIS_INSN_ADDO_CD, "addo-cd", "addo.d", 48,
2380 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2381 
  },
2382 
/* dip [${Rs}${inc}] */
2383 
  {
2384 
    CRIS_INSN_DIP_M, "dip-m", "dip", 16,
2385 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2386 
  },
2387 
/* dip [PC+] */
2388 
  {
2389 
    CRIS_INSN_DIP_C, "dip-c", "dip", 48,
2390 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2391 
  },
2392 
/* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
2393 
  {
2394 
    CRIS_INSN_ADDI_ACR_B_R, "addi-acr.b-r", "addi-acr.b", 16,
2395 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2396 
  },
2397 
/* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
2398 
  {
2399 
    CRIS_INSN_ADDI_ACR_W_R, "addi-acr.w-r", "addi-acr.w", 16,
2400 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2401 
  },
2402 
/* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
2403 
  {
2404 
    CRIS_INSN_ADDI_ACR_D_R, "addi-acr.d-r", "addi-acr.d", 16,
2405 
    { 0, { { { (1<<MACH_BASE), 0 } } } }
2406 
  },
2407 
/* biap-pc.b ${Rs-dfield}.m,PC */
2408 
  {
2409 
    CRIS_INSN_BIAP_PC_B_R, "biap-pc.b-r", "biap-pc.b", 16,
2410 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2411 
  },
2412 
/* biap-pc.w ${Rs-dfield}.m,PC */
2413 
  {
2414 
    CRIS_INSN_BIAP_PC_W_R, "biap-pc.w-r", "biap-pc.w", 16,
2415 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2416 
  },
2417 
/* biap-pc.d ${Rs-dfield}.m,PC */
2418 
  {
2419 
    CRIS_INSN_BIAP_PC_D_R, "biap-pc.d-r", "biap-pc.d", 16,
2420 
    { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } }
2421 
  },
2422 
/* fidxi [$Rs] */
2423 
  {
2424 
    CRIS_INSN_FIDXI, "fidxi", "fidxi", 16,
2425 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2426 
  },
2427 
/* fidxi [$Rs] */
2428 
  {
2429 
    CRIS_INSN_FTAGI, "ftagi", "fidxi", 16,
2430 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2431 
  },
2432 
/* fidxd [$Rs] */
2433 
  {
2434 
    CRIS_INSN_FIDXD, "fidxd", "fidxd", 16,
2435 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2436 
  },
2437 
/* ftagd [$Rs] */
2438 
  {
2439 
    CRIS_INSN_FTAGD, "ftagd", "ftagd", 16,
2440 
    { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } }
2441 
  },
2442 
};
2443 
 
2444 
#undef OP
2445 
#undef A
2446 
 
2447 
/* Initialize anything needed to be done once, before any cpu_open call.  */
2448 
 
2449 
static void
2450 
init_tables (void)
2451 
{
2452 
}
2453 
 
2454 
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
2455 
static void build_hw_table      (CGEN_CPU_TABLE *);
2456 
static void build_ifield_table  (CGEN_CPU_TABLE *);
2457 
static void build_operand_table (CGEN_CPU_TABLE *);
2458 
static void build_insn_table    (CGEN_CPU_TABLE *);
2459 
static void cris_cgen_rebuild_tables (CGEN_CPU_TABLE *);
2460 
 
2461 
/* Subroutine of cris_cgen_cpu_open to look up a mach via its bfd name.  */
2462 
 
2463 
static const CGEN_MACH *
2464 
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
2465 
{
2466 
  while (table->name)
2467 
    {
2468 
      if (strcmp (name, table->bfd_name) == 0)
2469 
        return table;
2470 
      ++table;
2471 
    }
2472 
  abort ();
2473 
}
2474 
 
2475 
/* Subroutine of cris_cgen_cpu_open to build the hardware table.  */
2476 
 
2477 
static void
2478 
build_hw_table (CGEN_CPU_TABLE *cd)
2479 
{
2480 
  int i;
2481 
  int machs = cd->machs;
2482 
  const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0];
2483 
  /* MAX_HW is only an upper bound on the number of selected entries.
2484 
     However each entry is indexed by it's enum so there can be holes in
2485 
     the table.  */
2486 
  const CGEN_HW_ENTRY **selected =
2487 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
2488 
 
2489 
  cd->hw_table.init_entries = init;
2490 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
2491 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
2492 
  /* ??? For now we just use machs to determine which ones we want.  */
2493 
  for (i = 0; init[i].name != NULL; ++i)
2494 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
2495 
        & machs)
2496 
      selected[init[i].type] = &init[i];
2497 
  cd->hw_table.entries = selected;
2498 
  cd->hw_table.num_entries = MAX_HW;
2499 
}
2500 
 
2501 
/* Subroutine of cris_cgen_cpu_open to build the hardware table.  */
2502 
 
2503 
static void
2504 
build_ifield_table (CGEN_CPU_TABLE *cd)
2505 
{
2506 
  cd->ifld_table = & cris_cgen_ifld_table[0];
2507 
}
2508 
 
2509 
/* Subroutine of cris_cgen_cpu_open to build the hardware table.  */
2510 
 
2511 
static void
2512 
build_operand_table (CGEN_CPU_TABLE *cd)
2513 
{
2514 
  int i;
2515 
  int machs = cd->machs;
2516 
  const CGEN_OPERAND *init = & cris_cgen_operand_table[0];
2517 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2518 
     However each entry is indexed by it's enum so there can be holes in
2519 
     the table.  */
2520 
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2521 
 
2522 
  cd->operand_table.init_entries = init;
2523 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2524 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2525 
  /* ??? For now we just use mach to determine which ones we want.  */
2526 
  for (i = 0; init[i].name != NULL; ++i)
2527 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2528 
        & machs)
2529 
      selected[init[i].type] = &init[i];
2530 
  cd->operand_table.entries = selected;
2531 
  cd->operand_table.num_entries = MAX_OPERANDS;
2532 
}
2533 
 
2534 
/* Subroutine of cris_cgen_cpu_open to build the hardware table.
2535 
   ??? This could leave out insns not supported by the specified mach/isa,
2536 
   but that would cause errors like "foo only supported by bar" to become
2537 
   "unknown insn", so for now we include all insns and require the app to
2538 
   do the checking later.
2539 
   ??? On the other hand, parsing of such insns may require their hardware or
2540 
   operand elements to be in the table [which they mightn't be].  */
2541 
 
2542 
static void
2543 
build_insn_table (CGEN_CPU_TABLE *cd)
2544 
{
2545 
  int i;
2546 
  const CGEN_IBASE *ib = & cris_cgen_insn_table[0];
2547 
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2548 
 
2549 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2550 
  for (i = 0; i < MAX_INSNS; ++i)
2551 
    insns[i].base = &ib[i];
2552 
  cd->insn_table.init_entries = insns;
2553 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2554 
  cd->insn_table.num_init_entries = MAX_INSNS;
2555 
}
2556 
 
2557 
/* Subroutine of cris_cgen_cpu_open to rebuild the tables.  */
2558 
 
2559 
static void
2560 
cris_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2561 
{
2562 
  int i;
2563 
  CGEN_BITSET *isas = cd->isas;
2564 
  unsigned int machs = cd->machs;
2565 
 
2566 
  cd->int_insn_p = CGEN_INT_INSN_P;
2567 
 
2568 
  /* Data derived from the isa spec.  */
2569 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
2570 
  cd->default_insn_bitsize = UNSET;
2571 
  cd->base_insn_bitsize = UNSET;
2572 
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
2573 
  cd->max_insn_bitsize = 0;
2574 
  for (i = 0; i < MAX_ISAS; ++i)
2575 
    if (cgen_bitset_contains (isas, i))
2576 
      {
2577 
        const CGEN_ISA *isa = & cris_cgen_isa_table[i];
2578 
 
2579 
        /* Default insn sizes of all selected isas must be
2580 
           equal or we set the result to 0, meaning "unknown".  */
2581 
        if (cd->default_insn_bitsize == UNSET)
2582 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
2583 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2584 
          ; /* This is ok.  */
2585 
        else
2586 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2587 
 
2588 
        /* Base insn sizes of all selected isas must be equal
2589 
           or we set the result to 0, meaning "unknown".  */
2590 
        if (cd->base_insn_bitsize == UNSET)
2591 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
2592 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2593 
          ; /* This is ok.  */
2594 
        else
2595 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2596 
 
2597 
        /* Set min,max insn sizes.  */
2598 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2599 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
2600 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2601 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
2602 
      }
2603 
 
2604 
  /* Data derived from the mach spec.  */
2605 
  for (i = 0; i < MAX_MACHS; ++i)
2606 
    if (((1 << i) & machs) != 0)
2607 
      {
2608 
        const CGEN_MACH *mach = & cris_cgen_mach_table[i];
2609 
 
2610 
        if (mach->insn_chunk_bitsize != 0)
2611 
        {
2612 
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2613 
            {
2614 
              fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2615 
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2616 
              abort ();
2617 
            }
2618 
 
2619 
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2620 
        }
2621 
      }
2622 
 
2623 
  /* Determine which hw elements are used by MACH.  */
2624 
  build_hw_table (cd);
2625 
 
2626 
  /* Build the ifield table.  */
2627 
  build_ifield_table (cd);
2628 
 
2629 
  /* Determine which operands are used by MACH/ISA.  */
2630 
  build_operand_table (cd);
2631 
 
2632 
  /* Build the instruction table.  */
2633 
  build_insn_table (cd);
2634 
}
2635 
 
2636 
/* Initialize a cpu table and return a descriptor.
2637 
   It's much like opening a file, and must be the first function called.
2638 
   The arguments are a set of (type/value) pairs, terminated with
2639 
   CGEN_CPU_OPEN_END.
2640 
 
2641 
   Currently supported values:
2642 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
2643 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
2644 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2645 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
2646 
   CGEN_CPU_OPEN_END:     terminates arguments
2647 
 
2648 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2649 
   precluded.  */
2650 
 
2651 
CGEN_CPU_DESC
2652 
cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2653 
{
2654 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2655 
  static int init_p;
2656 
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
2657 
  unsigned int machs = 0; /* 0 = "unspecified" */
2658 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2659 
  va_list ap;
2660 
 
2661 
  if (! init_p)
2662 
    {
2663 
      init_tables ();
2664 
      init_p = 1;
2665 
    }
2666 
 
2667 
  memset (cd, 0, sizeof (*cd));
2668 
 
2669 
  va_start (ap, arg_type);
2670 
  while (arg_type != CGEN_CPU_OPEN_END)
2671 
    {
2672 
      switch (arg_type)
2673 
        {
2674 
        case CGEN_CPU_OPEN_ISAS :
2675 
          isas = va_arg (ap, CGEN_BITSET *);
2676 
          break;
2677 
        case CGEN_CPU_OPEN_MACHS :
2678 
          machs = va_arg (ap, unsigned int);
2679 
          break;
2680 
        case CGEN_CPU_OPEN_BFDMACH :
2681 
          {
2682 
            const char *name = va_arg (ap, const char *);
2683 
            const CGEN_MACH *mach =
2684 
              lookup_mach_via_bfd_name (cris_cgen_mach_table, name);
2685 
 
2686 
            machs |= 1 << mach->num;
2687 
            break;
2688 
          }
2689 
        case CGEN_CPU_OPEN_ENDIAN :
2690 
          endian = va_arg (ap, enum cgen_endian);
2691 
          break;
2692 
        default :
2693 
          fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n",
2694 
                   arg_type);
2695 
          abort (); /* ??? return NULL? */
2696 
        }
2697 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2698 
    }
2699 
  va_end (ap);
2700 
 
2701 
  /* Mach unspecified means "all".  */
2702 
  if (machs == 0)
2703 
    machs = (1 << MAX_MACHS) - 1;
2704 
  /* Base mach is always selected.  */
2705 
  machs |= 1;
2706 
  if (endian == CGEN_ENDIAN_UNKNOWN)
2707 
    {
2708 
      /* ??? If target has only one, could have a default.  */
2709 
      fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n");
2710 
      abort ();
2711 
    }
2712 
 
2713 
  cd->isas = cgen_bitset_copy (isas);
2714 
  cd->machs = machs;
2715 
  cd->endian = endian;
2716 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
2717 
     The worry here is where both data and insn endian can be independently
2718 
     chosen, in which case this function will need another argument.
2719 
     Actually, will want to allow for more arguments in the future anyway.  */
2720 
  cd->insn_endian = endian;
2721 
 
2722 
  /* Table (re)builder.  */
2723 
  cd->rebuild_tables = cris_cgen_rebuild_tables;
2724 
  cris_cgen_rebuild_tables (cd);
2725 
 
2726 
  /* Default to not allowing signed overflow.  */
2727 
  cd->signed_overflow_ok_p = 0;
2728 
 
2729 
  return (CGEN_CPU_DESC) cd;
2730 
}
2731 
 
2732 
/* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2733 
   MACH_NAME is the bfd name of the mach.  */
2734 
 
2735 
CGEN_CPU_DESC
2736 
cris_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2737 
{
2738 
  return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2739 
                               CGEN_CPU_OPEN_ENDIAN, endian,
2740 
                               CGEN_CPU_OPEN_END);
2741 
}
2742 
 
2743 
/* Close a cpu table.
2744 
   ??? This can live in a machine independent file, but there's currently
2745 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
2746 
   place as some simulator ports use this but they don't use libopcodes.  */
2747 
 
2748 
void
2749 
cris_cgen_cpu_close (CGEN_CPU_DESC cd)
2750 
{
2751 
  unsigned int i;
2752 
  const CGEN_INSN *insns;
2753 
 
2754 
  if (cd->macro_insn_table.init_entries)
2755 
    {
2756 
      insns = cd->macro_insn_table.init_entries;
2757 
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2758 
        if (CGEN_INSN_RX ((insns)))
2759 
          regfree (CGEN_INSN_RX (insns));
2760 
    }
2761 
 
2762 
  if (cd->insn_table.init_entries)
2763 
    {
2764 
      insns = cd->insn_table.init_entries;
2765 
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2766 
        if (CGEN_INSN_RX (insns))
2767 
          regfree (CGEN_INSN_RX (insns));
2768 
    }
2769 
 
2770 
  if (cd->macro_insn_table.init_entries)
2771 
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2772 
 
2773 
  if (cd->insn_table.init_entries)
2774 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
2775 
 
2776 
  if (cd->hw_table.entries)
2777 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2778 
 
2779 
  if (cd->operand_table.entries)
2780 
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2781 
 
2782 
  free (cd);
2783 
}
2784 
 

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