OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [mn10300/] [tconfig.in] - Blame information for rev 381

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/* mn10300 target configuration file.  */
2
 
3
/* FIXME: This is unnecessarily necessary: */
4
#include "ansidecl.h"
5
#include "gdb/callback.h"
6
#include "gdb/remote-sim.h"
7
#include "sim-module.h"
8
 
9
MODULE_INSTALL_FN dv_sockser_install;
10
#define MODULE_LIST dv_sockser_install,
11
 
12
/* Define this if the simulator supports profiling.
13
   See the mips simulator for an example.
14
   This enables the `-p foo' and `-s bar' options.
15
   The target is required to provide sim_set_profile{,_size}.  */
16
/* #define SIM_HAVE_PROFILE */
17
 
18
/* Define this if the simulator uses an instruction cache.
19
   See the h8/300 simulator for an example.
20
   This enables the `-c size' option to set the size of the cache.
21
   The target is required to provide sim_set_simcache_size.  */
22
/* #define SIM_HAVE_SIMCACHE */
23
 
24
/* Define this if the target cpu is bi-endian
25
   and the simulator supports it.  */
26
/* #define SIM_HAVE_BIENDIAN */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.