URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 794

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_xcv_ram32x8d.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
//
// Revision 1.2  2002/07/14 22:17:17  lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
module or1200_xcv_ram32x8d
(
    DPO,
    SPO,
    A,
    D,
    DPRA,
    WCLK,
    WE
);
output  [7:0]   DPO;
output  [7:0]   SPO;
input   [4:0]   A;
input   [4:0]   DPRA;
input   [7:0]   D;
input           WCLK;
input           WE;
 
wire    [7:0]   DPO_0;
wire    [7:0]   SPO_0;
 
wire    [7:0]   DPO_1;
wire    [7:0]   SPO_1;
 
wire            WE_0 ;
wire            WE_1 ;
 
assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
assign SPO = A[4] ? SPO_1 : SPO_0 ;
 
assign WE_0 = !A[4] && WE ;
assign WE_1 =  A[4] && WE ;
 
RAM16X1D ram32x1d_0_0(
        .DPO(DPO_0[0]),
        .SPO(SPO_0[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_0_1(
        .DPO(DPO_0[1]),
        .SPO(SPO_0[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_0_2(
        .DPO(DPO_0[2]),
        .SPO(SPO_0[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_0_3(
        .DPO(DPO_0[3]),
        .SPO(SPO_0[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_0_4(
        .DPO(DPO_0[4]),
        .SPO(SPO_0[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_0_5(
        .DPO(DPO_0[5]),
        .SPO(SPO_0[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_0_6(
        .DPO(DPO_0[6]),
        .SPO(SPO_0[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_0_7(
        .DPO(DPO_0[7]),
        .SPO(SPO_0[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_0)
);
 
RAM16X1D ram32x1d_1_0(
        .DPO(DPO_1[0]),
        .SPO(SPO_1[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_1_1(
        .DPO(DPO_1[1]),
        .SPO(SPO_1[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_1_2(
        .DPO(DPO_1[2]),
        .SPO(SPO_1[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_1_3(
        .DPO(DPO_1[3]),
        .SPO(SPO_1[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_1_4(
        .DPO(DPO_1[4]),
        .SPO(SPO_1[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_1_5(
        .DPO(DPO_1[5]),
        .SPO(SPO_1[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_1_6(
        .DPO(DPO_1[6]),
        .SPO(SPO_1[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_1_7(
        .DPO(DPO_1[7]),
        .SPO(SPO_1[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .WCLK(WCLK),
        .WE(WE_1)
);
endmodule
 
`else
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
`endif
`endif

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Blame information for rev 794

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	142	marcus.erl	`// $Log: or1200_xcv_ram32x8d.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// No update`
49			`//`
50			`// Revision 1.2 2002/07/14 22:17:17 lampret`
51			`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
52			`//`
53	10	unneback	`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/21 17:57:16 lampret`
57			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
58			`//`
59			`// Revision 1.6 2001/10/14 13:12:10 lampret`
60			`// MP3 version.`
61			`//`
62			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
63			`// no message`
64			`//`
65			`// Revision 1.1 2001/08/09 13:39:33 lampret`
66			`// Major clean-up.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`ifdef OR1200_XILINX_RAM32X1D
76			`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
77			`module or1200_xcv_ram32x8d`
78			`(`
79			`DPO,`
80			`SPO,`
81			`A,`
82			`D,`
83			`DPRA,`
84			`WCLK,`
85			`WE`
86			`);`
87			`output [7:0] DPO;`
88			`output [7:0] SPO;`
89			`input [4:0] A;`
90			`input [4:0] DPRA;`
91			`input [7:0] D;`
92			`input WCLK;`
93			`input WE;`
94
95			`wire [7:0] DPO_0;`
96			`wire [7:0] SPO_0;`
97
98			`wire [7:0] DPO_1;`
99			`wire [7:0] SPO_1;`
100
101			`wire WE_0 ;`
102			`wire WE_1 ;`
103
104			`assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;`
105			`assign SPO = A[4] ? SPO_1 : SPO_0 ;`
106
107			`assign WE_0 = !A[4] && WE ;`
108			`assign WE_1 = A[4] && WE ;`
109
110			`RAM16X1D ram32x1d_0_0(`
111			`.DPO(DPO_0[0]),`
112			`.SPO(SPO_0[0]),`
113			`.A0(A[0]),`
114			`.A1(A[1]),`
115			`.A2(A[2]),`
116			`.A3(A[3]),`
117			`.D(D[0]),`
118			`.DPRA0(DPRA[0]),`
119			`.DPRA1(DPRA[1]),`
120			`.DPRA2(DPRA[2]),`
121			`.DPRA3(DPRA[3]),`
122			`.WCLK(WCLK),`
123			`.WE(WE_0)`
124			`);`
125
126			`//`
127			`// Instantiation of block 1`
128			`//`
129			`RAM16X1D ram32x1d_0_1(`
130			`.DPO(DPO_0[1]),`
131			`.SPO(SPO_0[1]),`
132			`.A0(A[0]),`
133			`.A1(A[1]),`
134			`.A2(A[2]),`
135			`.A3(A[3]),`
136			`.D(D[1]),`
137			`.DPRA0(DPRA[0]),`
138			`.DPRA1(DPRA[1]),`
139			`.DPRA2(DPRA[2]),`
140			`.DPRA3(DPRA[3]),`
141			`.WCLK(WCLK),`
142			`.WE(WE_0)`
143			`);`
144
145			`//`
146			`// Instantiation of block 2`
147			`//`
148			`RAM16X1D ram32x1d_0_2(`
149			`.DPO(DPO_0[2]),`
150			`.SPO(SPO_0[2]),`
151			`.A0(A[0]),`
152			`.A1(A[1]),`
153			`.A2(A[2]),`
154			`.A3(A[3]),`
155			`.D(D[2]),`
156			`.DPRA0(DPRA[0]),`
157			`.DPRA1(DPRA[1]),`
158			`.DPRA2(DPRA[2]),`
159			`.DPRA3(DPRA[3]),`
160			`.WCLK(WCLK),`
161			`.WE(WE_0)`
162			`);`
163
164			`//`
165			`// Instantiation of block 3`
166			`//`
167			`RAM16X1D ram32x1d_0_3(`
168			`.DPO(DPO_0[3]),`
169			`.SPO(SPO_0[3]),`
170			`.A0(A[0]),`
171			`.A1(A[1]),`
172			`.A2(A[2]),`
173			`.A3(A[3]),`
174			`.D(D[3]),`
175			`.DPRA0(DPRA[0]),`
176			`.DPRA1(DPRA[1]),`
177			`.DPRA2(DPRA[2]),`
178			`.DPRA3(DPRA[3]),`
179			`.WCLK(WCLK),`
180			`.WE(WE_0)`
181			`);`
182
183			`//`
184			`// Instantiation of block 4`
185			`//`
186			`RAM16X1D ram32x1d_0_4(`
187			`.DPO(DPO_0[4]),`
188			`.SPO(SPO_0[4]),`
189			`.A0(A[0]),`
190			`.A1(A[1]),`
191			`.A2(A[2]),`
192			`.A3(A[3]),`
193			`.D(D[4]),`
194			`.DPRA0(DPRA[0]),`
195			`.DPRA1(DPRA[1]),`
196			`.DPRA2(DPRA[2]),`
197			`.DPRA3(DPRA[3]),`
198			`.WCLK(WCLK),`
199			`.WE(WE_0)`
200			`);`
201
202			`//`
203			`// Instantiation of block 5`
204			`//`
205			`RAM16X1D ram32x1d_0_5(`
206			`.DPO(DPO_0[5]),`
207			`.SPO(SPO_0[5]),`
208			`.A0(A[0]),`
209			`.A1(A[1]),`
210			`.A2(A[2]),`
211			`.A3(A[3]),`
212			`.D(D[5]),`
213			`.DPRA0(DPRA[0]),`
214			`.DPRA1(DPRA[1]),`
215			`.DPRA2(DPRA[2]),`
216			`.DPRA3(DPRA[3]),`
217			`.WCLK(WCLK),`
218			`.WE(WE_0)`
219			`);`
220
221			`//`
222			`// Instantiation of block 6`
223			`//`
224			`RAM16X1D ram32x1d_0_6(`
225			`.DPO(DPO_0[6]),`
226			`.SPO(SPO_0[6]),`
227			`.A0(A[0]),`
228			`.A1(A[1]),`
229			`.A2(A[2]),`
230			`.A3(A[3]),`
231			`.D(D[6]),`
232			`.DPRA0(DPRA[0]),`
233			`.DPRA1(DPRA[1]),`
234			`.DPRA2(DPRA[2]),`
235			`.DPRA3(DPRA[3]),`
236			`.WCLK(WCLK),`
237			`.WE(WE_0)`
238			`);`
239
240			`//`
241			`// Instantiation of block 7`
242			`//`
243			`RAM16X1D ram32x1d_0_7(`
244			`.DPO(DPO_0[7]),`
245			`.SPO(SPO_0[7]),`
246			`.A0(A[0]),`
247			`.A1(A[1]),`
248			`.A2(A[2]),`
249			`.A3(A[3]),`
250			`.D(D[7]),`
251			`.DPRA0(DPRA[0]),`
252			`.DPRA1(DPRA[1]),`
253			`.DPRA2(DPRA[2]),`
254			`.DPRA3(DPRA[3]),`
255			`.WCLK(WCLK),`
256			`.WE(WE_0)`
257			`);`
258
259			`RAM16X1D ram32x1d_1_0(`
260			`.DPO(DPO_1[0]),`
261			`.SPO(SPO_1[0]),`
262			`.A0(A[0]),`
263			`.A1(A[1]),`
264			`.A2(A[2]),`
265			`.A3(A[3]),`
266			`.D(D[0]),`
267			`.DPRA0(DPRA[0]),`
268			`.DPRA1(DPRA[1]),`
269			`.DPRA2(DPRA[2]),`
270			`.DPRA3(DPRA[3]),`
271			`.WCLK(WCLK),`
272			`.WE(WE_1)`
273			`);`
274
275			`//`
276			`// Instantiation of block 1`
277			`//`
278			`RAM16X1D ram32x1d_1_1(`
279			`.DPO(DPO_1[1]),`
280			`.SPO(SPO_1[1]),`
281			`.A0(A[0]),`
282			`.A1(A[1]),`
283			`.A2(A[2]),`
284			`.A3(A[3]),`
285			`.D(D[1]),`
286			`.DPRA0(DPRA[0]),`
287			`.DPRA1(DPRA[1]),`
288			`.DPRA2(DPRA[2]),`
289			`.DPRA3(DPRA[3]),`
290			`.WCLK(WCLK),`
291			`.WE(WE_1)`
292			`);`
293
294			`//`
295			`// Instantiation of block 2`
296			`//`
297			`RAM16X1D ram32x1d_1_2(`
298			`.DPO(DPO_1[2]),`
299			`.SPO(SPO_1[2]),`
300			`.A0(A[0]),`
301			`.A1(A[1]),`
302			`.A2(A[2]),`
303			`.A3(A[3]),`
304			`.D(D[2]),`
305			`.DPRA0(DPRA[0]),`
306			`.DPRA1(DPRA[1]),`
307			`.DPRA2(DPRA[2]),`
308			`.DPRA3(DPRA[3]),`
309			`.WCLK(WCLK),`
310			`.WE(WE_1)`
311			`);`
312
313			`//`
314			`// Instantiation of block 3`
315			`//`
316			`RAM16X1D ram32x1d_1_3(`
317			`.DPO(DPO_1[3]),`
318			`.SPO(SPO_1[3]),`
319			`.A0(A[0]),`
320			`.A1(A[1]),`
321			`.A2(A[2]),`
322			`.A3(A[3]),`
323			`.D(D[3]),`
324			`.DPRA0(DPRA[0]),`
325			`.DPRA1(DPRA[1]),`
326			`.DPRA2(DPRA[2]),`
327			`.DPRA3(DPRA[3]),`
328			`.WCLK(WCLK),`
329			`.WE(WE_1)`
330			`);`
331
332			`//`
333			`// Instantiation of block 4`
334			`//`
335			`RAM16X1D ram32x1d_1_4(`
336			`.DPO(DPO_1[4]),`
337			`.SPO(SPO_1[4]),`
338			`.A0(A[0]),`
339			`.A1(A[1]),`
340			`.A2(A[2]),`
341			`.A3(A[3]),`
342			`.D(D[4]),`
343			`.DPRA0(DPRA[0]),`
344			`.DPRA1(DPRA[1]),`
345			`.DPRA2(DPRA[2]),`
346			`.DPRA3(DPRA[3]),`
347			`.WCLK(WCLK),`
348			`.WE(WE_1)`
349			`);`
350
351			`//`
352			`// Instantiation of block 5`
353			`//`
354			`RAM16X1D ram32x1d_1_5(`
355			`.DPO(DPO_1[5]),`
356			`.SPO(SPO_1[5]),`
357			`.A0(A[0]),`
358			`.A1(A[1]),`
359			`.A2(A[2]),`
360			`.A3(A[3]),`
361			`.D(D[5]),`
362			`.DPRA0(DPRA[0]),`
363			`.DPRA1(DPRA[1]),`
364			`.DPRA2(DPRA[2]),`
365			`.DPRA3(DPRA[3]),`
366			`.WCLK(WCLK),`
367			`.WE(WE_1)`
368			`);`
369
370			`//`
371			`// Instantiation of block 6`
372			`//`
373			`RAM16X1D ram32x1d_1_6(`
374			`.DPO(DPO_1[6]),`
375			`.SPO(SPO_1[6]),`
376			`.A0(A[0]),`
377			`.A1(A[1]),`
378			`.A2(A[2]),`
379			`.A3(A[3]),`
380			`.D(D[6]),`
381			`.DPRA0(DPRA[0]),`
382			`.DPRA1(DPRA[1]),`
383			`.DPRA2(DPRA[2]),`
384			`.DPRA3(DPRA[3]),`
385			`.WCLK(WCLK),`
386			`.WE(WE_1)`
387			`);`
388
389			`//`
390			`// Instantiation of block 7`
391			`//`
392			`RAM16X1D ram32x1d_1_7(`
393			`.DPO(DPO_1[7]),`
394			`.SPO(SPO_1[7]),`
395			`.A0(A[0]),`
396			`.A1(A[1]),`
397			`.A2(A[2]),`
398			`.A3(A[3]),`
399			`.D(D[7]),`
400			`.DPRA0(DPRA[0]),`
401			`.DPRA1(DPRA[1]),`
402			`.DPRA2(DPRA[2]),`
403			`.DPRA3(DPRA[3]),`
404			`.WCLK(WCLK),`
405			`.WE(WE_1)`
406			`);`
407			`endmodule`
408
409			`else
410
411			`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
412
413			`//`
414			`// I/O`
415			`//`
416			`output [7:0] DPO;`
417			`output [7:0] SPO;`
418			`input [4:0] A;`
419			`input [4:0] DPRA;`
420			`input [7:0] D;`
421			`input WCLK;`
422			`input WE;`
423
424			`//`
425			`// Instantiation of block 0`
426			`//`
427			`RAM32X1D ram32x1d_0(`
428			`.DPO(DPO[0]),`
429			`.SPO(SPO[0]),`
430			`.A0(A[0]),`
431			`.A1(A[1]),`
432			`.A2(A[2]),`
433			`.A3(A[3]),`
434			`.A4(A[4]),`
435			`.D(D[0]),`
436			`.DPRA0(DPRA[0]),`
437			`.DPRA1(DPRA[1]),`
438			`.DPRA2(DPRA[2]),`
439			`.DPRA3(DPRA[3]),`
440			`.DPRA4(DPRA[4]),`
441			`.WCLK(WCLK),`
442			`.WE(WE)`
443			`);`
444
445			`//`
446			`// Instantiation of block 1`
447			`//`
448			`RAM32X1D ram32x1d_1(`
449			`.DPO(DPO[1]),`
450			`.SPO(SPO[1]),`
451			`.A0(A[0]),`
452			`.A1(A[1]),`
453			`.A2(A[2]),`
454			`.A3(A[3]),`
455			`.A4(A[4]),`
456			`.D(D[1]),`
457			`.DPRA0(DPRA[0]),`
458			`.DPRA1(DPRA[1]),`
459			`.DPRA2(DPRA[2]),`
460			`.DPRA3(DPRA[3]),`
461			`.DPRA4(DPRA[4]),`
462			`.WCLK(WCLK),`
463			`.WE(WE)`
464			`);`
465
466			`//`
467			`// Instantiation of block 2`
468			`//`
469			`RAM32X1D ram32x1d_2(`
470			`.DPO(DPO[2]),`
471			`.SPO(SPO[2]),`
472			`.A0(A[0]),`
473			`.A1(A[1]),`
474			`.A2(A[2]),`
475			`.A3(A[3]),`
476			`.A4(A[4]),`
477			`.D(D[2]),`
478			`.DPRA0(DPRA[0]),`
479			`.DPRA1(DPRA[1]),`
480			`.DPRA2(DPRA[2]),`
481			`.DPRA3(DPRA[3]),`
482			`.DPRA4(DPRA[4]),`
483			`.WCLK(WCLK),`
484			`.WE(WE)`
485			`);`
486
487			`//`
488			`// Instantiation of block 3`
489			`//`
490			`RAM32X1D ram32x1d_3(`
491			`.DPO(DPO[3]),`
492			`.SPO(SPO[3]),`
493			`.A0(A[0]),`
494			`.A1(A[1]),`
495			`.A2(A[2]),`
496			`.A3(A[3]),`
497			`.A4(A[4]),`
498			`.D(D[3]),`
499			`.DPRA0(DPRA[0]),`
500			`.DPRA1(DPRA[1]),`
501			`.DPRA2(DPRA[2]),`
502			`.DPRA3(DPRA[3]),`
503			`.DPRA4(DPRA[4]),`
504			`.WCLK(WCLK),`
505			`.WE(WE)`
506			`);`
507
508			`//`
509			`// Instantiation of block 4`
510			`//`
511			`RAM32X1D ram32x1d_4(`
512			`.DPO(DPO[4]),`
513			`.SPO(SPO[4]),`
514			`.A0(A[0]),`
515			`.A1(A[1]),`
516			`.A2(A[2]),`
517			`.A3(A[3]),`
518			`.A4(A[4]),`
519			`.D(D[4]),`
520			`.DPRA0(DPRA[0]),`
521			`.DPRA1(DPRA[1]),`
522			`.DPRA2(DPRA[2]),`
523			`.DPRA3(DPRA[3]),`
524			`.DPRA4(DPRA[4]),`
525			`.WCLK(WCLK),`
526			`.WE(WE)`
527			`);`
528
529			`//`
530			`// Instantiation of block 5`
531			`//`
532			`RAM32X1D ram32x1d_5(`
533			`.DPO(DPO[5]),`
534			`.SPO(SPO[5]),`
535			`.A0(A[0]),`
536			`.A1(A[1]),`
537			`.A2(A[2]),`
538			`.A3(A[3]),`
539			`.A4(A[4]),`
540			`.D(D[5]),`
541			`.DPRA0(DPRA[0]),`
542			`.DPRA1(DPRA[1]),`
543			`.DPRA2(DPRA[2]),`
544			`.DPRA3(DPRA[3]),`
545			`.DPRA4(DPRA[4]),`
546			`.WCLK(WCLK),`
547			`.WE(WE)`
548			`);`
549
550			`//`
551			`// Instantiation of block 6`
552			`//`
553			`RAM32X1D ram32x1d_6(`
554			`.DPO(DPO[6]),`
555			`.SPO(SPO[6]),`
556			`.A0(A[0]),`
557			`.A1(A[1]),`
558			`.A2(A[2]),`
559			`.A3(A[3]),`
560			`.A4(A[4]),`
561			`.D(D[6]),`
562			`.DPRA0(DPRA[0]),`
563			`.DPRA1(DPRA[1]),`
564			`.DPRA2(DPRA[2]),`
565			`.DPRA3(DPRA[3]),`
566			`.DPRA4(DPRA[4]),`
567			`.WCLK(WCLK),`
568			`.WE(WE)`
569			`);`
570
571			`//`
572			`// Instantiation of block 7`
573			`//`
574			`RAM32X1D ram32x1d_7(`
575			`.DPO(DPO[7]),`
576			`.SPO(SPO[7]),`
577			`.A0(A[0]),`
578			`.A1(A[1]),`
579			`.A2(A[2]),`
580			`.A3(A[3]),`
581			`.A4(A[4]),`
582			`.D(D[7]),`
583			`.DPRA0(DPRA[0]),`
584			`.DPRA1(DPRA[1]),`
585			`.DPRA2(DPRA[2]),`
586			`.DPRA3(DPRA[3]),`
587			`.DPRA4(DPRA[4]),`
588			`.WCLK(WCLK),`
589			`.WE(WE)`
590			`);`
591
592			`endmodule`
593			`endif
594			`endif