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[/] [openrisc/] [trunk/] [or1k_startup/] [sw/] [OR1K_startup.S] - Blame information for rev 792

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/*
        Register usage
        R0 = 0
        R1 = pointer to destination
        R2 = nr of words to be copied
        R3 = data
        R4 = pointer to SPI core
        R5 = spi control word
        R6 = jump adr
        R7 = nr of control words
        r8 = adr pointer
*/
        .equ spi_base,0xb0000000 ;
        .equ spi_ctrl,0x0520    ;
        .equ read_cmd, 0x03000000 ;
 
        .global start           ;
        .text
start:
        l.movhi r0,0x0          ;
        l.ori r1,r0,0x0 ; # R1 = 0x0
        l.movhi r4,hi(spi_base) ; # R4 = spi base
        l.ori r5,r0,lo(spi_ctrl); # R5 = spi control
 
        # set SPI regs, can be removed if reset state is changed in IP core
        #l.ori r3,r0,0x420      ;
        #l.sw 0x10(r4),r3       ; # tx at negedge, 32 bit transfer
        #l.movhi r3,0x0300      ;
        #l.ori r3,r3,0x0        ;
        #l.sw 0x0(r4),r3        ; # TX = 0x03000000
        #l.sw 0x14(r4),r0       ; # prescaler to zero
 
        # set slave select active
        l.ori r3,r0,0x1         ; # R3 = 0x1
 
        # initiate SPI FLASH READ
        l.jal read              ;
        l.sw 0x18(r4),r3        ; # ss active
 
        # read
        l.jal read              ;
        l.sw 0x0(r4),r0         ; # set TX to zero
        l.or r2,r3,r3           ; # R2 = nr of words
 
loop1:  l.jal read              ; # read adr pointer
        l.addi r1,r1,0x8        ;
        l.jal read              ; # read data
        l.or r8,r3,r3           ; # copy adr pointer to r8
        l.sfeq r8,r0            ;
        l.bnf loop1             ;
        l.sw 0x0(r8),r3         ; # write control data
 
loop2:  l.jal read              ;
        l.addi r1,r1,0x4        ;
        l.sw 0x0(r1),r3         ; # write to RAM
        l.sfeq r1,r2            ;
        l.bnf loop2             ;
        l.ori r6,r0,0x100       ;
        l.jr r6                 ;
        # set slave select inactive
        l.sw 0x18(r4),r0        ; # set slave select inactive
 
read:
        l.sw 0x10(r4),r5        ; # write spi control
w4busy: l.lwz r3,0x10(r4)       ;
        l.sfeqi r3,lo(spi_ctrl) ;
        l.bf w4busy             ;
        l.nop                   ;
        l.jr r9                 ;
        l.lwz r3,0x0(r4)        ; # R3 = RX
 

Line No.	Rev	Author	Line
1	2	marcus.erl	`/*`
2			`Register usage`
3			`R0 = 0`
4			`R1 = pointer to destination`
5			`R2 = nr of words to be copied`
6			`R3 = data`
7			`R4 = pointer to SPI core`
8			`R5 = spi control word`
9			`R6 = jump adr`
10			`R7 = nr of control words`
11			`r8 = adr pointer`
12			`*/`
13			`.equ spi_base,0xb0000000 ;`
14			`.equ spi_ctrl,0x0520 ;`
15			`.equ read_cmd, 0x03000000 ;`
16
17			`.global start ;`
18			`.text`
19			`start:`
20			`l.movhi r0,0x0 ;`
21			`l.ori r1,r0,0x0 ; # R1 = 0x0`
22			`l.movhi r4,hi(spi_base) ; # R4 = spi base`
23			`l.ori r5,r0,lo(spi_ctrl); # R5 = spi control`
24
25			`# set SPI regs, can be removed if reset state is changed in IP core`
26			`#l.ori r3,r0,0x420 ;`
27			`#l.sw 0x10(r4),r3 ; # tx at negedge, 32 bit transfer`
28			`#l.movhi r3,0x0300 ;`
29			`#l.ori r3,r3,0x0 ;`
30			`#l.sw 0x0(r4),r3 ; # TX = 0x03000000`
31			`#l.sw 0x14(r4),r0 ; # prescaler to zero`
32
33			`# set slave select active`
34			`l.ori r3,r0,0x1 ; # R3 = 0x1`
35
36			`# initiate SPI FLASH READ`
37			`l.jal read ;`
38			`l.sw 0x18(r4),r3 ; # ss active`
39
40			`# read`
41			`l.jal read ;`
42			`l.sw 0x0(r4),r0 ; # set TX to zero`
43			`l.or r2,r3,r3 ; # R2 = nr of words`
44
45			`loop1: l.jal read ; # read adr pointer`
46			`l.addi r1,r1,0x8 ;`
47			`l.jal read ; # read data`
48			`l.or r8,r3,r3 ; # copy adr pointer to r8`
49			`l.sfeq r8,r0 ;`
50			`l.bnf loop1 ;`
51			`l.sw 0x0(r8),r3 ; # write control data`
52
53			`loop2: l.jal read ;`
54			`l.addi r1,r1,0x4 ;`
55			`l.sw 0x0(r1),r3 ; # write to RAM`
56			`l.sfeq r1,r2 ;`
57			`l.bnf loop2 ;`
58			`l.ori r6,r0,0x100 ;`
59			`l.jr r6 ;`
60			`# set slave select inactive`
61			`l.sw 0x18(r4),r0 ; # set slave select inactive`
62
63			`read:`
64			`l.sw 0x10(r4),r5 ; # write spi control`
65			`w4busy: l.lwz r3,0x10(r4) ;`
66			`l.sfeqi r3,lo(spi_ctrl) ;`
67			`l.bf w4busy ;`
68			`l.nop ;`
69			`l.jr r9 ;`
70			`l.lwz r3,0x0(r4) ; # R3 = RX`
71

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[/] [openrisc/] [trunk/] [or1k_startup/] [sw/] [OR1K_startup.S] - Blame information for rev 792