OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [cfg/] [cfg.S] - Blame information for rev 97

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn 
/* cfg.s. CPU configuration test of Or1ksim
2 
 
3 
   Copyright (C) 1999-2006 OpenCores
4 
   Copyright (C) 2010 Embecosm Limited
5 
 
6 
   Contributors various OpenCores participants
7 
   Contributor Jeremy Bennett
8 
 
9 
   This file is part of OpenRISC 1000 Architectural Simulator.
10 
 
11 
   This program is free software; you can redistribute it and/or modify it
12 
   under the terms of the GNU General Public License as published by the Free
13 
   Software Foundation; either version 3 of the License, or (at your option)
14 
   any later version.
15 
 
16 
   This program is distributed in the hope that it will be useful, but WITHOUT
17 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
   more details.
20 
 
21 
   You should have received a copy of the GNU General Public License along
22 
   with this program.  If not, see .  */
23 
 
24 
/* ----------------------------------------------------------------------------
25 
   This code is commented throughout for use with Doxygen.
26 
   --------------------------------------------------------------------------*/
27 
 
28 
#include "spr-defs.h"
29 
 
30 
        .section .except, "ax"
31 
        l.addi  r2,r0,0
32 
 
33 
        .section .text
34 
        .org 0x100
35 
_reset:
36 
        l.addi  r1,r0,0x7f00
37 
        l.movhi r2,hi(_main)
38 
        l.ori   r2,r2,lo(_main)
39 
        l.jr    r2
40 
        l.nop
41 
 
42 
 
43 
_main:
44 
        l.addi  r2,r0,0
45 
 
46 
        l.mfspr r3,r0,SPR_VR            /* Version */
47 
  l.nop NOP_REPORT
48 
        l.add   r2,r2,r3
49 
 
50 
        l.mfspr r3,r0,SPR_UPR           /* Unit Present */
51 
  l.nop NOP_REPORT
52 
        l.add   r2,r2,r3
53 
 
54 
        l.mfspr r4,r0,SPR_PMR           /* Power Management */
55 
        l.addi  r3,r0,0
56 
        l.mtspr r0,r3,SPR_PMR
57 
        l.mfspr r3,r0,SPR_PMR
58 
        l.andi  r3,r3,0xff
59 
        l.nop NOP_REPORT
60 
        l.add   r2,r2,r3
61 
 
62 
        l.addi  r3,r0,5
63 
        l.mtspr r0,r3,SPR_PMR
64 
        l.mfspr r3,r0,SPR_PMR
65 
        l.andi  r3,r3,0xff
66 
        l.nop NOP_REPORT
67 
        l.add   r2,r2,r3
68 
 
69 
        l.mtspr r0,r4,SPR_PMR
70 
 
71 
        l.mfspr r3,r0,SPR_CPUCFGR
72 
        l.nop NOP_REPORT
73 
        l.add   r2,r2,r3
74 
 
75 
        l.mfspr r3,r0,SPR_DMMUCFGR
76 
        l.nop NOP_REPORT
77 
        l.add   r2,r2,r3
78 
 
79 
        l.mfspr r3,r0,SPR_IMMUCFGR
80 
        l.nop NOP_REPORT
81 
        l.add   r2,r2,r3
82 
 
83 
        l.mfspr r3,r0,SPR_DCCFGR
84 
        l.nop NOP_REPORT
85 
        l.add   r2,r2,r3
86 
 
87 
        l.mfspr r3,r0,SPR_ICCFGR
88 
        l.nop NOP_REPORT
89 
        l.add   r2,r2,r3
90 
 
91 
        l.mfspr r3,r0,SPR_DCFGR
92 
        l.nop NOP_REPORT
93 
        l.add   r2,r2,r3
94 
 
95 
        l.mfspr r3,r0,SPR_PCCFGR
96 
        l.nop NOP_REPORT
97 
        l.add   r2,r2,r3
98 
 
99 
        /* Configurations may differ, so we will insert another report*/
100 
        l.movhi r3,hi(0xdeacf5cc)
101 
        l.ori   r3,r3,lo(0xdeacf5cc)
102 
        l.add   r3,r2,r3
103 
  l.nop NOP_REPORT
104 
 
105 
        l.movhi r3,hi(0xdeaddead)
106 
        l.ori   r3,r3,lo(0xdeaddead)
107 
  l.nop NOP_REPORT
108 
        l.addi  r3,r0,0
109 
        l.nop NOP_EXIT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.