OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocAccess.cpp] - Blame information for rev 57

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 julius
// ----------------------------------------------------------------------------
2
 
3
// Access functions for the ORPSoC Verilator model: implementation
4
 
5
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
6
 
7
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 44 julius
// Contributor Julius Baxter <jb@orsoc.se>
9 6 julius
 
10
// This file is part of the cycle accurate model of the OpenRISC 1000 based
11
// system-on-chip, ORPSoC, built using Verilator.
12
 
13
// This program is free software: you can redistribute it and/or modify it
14
// under the terms of the GNU Lesser General Public License as published by
15
// the Free Software Foundation, either version 3 of the License, or (at your
16
// option) any later version.
17
 
18
// This program is distributed in the hope that it will be useful, but WITHOUT
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
21
// License for more details.
22
 
23
// You should have received a copy of the GNU Lesser General Public License
24
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
25
 
26
// ----------------------------------------------------------------------------
27
 
28
// $Id: OrpsocAccess.cpp 303 2009-02-16 11:20:17Z jeremy $
29
 
30
#include "OrpsocAccess.h"
31
 
32
#include "Vorpsoc_top.h"
33
#include "Vorpsoc_top_orpsoc_top.h"
34
#include "Vorpsoc_top_or1k_top.h"
35
#include "Vorpsoc_top_or1200_top.h"
36
#include "Vorpsoc_top_or1200_cpu.h"
37
#include "Vorpsoc_top_or1200_ctrl.h"
38 44 julius
#include "Vorpsoc_top_or1200_except.h"
39
#include "Vorpsoc_top_or1200_sprs.h"
40 6 julius
#include "Vorpsoc_top_or1200_rf.h"
41
#include "Vorpsoc_top_or1200_dpram.h"
42 51 julius
//#include "Vorpsoc_top_ram_wb.h"
43
//#include "Vorpsoc_top_ram_wb_sc_sw.h"
44
#include "Vorpsoc_top_ram_wb__D20_A18_M800000.h"
45
#include "Vorpsoc_top_ram_wb_sc_sw__D20_A18_M800000.h"
46 6 julius
 
47
//! Constructor for the ORPSoC access class
48
 
49
//! Initializes the pointers to the various module instances of interest
50
//! within the Verilator model.
51
 
52
//! @param[in] orpsoc  The SystemC Verilated ORPSoC instance
53
 
54
OrpsocAccess::OrpsocAccess (Vorpsoc_top *orpsoc_top)
55
{
56
  or1200_ctrl = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_ctrl;
57 44 julius
  or1200_except = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_except;
58
  or1200_sprs = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_sprs;
59 6 julius
  rf_a        = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_rf->rf_a;
60 51 julius
  ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0;
61 6 julius
 
62
}       // OrpsocAccess ()
63
 
64 51 julius
//! Access for the ex_freeze signal
65 6 julius
 
66 51 julius
//! @return  The value of the or1200_ctrl.ex_freeze signal
67
 
68
bool
69
OrpsocAccess::getExFreeze ()
70
{
71
  return  or1200_ctrl->ex_freeze;
72
 
73
}       // getExFreeze ()
74
 
75 6 julius
//! Access for the wb_freeze signal
76
 
77
//! @return  The value of the or1200_ctrl.wb_freeze signal
78
 
79
bool
80
OrpsocAccess::getWbFreeze ()
81
{
82
  return  or1200_ctrl->wb_freeze;
83
 
84
}       // getWbFreeze ()
85
 
86 44 julius
//! Access for the except_flushpipe signal
87 6 julius
 
88 44 julius
//! @return  The value of the or1200_except.except_flushpipe signal
89
 
90
bool
91
OrpsocAccess::getExceptFlushpipe ()
92
{
93
  return  or1200_except->except_flushpipe;
94
 
95
}       // getExceptFlushpipe ()
96
 
97
//! Access for the ex_dslot signal
98
 
99
//! @return  The value of the or1200_except.ex_dslot signalfac
100
 
101
bool
102
OrpsocAccess::getExDslot ()
103
{
104
  return  or1200_except->ex_dslot;
105
 
106
}       // getExDslot ()
107
 
108 51 julius
//! Access for the except_type value
109
 
110
//! @return  The value of the or1200_except.except_type register
111
 
112
uint32_t
113
OrpsocAccess::getExceptType ()
114
{
115
  return  (or1200_except->get_except_type) ();
116
 
117
}       // getExceptType ()
118
 
119
 
120 49 julius
//! Access for the id_pc register
121
 
122
//! @return  The value of the or1200_except.id_pc register
123
 
124
uint32_t
125
OrpsocAccess::getIdPC ()
126
{
127
  return  (or1200_except->get_id_pc) ();
128
 
129
}       // getIdPC ()
130
 
131 51 julius
//! Access for the ex_pc register
132
 
133
//! @return  The value of the or1200_except.id_ex register
134
 
135
uint32_t
136
OrpsocAccess::getExPC ()
137
{
138
  return  (or1200_except->get_ex_pc) ();
139
 
140
}       // getExPC ()
141
 
142 44 julius
//! Access for the wb_pc register
143
 
144 49 julius
//! @return  The value of the or1200_except.wb_pc register
145 44 julius
 
146
uint32_t
147
OrpsocAccess::getWbPC ()
148
{
149
  return  (or1200_except->get_wb_pc) ();
150
 
151
}       // getWbPC ()
152
 
153 51 julius
//! Access for the id_insn register
154
 
155
//! @return  The value of the or1200_ctrl.wb_insn register
156
 
157
uint32_t
158
OrpsocAccess::getIdInsn ()
159
{
160
  return  (or1200_ctrl->get_id_insn) ();
161
 
162
}       // getIdInsn ()
163
 
164
//! Access for the ex_insn register
165
 
166
//! @return  The value of the or1200_ctrl.ex_insn register
167
 
168
uint32_t
169
OrpsocAccess::getExInsn ()
170
{
171
  return  (or1200_ctrl->get_ex_insn) ();
172
 
173
}       // getExInsn ()
174
 
175
 
176 6 julius
//! Access for the wb_insn register
177
 
178
//! @return  The value of the or1200_ctrl.wb_insn register
179
 
180
uint32_t
181
OrpsocAccess::getWbInsn ()
182
{
183
  return  (or1200_ctrl->get_wb_insn) ();
184
 
185
}       // getWbInsn ()
186
 
187 51 julius
//! Access the Wishbone SRAM memory
188 6 julius
 
189 51 julius
//! @return  The value of the memory word at addr
190 49 julius
 
191
uint32_t
192 51 julius
OrpsocAccess::get_mem (uint32_t addr)
193 49 julius
{
194 51 julius
  return  (ram_wb_sc_sw->get_mem) (addr);
195 49 julius
 
196 51 julius
}       // get_mem ()
197 49 julius
 
198 51 julius
//! Write value to the Wishbone SRAM memory
199
 
200
void
201
OrpsocAccess::set_mem (uint32_t addr, uint32_t data)
202
{
203
  (ram_wb_sc_sw->set_mem) (addr, data);
204
 
205
}       // set_mem ()
206
 
207
//! Trigger the $readmemh() system call
208
 
209
void
210
OrpsocAccess::do_ram_readmemh (void)
211
{
212
  (ram_wb_sc_sw->do_readmemh) ();
213
 
214
}       // do_ram_readmemh ()
215
 
216 6 julius
//! Access for the OR1200 GPRs
217
 
218
//! These are extracted from memory using the Verilog function
219
 
220
//! @param[in] regNum  The GPR whose value is wanted
221
 
222
//! @return            The value of the GPR
223
 
224
uint32_t
225
OrpsocAccess::getGpr (uint32_t  regNum)
226
{
227
  return  (rf_a->get_gpr) (regNum);
228
 
229
}       // getGpr ()
230 44 julius
 
231
 
232
//! Access for the sr register
233
 
234
//! @return  The value of the or1200_sprs.sr register
235
 
236
uint32_t
237
OrpsocAccess::getSprSr ()
238
{
239
  return  (or1200_sprs->get_sr) ();
240
 
241
}       // getSprSr ()
242
 
243
//! Access for the epcr register
244
 
245
//! @return  The value of the or1200_sprs.epcr register
246
 
247
uint32_t
248
OrpsocAccess::getSprEpcr ()
249
{
250
  return  (or1200_sprs->get_epcr) ();
251
 
252
}       // getSprEpcr ()
253
 
254
//! Access for the eear register
255
 
256
//! @return  The value of the or1200_sprs.eear register
257
 
258
uint32_t
259
OrpsocAccess::getSprEear ()
260
{
261
  return  (or1200_sprs->get_eear) ();
262
 
263
}       // getSprEear ()
264
 
265
//! Access for the esr register
266
 
267
//! @return  The value of the or1200_sprs.esr register
268
 
269
uint32_t
270
OrpsocAccess::getSprEsr ()
271
{
272
  return  (or1200_sprs->get_esr) ();
273
 
274
}       // getSprEsr ()
275
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.