| 1 |
408 |
julius |
`timescale 1 ns/100 ps
|
| 2 |
|
|
// Version: 8.6 8.6.0.34
|
| 3 |
|
|
|
| 4 |
|
|
|
| 5 |
|
|
module eth_pll(POWERDOWN,CLKA,LOCK,GLA);
|
| 6 |
|
|
input POWERDOWN, CLKA;
|
| 7 |
|
|
output LOCK, GLA;
|
| 8 |
|
|
|
| 9 |
|
|
wire CLKAP, VCC, GND;
|
| 10 |
|
|
|
| 11 |
|
|
VCC VCC_1_net(.Y(VCC));
|
| 12 |
|
|
GND GND_1_net(.Y(GND));
|
| 13 |
|
|
PLL #( .VCOFREQUENCY(125.000) ) Core(.CLKA(CLKAP), .EXTFB(
|
| 14 |
|
|
GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(
|
| 15 |
|
|
), .YB(), .GLC(), .YC(), .OADIV0(GND), .OADIV1(GND),
|
| 16 |
|
|
.OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND),
|
| 17 |
|
|
.OAMUX1(VCC), .OAMUX2(GND), .DLYGLA0(GND), .DLYGLA1(GND),
|
| 18 |
|
|
.DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND),
|
| 19 |
|
|
.OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND),
|
| 20 |
|
|
.OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND),
|
| 21 |
|
|
.DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND),
|
| 22 |
|
|
.DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND)
|
| 23 |
|
|
, .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND),
|
| 24 |
|
|
.OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND),
|
| 25 |
|
|
.OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND),
|
| 26 |
|
|
.DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND),
|
| 27 |
|
|
.DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(GND)
|
| 28 |
|
|
, .FINDIV1(VCC), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4(
|
| 29 |
|
|
VCC), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1(
|
| 30 |
|
|
VCC), .FBDIV2(VCC), .FBDIV3(GND), .FBDIV4(VCC), .FBDIV5(
|
| 31 |
|
|
GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(
|
| 32 |
|
|
GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(
|
| 33 |
|
|
GND), .XDLYSEL(VCC), .VCOSEL0(GND), .VCOSEL1(GND),
|
| 34 |
|
|
.VCOSEL2(VCC));
|
| 35 |
|
|
PLLINT pllint1(.A(CLKA), .Y(CLKAP));
|
| 36 |
|
|
|
| 37 |
|
|
endmodule
|
