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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [gbuf.v] - Blame information for rev 784

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`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
 
 
module gbuf(GL,CLK);
output GL;
input  CLK;
 
    wire GND;
 
    GND GND_1_net(.Y(GND));
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
endmodule

Line No.	Rev	Author	Line
1	408	julius	`timescale 1 ns/100 ps
2			`// Version: 8.4 8.4.0.33`
3
4
5			`module gbuf(GL,CLK);`
6			`output GL;`
7			`input CLK;`
8
9			`wire GND;`
10
11			`GND GND_1_net(.Y(GND));`
12			`CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),`
13			`.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;`
14
15			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [gbuf.v] - Blame information for rev 784