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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [reset_buffer.v] - Blame information for rev 784

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`timescale 1 ns/100 ps
// Version: 8.6 8.6.0.34
 
 
module reset_buffer(GL,CLK);
output GL;
input  CLK;
 
    wire CLKP, GND;
 
    GND GND_1_net(.Y(GND));
    PLLINT pllint1(.A(CLK), .Y(CLKP));
    CLKDLY Inst1(.CLK(CLKP), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND));
 
endmodule

Line No.	Rev	Author	Line
1	408	julius	`timescale 1 ns/100 ps
2			`// Version: 8.6 8.6.0.34`
3
4
5			`module reset_buffer(GL,CLK);`
6			`output GL;`
7			`input CLK;`
8
9			`wire CLKP, GND;`
10
11			`GND GND_1_net(.Y(GND));`
12			`PLLINT pllint1(.A(CLK), .Y(CLKP));`
13			`CLKDLY Inst1(.CLK(CLKP), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),`
14			`.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND));`
15
16			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [reset_buffer.v] - Blame information for rev 784