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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 408

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// orpsoc-defines                                               ////
////                                                              ////
//// Top level ORPSoC defines file                                ////
////                                                              ////
//// Included in toplevel and testbench                           ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
// Uncomment a `define BOARD_XYZ to configure design RTL for it.
//
// Mainly presets are for internal frequency settings, and what
// external oscillator is expected (ordb1's were made with various
// XTALs.)
//
//////////////////////////////////////////////////////////////////////
 
// ORSoC Dev board: XTAL: 64MHz, WB: 24MHz
//`define BOARD_ORSOC_DEV_XTAL64_WB24
 
// ORSoC Dev board: XTAL: 64MHz, WB: 20MHz
`define BOARD_ORSOC_DEV_XTAL64_WB20
 
// ORSoC Dev board: XTAL: 64MHz, WB: 18MHz
//`define BOARD_ORSOC_DEV_XTAL64_WB18
 
// ORSoC Dev board: XTAL: 64MHz, WB: 16MHz
//`define BOARD_ORSOC_DEV_XTAL64_WB16
 
// ORSoC Dev board: XTAL: 25MHz, WB: 24MHz
//`define BOARD_ORSOC_DEV_XTAL25_WB24
 
// ORSoC Dev board: XTAL: 25MHz, WB: 20MHz
//`define BOARD_ORSOC_DEV_XTAL25_WB20
 
// Actel simulation:
// Clock periods are used in  simulation only! 
// We generate our own because Actel's PLL model is buggy.
// CLKA is SDRAM clock
// CLKB is Wishbone clock
// CLKC is USB clock
 
`ifdef BOARD_ORSOC_DEV_XTAL64_WB24
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL64_WB24
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ETH_CLK_PLL
 `define ACTEL_PLL_CLKA_PERIOD 15.625     // 64 MHz
 `define ACTEL_PLL_CLKB_PERIOD 41.666667  // 24 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334   // 48 MHz
 `define BOARD_CLOCK_PERIOD 15.625     // 64 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
 `define CUSTOM_MODULES_CONFIG
`endif //  `ifdef BOARD_ORSOC_DEV_XTAL64_WB24
 
`ifdef BOARD_ORSOC_DEV_XTAL64_WB20
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL64_WB20
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ETH_CLK_PLL
 `define ACTEL_PLL_CLKA_PERIOD 15.625    // 64 MHz
 `define ACTEL_PLL_CLKB_PERIOD 50        // 20 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334  // 48 MHz
 `define BOARD_CLOCK_PERIOD 15.625    // 64 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
 `define CUSTOM_MODULES_CONFIG
`endif
 
`ifdef BOARD_ORSOC_DEV_XTAL64_WB18
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL64_WB18
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ETH_CLK_PLL
 `define ACTEL_PLL_CLKA_PERIOD 15.625    // 64 MHz
 `define ACTEL_PLL_CLKB_PERIOD 55.55556  // 18 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334  // 48 MHz
 `define BOARD_CLOCK_PERIOD 15.625    // 64 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
 `define CUSTOM_MODULES_CONFIG
`endif
 
`ifdef BOARD_ORSOC_DEV_XTAL64_WB16
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL64_WB16
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ETH_CLK_PLL
 `define ACTEL_PLL_CLKA_PERIOD 15.625    // 64 MHz
 `define ACTEL_PLL_CLKB_PERIOD 62.5      // 16 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334  // 48 MHz
 `define BOARD_CLOCK_PERIOD 15.625    // 64 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
 `define CUSTOM_MODULES_CONFIG
`endif
 
`ifdef BOARD_ORSOC_DEV_XTAL25_WB24
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL25_WB24
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ACTEL_PLL_CLKA_PERIOD 40        // 25 MHz
 `define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334  // 48 MHz
 `define BOARD_CLOCK_PERIOD 40        // 25 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
 `define CUSTOM_MODULES_CONFIG
`endif //  `ifdef BOARD_ORSOC_DEV_XTAL25_WB24
 
`ifdef BOARD_ORSOC_DEV_XTAL25_WB20
 `define ACTEL
 `define ACTEL_PLL
 `define PLL_XTAL25_WB20
 `define FPGA_BOARD_ORSOC_DEV
 `define IOCONFIG_ORSOC_IO_BOARD
 `define ETH_CLK
 `define ACTEL_PLL_CLKA_PERIOD 40        // 25 MHz
 `define ACTEL_PLL_CLKB_PERIOD 50        // 20 MHz
 `define ACTEL_PLL_CLKC_PERIOD 20.83334  // 48 MHz
 `define BOARD_CLOCK_PERIOD 40        // 25 MHz
// Modules in system (or `define CUSTOM_CONFIG and define below)
// `define CUSTOM_MODULES_CONFIG
// Included modules: define to include
 `define JTAG_DEBUG
 `define VERSATILE_SDRAM
 `define UART0
 `define SPI0
 `define I2C0
 `define GPIO0
 `define ETH0
 `define SMII0
`endif
 
`ifdef CUSTOM_MODULES_CONFIG
// Included modules: define to include
 `define JTAG_DEBUG
 `define VERSATILE_SDRAM
//`define RAM_WB
//`define ACTEL_UFR
 `define UART0
 `define SPI0
// `define SPI1
// `define SPI2
// `define I2C0
// `define I2C1
// `define I2C2
// `define I2C3
// `define USB0
// `define USB1
//`define GPIO0
`define ETH0
`define SMII0
 
`endif //  `ifdef CUSTOM_MODULES_CONFIG
 
 
// end of included module defines - keep this comment line here, scripts depend on it!!
 
`ifdef SPI0
 `define SPI0_SLAVE_SELECTS
`endif
 
 
`ifdef SPI1
 `define SPI1_SLAVE_SELECTS
`endif
 
`ifdef SPI2
 `define SPI2_SLAVE_SELECTS
`endif
 
`ifdef USB0
// Indicate we need clock for USB
`define USB_CLK
// uncomment this for the module to be only a host controller
 `define USB0_ONLY_HOST
`endif
 
 
`ifdef USB1
// If we haven't already, indicate we need clock for USB
 `ifndef USB_CLK
  `define USB_CLK
 `endif
 
// If both are commented out, USB1 is a host and slave otherwise uncomment
// only one of the following to instantiate the desired type:
// `define USB1_ONLY_HOST
 `define USB1_ONLY_SLAVE
`endif
 
 
`ifdef ETH0
// Define ETH0_PHY_RST here or where ETH0 is defined to enable an active-low
// reset output to the PHY if it's possible.
// `define ETH0_PHY_RST
`endif
 
`ifdef ETH_CLK
// Ethernet clock rate, for simulation
 `define ETHERNET_CLOCK_PERIOD 8.00 // 125 MHz
`endif
 
//
// Arbiter defines
//
 
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
 
// Data bus arbiter
 
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 408

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// orpsoc-defines ////`
4			`//// ////`
5			`//// Top level ORPSoC defines file ////`
6			`//// ////`
7			`//// Included in toplevel and testbench ////`
8			`//// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//`
37			// Uncomment a `define BOARD_XYZ to configure design RTL for it.
38			`//`
39			`// Mainly presets are for internal frequency settings, and what`
40			`// external oscillator is expected (ordb1's were made with various`
41			`// XTALs.)`
42			`//`
43			`//////////////////////////////////////////////////////////////////////`
44
45			`// ORSoC Dev board: XTAL: 64MHz, WB: 24MHz`
46			//`define BOARD_ORSOC_DEV_XTAL64_WB24
47
48			`// ORSoC Dev board: XTAL: 64MHz, WB: 20MHz`
49			`define BOARD_ORSOC_DEV_XTAL64_WB20
50
51			`// ORSoC Dev board: XTAL: 64MHz, WB: 18MHz`
52			//`define BOARD_ORSOC_DEV_XTAL64_WB18
53
54			`// ORSoC Dev board: XTAL: 64MHz, WB: 16MHz`
55			//`define BOARD_ORSOC_DEV_XTAL64_WB16
56
57			`// ORSoC Dev board: XTAL: 25MHz, WB: 24MHz`
58			//`define BOARD_ORSOC_DEV_XTAL25_WB24
59
60			`// ORSoC Dev board: XTAL: 25MHz, WB: 20MHz`
61			//`define BOARD_ORSOC_DEV_XTAL25_WB20
62
63			`// Actel simulation:`
64			`// Clock periods are used in simulation only!`
65			`// We generate our own because Actel's PLL model is buggy.`
66			`// CLKA is SDRAM clock`
67			`// CLKB is Wishbone clock`
68			`// CLKC is USB clock`
69
70			`ifdef BOARD_ORSOC_DEV_XTAL64_WB24
71			`define ACTEL
72			`define ACTEL_PLL
73			`define PLL_XTAL64_WB24
74			`define FPGA_BOARD_ORSOC_DEV
75			`define IOCONFIG_ORSOC_IO_BOARD
76			`define ETH_CLK
77			`define ETH_CLK_PLL
78			`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
79			`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
80			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
81			`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
82			// Modules in system (or `define CUSTOM_CONFIG and define below)
83			`define CUSTOM_MODULES_CONFIG
84			`endif // `ifdef BOARD_ORSOC_DEV_XTAL64_WB24
85
86			`ifdef BOARD_ORSOC_DEV_XTAL64_WB20
87			`define ACTEL
88			`define ACTEL_PLL
89			`define PLL_XTAL64_WB20
90			`define FPGA_BOARD_ORSOC_DEV
91			`define IOCONFIG_ORSOC_IO_BOARD
92			`define ETH_CLK
93			`define ETH_CLK_PLL
94			`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
95			`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
96			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
97			`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
98			// Modules in system (or `define CUSTOM_CONFIG and define below)
99			`define CUSTOM_MODULES_CONFIG
100			`endif
101
102			`ifdef BOARD_ORSOC_DEV_XTAL64_WB18
103			`define ACTEL
104			`define ACTEL_PLL
105			`define PLL_XTAL64_WB18
106			`define FPGA_BOARD_ORSOC_DEV
107			`define IOCONFIG_ORSOC_IO_BOARD
108			`define ETH_CLK
109			`define ETH_CLK_PLL
110			`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
111			`define ACTEL_PLL_CLKB_PERIOD 55.55556 // 18 MHz
112			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
113			`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
114			// Modules in system (or `define CUSTOM_CONFIG and define below)
115			`define CUSTOM_MODULES_CONFIG
116			`endif
117
118			`ifdef BOARD_ORSOC_DEV_XTAL64_WB16
119			`define ACTEL
120			`define ACTEL_PLL
121			`define PLL_XTAL64_WB16
122			`define FPGA_BOARD_ORSOC_DEV
123			`define IOCONFIG_ORSOC_IO_BOARD
124			`define ETH_CLK
125			`define ETH_CLK_PLL
126			`define ACTEL_PLL_CLKA_PERIOD 15.625 // 64 MHz
127			`define ACTEL_PLL_CLKB_PERIOD 62.5 // 16 MHz
128			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
129			`define BOARD_CLOCK_PERIOD 15.625 // 64 MHz
130			// Modules in system (or `define CUSTOM_CONFIG and define below)
131			`define CUSTOM_MODULES_CONFIG
132			`endif
133
134			`ifdef BOARD_ORSOC_DEV_XTAL25_WB24
135			`define ACTEL
136			`define ACTEL_PLL
137			`define PLL_XTAL25_WB24
138			`define FPGA_BOARD_ORSOC_DEV
139			`define IOCONFIG_ORSOC_IO_BOARD
140			`define ETH_CLK
141			`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
142			`define ACTEL_PLL_CLKB_PERIOD 41.666667 // 24 MHz
143			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
144			`define BOARD_CLOCK_PERIOD 40 // 25 MHz
145			// Modules in system (or `define CUSTOM_CONFIG and define below)
146			`define CUSTOM_MODULES_CONFIG
147			`endif // `ifdef BOARD_ORSOC_DEV_XTAL25_WB24
148
149			`ifdef BOARD_ORSOC_DEV_XTAL25_WB20
150			`define ACTEL
151			`define ACTEL_PLL
152			`define PLL_XTAL25_WB20
153			`define FPGA_BOARD_ORSOC_DEV
154			`define IOCONFIG_ORSOC_IO_BOARD
155			`define ETH_CLK
156			`define ACTEL_PLL_CLKA_PERIOD 40 // 25 MHz
157			`define ACTEL_PLL_CLKB_PERIOD 50 // 20 MHz
158			`define ACTEL_PLL_CLKC_PERIOD 20.83334 // 48 MHz
159			`define BOARD_CLOCK_PERIOD 40 // 25 MHz
160			// Modules in system (or `define CUSTOM_CONFIG and define below)
161			// `define CUSTOM_MODULES_CONFIG
162			`// Included modules: define to include`
163			`define JTAG_DEBUG
164			`define VERSATILE_SDRAM
165			`define UART0
166			`define SPI0
167			`define I2C0
168			`define GPIO0
169			`define ETH0
170			`define SMII0
171			`endif
172
173			`ifdef CUSTOM_MODULES_CONFIG
174			`// Included modules: define to include`
175			`define JTAG_DEBUG
176			`define VERSATILE_SDRAM
177			//`define RAM_WB
178			//`define ACTEL_UFR
179			`define UART0
180			`define SPI0
181			// `define SPI1
182			// `define SPI2
183			// `define I2C0
184			// `define I2C1
185			// `define I2C2
186			// `define I2C3
187			// `define USB0
188			// `define USB1
189			//`define GPIO0
190			`define ETH0
191			`define SMII0
192
193			`endif // `ifdef CUSTOM_MODULES_CONFIG
194
195
196			`// end of included module defines - keep this comment line here, scripts depend on it!!`
197
198			`ifdef SPI0
199			`define SPI0_SLAVE_SELECTS
200			`endif
201
202
203			`ifdef SPI1
204			`define SPI1_SLAVE_SELECTS
205			`endif
206
207			`ifdef SPI2
208			`define SPI2_SLAVE_SELECTS
209			`endif
210
211			`ifdef USB0
212			`// Indicate we need clock for USB`
213			`define USB_CLK
214			`// uncomment this for the module to be only a host controller`
215			`define USB0_ONLY_HOST
216			`endif
217
218
219			`ifdef USB1
220			`// If we haven't already, indicate we need clock for USB`
221			`ifndef USB_CLK
222			`define USB_CLK
223			`endif
224
225			`// If both are commented out, USB1 is a host and slave otherwise uncomment`
226			`// only one of the following to instantiate the desired type:`
227			// `define USB1_ONLY_HOST
228			`define USB1_ONLY_SLAVE
229			`endif
230
231
232			`ifdef ETH0
233			`// Define ETH0_PHY_RST here or where ETH0 is defined to enable an active-low`
234			`// reset output to the PHY if it's possible.`
235			// `define ETH0_PHY_RST
236			`endif
237
238			`ifdef ETH_CLK
239			`// Ethernet clock rate, for simulation`
240			`define ETHERNET_CLOCK_PERIOD 8.00 // 125 MHz
241			`endif
242
243			`//`
244			`// Arbiter defines`
245			`//`
246
247			`// Uncomment to register things through arbiter (hopefully quicker design)`
248			`// Instruction bus arbiter`
249			//`define ARBITER_IBUS_REGISTERING
250			`define ARBITER_IBUS_WATCHDOG
251			`// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
252			`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
253
254			`// Data bus arbiter`
255
256			//`define ARBITER_DBUS_REGISTERING
257			`define ARBITER_DBUS_WATCHDOG
258			`// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
259			`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
260
261			`// Byte bus (peripheral bus) arbiter`
262			`// Don't really need the watchdog here - the databus will pick it up`
263			//`define ARBITER_BYTEBUS_WATCHDOG
264			`// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
265			`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
266