URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_controller_wb.v] - Blame information for rev 701

Go to most recent revision | Details | Compare with Previous | View Log


`include "sd_defines.v"
module sd_controller_wb(
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
 
  // WISHBONE slave
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
 
  // WISHBONE master
 
 
  we_m_tx_bd, new_cmd,
  we_m_rx_bd,
  we_ack, int_ack, cmd_int_busy,
  Bd_isr_reset,
  normal_isr_reset,
  error_isr_reset,
  int_busy,
  dat_in_m_tx_bd,
  dat_in_m_rx_bd,
  write_req_s,
  cmd_set_s,
  cmd_arg_s,
  argument_reg,
  cmd_setting_reg,
  status_reg,
  cmd_resp_1,
  software_reset_reg,
  time_out_reg,
  normal_int_status_reg,
  error_int_status_reg,
  normal_int_signal_enable_reg,
  error_int_signal_enable_reg,
  clock_divider,
  Bd_Status_reg,
  Bd_isr_reg,
  Bd_isr_enable_reg
  );
 
  // WISHBONE common
input           wb_clk_i;     // WISHBONE clock
input           wb_rst_i;     // WISHBONE reset
input   [31:0]  wb_dat_i;     // WISHBONE data input
output reg [31:0]  wb_dat_o;     // WISHBONE data output
     // WISHBONE error output
 
// WISHBONE slave
input   [7:0]  wb_adr_i;     // WISHBONE address input
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
input           wb_we_i;      // WISHBONE write enable input
input           wb_cyc_i;     // WISHBONE cycle input
input           wb_stb_i;     // WISHBONE strobe input
 
output reg         wb_ack_o;     // WISHBONE acknowledge output
 
 
 
output reg we_m_tx_bd;
 
output reg new_cmd;
output reg we_ack; //CMD acces granted 
output reg int_ack; //Internal Delayed Ack;
output reg cmd_int_busy;
 
output reg we_m_rx_bd; //Write enable Master side Rx_bd
  //Read enable Master side Rx_bd
output reg int_busy;
input write_req_s;
input wire [15:0] cmd_set_s;
input wire [31:0] cmd_arg_s;
 
 
//
`define SUPPLY_VOLTAGE_3_3
`define SD_CARD_2_0
 
//Register Addreses 
`define argument 8'h00
`define command 8'h04
`define status 8'h08
`define resp1 8'h0c
`define controller 8'h1c
`define block 8'h20
`define power 8'h24
`define software 8'h28
`define timeout 8'h2c
`define normal_isr 8'h30
`define error_isr 8'h34
`define normal_iser 8'h38
`define error_iser 8'h3c
`define capa 8'h48
`define clock_d 8'h4c
`define bd_status 8'h50
`define bd_isr 8'h54
`define bd_iser 8'h58
`define bd_rx 8'h60
`define bd_tx 8'h80
 
 
 
`ifdef SUPPLY_VOLTAGE_3_3
   parameter power_controll_reg  = 8'b0000_111_1;
`elsif SUPPLY_VOLTAGE_3_0
   parameter power_controll_reg  = 8'b0000_110_1;
`elsif SUPPLY_VOLTAGE_1_8
   parameter power_controll_reg  = 8'b0000_101_1;
`endif
 
parameter block_size_reg = `BLOCK_SIZE ; //512-Bytes
 
`ifdef SD_BUS_WIDTH_4
     parameter controll_setting_reg =16'b0000_0000_0000_0010;
`else
     parameter controll_setting_reg =16'b0000_0000_0000_0000;
`endif
     parameter capabilies_reg =16'b0000_0000_0000_0000;
 
//Buss accessible registers    
output reg [31:0] argument_reg;
output reg [15:0] cmd_setting_reg;
input  wire [15:0] status_reg;
input wire [31:0] cmd_resp_1;
output reg [7:0] software_reset_reg;
output reg [15:0] time_out_reg;
input wire [15:0]normal_int_status_reg;
input wire [15:0]error_int_status_reg;
output reg [15:0]normal_int_signal_enable_reg;
output reg [15:0]error_int_signal_enable_reg;
output reg [7:0] clock_divider;
input  wire [15:0] Bd_Status_reg;
input  wire [7:0] Bd_isr_reg;
output reg [7:0] Bd_isr_enable_reg;
 
//Register Controll
output reg Bd_isr_reset;
output reg normal_isr_reset;
output reg error_isr_reset;
output reg [`RAM_MEM_WIDTH-1:0] dat_in_m_rx_bd; //Data in to Rx_bd from Master
output reg [`RAM_MEM_WIDTH-1:0] dat_in_m_tx_bd;
 
 
//internal reg
reg [1:0] we;
 
 
always @(posedge wb_clk_i or posedge wb_rst_i)
        begin
          we_m_rx_bd <= 0;
        we_m_tx_bd <= 0;
          new_cmd<= 1'b0 ;
          we_ack <= 0;
          int_ack =  1;
          cmd_int_busy<=0;
     if ( wb_rst_i )begin
            argument_reg <=0;
      cmd_setting_reg <= 0;
            software_reset_reg <= 0;
            time_out_reg <= 0;
            normal_int_signal_enable_reg <= 0;
            error_int_signal_enable_reg <= 0;
            clock_divider <=`RESET_CLK_DIV;
            int_ack=1 ;
            we<=0;
            int_busy <=0;
            we_ack <=0;
            wb_ack_o=0;
            cmd_int_busy<=0;
            Bd_isr_reset<=0;
            dat_in_m_tx_bd<=0;
            dat_in_m_rx_bd<=0;
            Bd_isr_enable_reg<=0;
            normal_isr_reset<=0;
            error_isr_reset<=0;
          end
          else if ((wb_stb_i  & wb_cyc_i) || wb_ack_o )begin
            Bd_isr_reset<=0;
             normal_isr_reset<=  0;
            error_isr_reset<=  0;
            if (wb_we_i) begin
              case (wb_adr_i)
                `argument: begin
                    argument_reg  <=  wb_dat_i;
                    new_cmd <=  1'b1 ;
                 end
                `command : begin
                    cmd_setting_reg  <=  wb_dat_i;
                    int_busy <= 1;
                end
          `software : software_reset_reg <=  wb_dat_i;
          `timeout : time_out_reg  <=  wb_dat_i;
          `normal_iser : normal_int_signal_enable_reg <=  wb_dat_i;
          `error_iser : error_int_signal_enable_reg  <=  wb_dat_i;
          `normal_isr : normal_isr_reset<=  1;
          `error_isr:  error_isr_reset<=  1;
                `clock_d: clock_divider  <=  wb_dat_i;
                `bd_isr: Bd_isr_reset<=  1;
                `bd_iser : Bd_isr_enable_reg <= wb_dat_i ;
                `ifdef RAM_MEM_WIDTH_32
                  `bd_rx: begin
                     we <= we+1;
                     we_m_rx_bd <= 1;
                     int_ack =  0;
                   if  (we[1:0]==2'b00)
                     we_m_rx_bd <= 0;
                   else if  (we[1:0]==2'b01)
                    dat_in_m_rx_bd <=  wb_dat_i;
                   else begin
                      int_ack =  1;
                      we<= 0;
                      we_m_rx_bd <= 0;
                    end
 
                end
                `bd_tx: begin
                   we <= we+1;
                   we_m_tx_bd <= 1;
                   int_ack =  0;
                   if  (we[1:0]==2'b00)
                     we_m_tx_bd <= 0;
                   else if  (we[1:0]==2'b01)
                    dat_in_m_tx_bd <=  wb_dat_i;
                   else begin
                     int_ack =  1;
                      we<= 0;
                      we_m_tx_bd <= 0;
                    end
                end
 
                `endif
                `ifdef RAM_MEM_WIDTH_16
                `bd_rx: begin
                     we <= we+1;
                     we_m_rx_bd <= 1;
                     int_ack =  0;
                   if  (we[1:0]==2'b00)
                     we_m_rx_bd <= 0;
                   else if  (we[1:0]==2'b01)
                    dat_in_m_rx_bd <=  wb_dat_i[15:0];
                   else if ( we[1:0]==2'b10)
                     dat_in_m_rx_bd <=  wb_dat_i[31:16];
                   else begin
                     int_ack =  1;
                      we<= 0;
                      we_m_rx_bd <= 0;
                    end
 
                end
                `bd_tx: begin
                   we <= we+1;
                   we_m_tx_bd <= 1;
                   int_ack =  0;
                   if  (we[1:0]==2'b00)
                     we_m_tx_bd <= 0;
                   else if  (we[1:0]==2'b01)
                    dat_in_m_tx_bd <=  wb_dat_i[15:0];
                   else if ( we[1:0]==2'b10)
                     dat_in_m_tx_bd <=  wb_dat_i[31:16];
                   else begin
                     int_ack =  1;
                      we<= 0;
                      we_m_tx_bd <= 0;
                    end
                end
                `endif
 
              endcase
            end
        wb_ack_o =   wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;
         end
            else if (write_req_s) begin
               new_cmd <=  1'b1 ;
               cmd_setting_reg <=   cmd_set_s;
               argument_reg  <=  cmd_arg_s ;
               cmd_int_busy<=  1;
               we_ack <= 1;
            end
 
         if (status_reg[0])
            int_busy <=  0;
 
        //wb_ack_o =   wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack; 
end
 
always @(posedge wb_clk_i )begin
   if (wb_stb_i  & wb_cyc_i) begin //CS
      case (wb_adr_i)
                 `argument:  wb_dat_o  <=   argument_reg ;
                 `command : wb_dat_o <=  cmd_setting_reg ;
                 `status : wb_dat_o <=  status_reg ;
           `resp1 : wb_dat_o <=  cmd_resp_1 ;
 
           `controller : wb_dat_o <=  controll_setting_reg ;
           `block :  wb_dat_o <=  block_size_reg ;
           `power : wb_dat_o <=  power_controll_reg ;
           `software : wb_dat_o  <=  software_reset_reg ;
           `timeout : wb_dat_o  <=  time_out_reg ;
           `normal_isr : wb_dat_o <=  normal_int_status_reg ;
           `error_isr : wb_dat_o  <=  error_int_status_reg ;
           `normal_iser : wb_dat_o <=  normal_int_signal_enable_reg ;
           `error_iser : wb_dat_o  <=  error_int_signal_enable_reg ;
            `clock_d : wb_dat_o  <= clock_divider;
                 `capa  : wb_dat_o  <=  capabilies_reg ;
                 `bd_status : wb_dat_o  <=  Bd_Status_reg;
                 `bd_isr : wb_dat_o  <=  Bd_isr_reg ;
                 `bd_iser : wb_dat_o  <=  Bd_isr_enable_reg ;
            endcase
          end
end
 
 
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_controller_wb.v] - Blame information for rev 701

Line No.	Rev	Author	Line
1	544	julius	`include "sd_defines.v"
2			`module sd_controller_wb(`
3			`wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,`
4
5			`// WISHBONE slave`
6			`wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,`
7
8			`// WISHBONE master`
9
10
11			`we_m_tx_bd, new_cmd,`
12			`we_m_rx_bd,`
13			`we_ack, int_ack, cmd_int_busy,`
14			`Bd_isr_reset,`
15			`normal_isr_reset,`
16			`error_isr_reset,`
17			`int_busy,`
18			`dat_in_m_tx_bd,`
19			`dat_in_m_rx_bd,`
20			`write_req_s,`
21			`cmd_set_s,`
22			`cmd_arg_s,`
23			`argument_reg,`
24			`cmd_setting_reg,`
25			`status_reg,`
26			`cmd_resp_1,`
27			`software_reset_reg,`
28			`time_out_reg,`
29			`normal_int_status_reg,`
30			`error_int_status_reg,`
31			`normal_int_signal_enable_reg,`
32			`error_int_signal_enable_reg,`
33			`clock_divider,`
34			`Bd_Status_reg,`
35			`Bd_isr_reg,`
36			`Bd_isr_enable_reg`
37			`);`
38
39			`// WISHBONE common`
40			`input wb_clk_i; // WISHBONE clock`
41			`input wb_rst_i; // WISHBONE reset`
42			`input [31:0] wb_dat_i; // WISHBONE data input`
43			`output reg [31:0] wb_dat_o; // WISHBONE data output`
44			`// WISHBONE error output`
45
46			`// WISHBONE slave`
47			`input [7:0] wb_adr_i; // WISHBONE address input`
48			`input [3:0] wb_sel_i; // WISHBONE byte select input`
49			`input wb_we_i; // WISHBONE write enable input`
50			`input wb_cyc_i; // WISHBONE cycle input`
51			`input wb_stb_i; // WISHBONE strobe input`
52
53			`output reg wb_ack_o; // WISHBONE acknowledge output`
54
55
56
57			`output reg we_m_tx_bd;`
58
59			`output reg new_cmd;`
60			`output reg we_ack; //CMD acces granted`
61			`output reg int_ack; //Internal Delayed Ack;`
62			`output reg cmd_int_busy;`
63
64			`output reg we_m_rx_bd; //Write enable Master side Rx_bd`
65			`//Read enable Master side Rx_bd`
66			`output reg int_busy;`
67			`input write_req_s;`
68			`input wire [15:0] cmd_set_s;`
69			`input wire [31:0] cmd_arg_s;`
70
71
72			`//`
73			`define SUPPLY_VOLTAGE_3_3
74			`define SD_CARD_2_0
75
76			`//Register Addreses`
77			`define argument 8'h00
78			`define command 8'h04
79			`define status 8'h08
80			`define resp1 8'h0c
81			`define controller 8'h1c
82			`define block 8'h20
83			`define power 8'h24
84			`define software 8'h28
85			`define timeout 8'h2c
86			`define normal_isr 8'h30
87			`define error_isr 8'h34
88			`define normal_iser 8'h38
89			`define error_iser 8'h3c
90			`define capa 8'h48
91			`define clock_d 8'h4c
92			`define bd_status 8'h50
93			`define bd_isr 8'h54
94			`define bd_iser 8'h58
95			`define bd_rx 8'h60
96			`define bd_tx 8'h80
97
98
99
100			`ifdef SUPPLY_VOLTAGE_3_3
101			`parameter power_controll_reg = 8'b0000_111_1;`
102			`elsif SUPPLY_VOLTAGE_3_0
103			`parameter power_controll_reg = 8'b0000_110_1;`
104			`elsif SUPPLY_VOLTAGE_1_8
105			`parameter power_controll_reg = 8'b0000_101_1;`
106			`endif
107
108			parameter block_size_reg = `BLOCK_SIZE ; //512-Bytes
109
110			`ifdef SD_BUS_WIDTH_4
111			`parameter controll_setting_reg =16'b0000_0000_0000_0010;`
112			`else
113			`parameter controll_setting_reg =16'b0000_0000_0000_0000;`
114			`endif
115			`parameter capabilies_reg =16'b0000_0000_0000_0000;`
116
117			`//Buss accessible registers`
118			`output reg [31:0] argument_reg;`
119			`output reg [15:0] cmd_setting_reg;`
120			`input wire [15:0] status_reg;`
121			`input wire [31:0] cmd_resp_1;`
122			`output reg [7:0] software_reset_reg;`
123			`output reg [15:0] time_out_reg;`
124			`input wire [15:0]normal_int_status_reg;`
125			`input wire [15:0]error_int_status_reg;`
126			`output reg [15:0]normal_int_signal_enable_reg;`
127			`output reg [15:0]error_int_signal_enable_reg;`
128			`output reg [7:0] clock_divider;`
129			`input wire [15:0] Bd_Status_reg;`
130			`input wire [7:0] Bd_isr_reg;`
131			`output reg [7:0] Bd_isr_enable_reg;`
132
133			`//Register Controll`
134			`output reg Bd_isr_reset;`
135			`output reg normal_isr_reset;`
136			`output reg error_isr_reset;`
137			output reg [`RAM_MEM_WIDTH-1:0] dat_in_m_rx_bd; //Data in to Rx_bd from Master
138			output reg [`RAM_MEM_WIDTH-1:0] dat_in_m_tx_bd;
139
140
141			`//internal reg`
142			`reg [1:0] we;`
143
144
145			`always @(posedge wb_clk_i or posedge wb_rst_i)`
146			`begin`
147			`we_m_rx_bd <= 0;`
148			`we_m_tx_bd <= 0;`
149			`new_cmd<= 1'b0 ;`
150			`we_ack <= 0;`
151			`int_ack = 1;`
152			`cmd_int_busy<=0;`
153			`if ( wb_rst_i )begin`
154			`argument_reg <=0;`
155			`cmd_setting_reg <= 0;`
156			`software_reset_reg <= 0;`
157			`time_out_reg <= 0;`
158			`normal_int_signal_enable_reg <= 0;`
159			`error_int_signal_enable_reg <= 0;`
160			clock_divider <=`RESET_CLK_DIV;
161			`int_ack=1 ;`
162			`we<=0;`
163			`int_busy <=0;`
164			`we_ack <=0;`
165			`wb_ack_o=0;`
166			`cmd_int_busy<=0;`
167			`Bd_isr_reset<=0;`
168			`dat_in_m_tx_bd<=0;`
169			`dat_in_m_rx_bd<=0;`
170			`Bd_isr_enable_reg<=0;`
171			`normal_isr_reset<=0;`
172			`error_isr_reset<=0;`
173			`end`
174			`else if ((wb_stb_i & wb_cyc_i) \|\| wb_ack_o )begin`
175			`Bd_isr_reset<=0;`
176			`normal_isr_reset<= 0;`
177			`error_isr_reset<= 0;`
178			`if (wb_we_i) begin`
179			`case (wb_adr_i)`
180			`argument: begin
181			`argument_reg <= wb_dat_i;`
182			`new_cmd <= 1'b1 ;`
183			`end`
184			`command : begin
185			`cmd_setting_reg <= wb_dat_i;`
186			`int_busy <= 1;`
187			`end`
188			`software : software_reset_reg <= wb_dat_i;
189			`timeout : time_out_reg <= wb_dat_i;
190			`normal_iser : normal_int_signal_enable_reg <= wb_dat_i;
191			`error_iser : error_int_signal_enable_reg <= wb_dat_i;
192			`normal_isr : normal_isr_reset<= 1;
193			`error_isr: error_isr_reset<= 1;
194			`clock_d: clock_divider <= wb_dat_i;
195			`bd_isr: Bd_isr_reset<= 1;
196			`bd_iser : Bd_isr_enable_reg <= wb_dat_i ;
197			`ifdef RAM_MEM_WIDTH_32
198			`bd_rx: begin
199			`we <= we+1;`
200			`we_m_rx_bd <= 1;`
201			`int_ack = 0;`
202			`if (we[1:0]==2'b00)`
203			`we_m_rx_bd <= 0;`
204			`else if (we[1:0]==2'b01)`
205			`dat_in_m_rx_bd <= wb_dat_i;`
206			`else begin`
207			`int_ack = 1;`
208			`we<= 0;`
209			`we_m_rx_bd <= 0;`
210			`end`
211
212			`end`
213			`bd_tx: begin
214			`we <= we+1;`
215			`we_m_tx_bd <= 1;`
216			`int_ack = 0;`
217			`if (we[1:0]==2'b00)`
218			`we_m_tx_bd <= 0;`
219			`else if (we[1:0]==2'b01)`
220			`dat_in_m_tx_bd <= wb_dat_i;`
221			`else begin`
222			`int_ack = 1;`
223			`we<= 0;`
224			`we_m_tx_bd <= 0;`
225			`end`
226			`end`
227
228			`endif
229			`ifdef RAM_MEM_WIDTH_16
230			`bd_rx: begin
231			`we <= we+1;`
232			`we_m_rx_bd <= 1;`
233			`int_ack = 0;`
234			`if (we[1:0]==2'b00)`
235			`we_m_rx_bd <= 0;`
236			`else if (we[1:0]==2'b01)`
237			`dat_in_m_rx_bd <= wb_dat_i[15:0];`
238			`else if ( we[1:0]==2'b10)`
239			`dat_in_m_rx_bd <= wb_dat_i[31:16];`
240			`else begin`
241			`int_ack = 1;`
242			`we<= 0;`
243			`we_m_rx_bd <= 0;`
244			`end`
245
246			`end`
247			`bd_tx: begin
248			`we <= we+1;`
249			`we_m_tx_bd <= 1;`
250			`int_ack = 0;`
251			`if (we[1:0]==2'b00)`
252			`we_m_tx_bd <= 0;`
253			`else if (we[1:0]==2'b01)`
254			`dat_in_m_tx_bd <= wb_dat_i[15:0];`
255			`else if ( we[1:0]==2'b10)`
256			`dat_in_m_tx_bd <= wb_dat_i[31:16];`
257			`else begin`
258			`int_ack = 1;`
259			`we<= 0;`
260			`we_m_tx_bd <= 0;`
261			`end`
262			`end`
263			`endif
264
265			`endcase`
266			`end`
267			`wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;`
268			`end`
269			`else if (write_req_s) begin`
270			`new_cmd <= 1'b1 ;`
271			`cmd_setting_reg <= cmd_set_s;`
272			`argument_reg <= cmd_arg_s ;`
273			`cmd_int_busy<= 1;`
274			`we_ack <= 1;`
275			`end`
276
277			`if (status_reg[0])`
278			`int_busy <= 0;`
279
280			`//wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;`
281			`end`
282
283			`always @(posedge wb_clk_i )begin`
284			`if (wb_stb_i & wb_cyc_i) begin //CS`
285			`case (wb_adr_i)`
286			`argument: wb_dat_o <= argument_reg ;
287			`command : wb_dat_o <= cmd_setting_reg ;
288			`status : wb_dat_o <= status_reg ;
289			`resp1 : wb_dat_o <= cmd_resp_1 ;
290
291			`controller : wb_dat_o <= controll_setting_reg ;
292			`block : wb_dat_o <= block_size_reg ;
293			`power : wb_dat_o <= power_controll_reg ;
294			`software : wb_dat_o <= software_reset_reg ;
295			`timeout : wb_dat_o <= time_out_reg ;
296			`normal_isr : wb_dat_o <= normal_int_status_reg ;
297			`error_isr : wb_dat_o <= error_int_status_reg ;
298			`normal_iser : wb_dat_o <= normal_int_signal_enable_reg ;
299			`error_iser : wb_dat_o <= error_int_signal_enable_reg ;
300			`clock_d : wb_dat_o <= clock_divider;
301			`capa : wb_dat_o <= capabilies_reg ;
302			`bd_status : wb_dat_o <= Bd_Status_reg;
303			`bd_isr : wb_dat_o <= Bd_isr_reg ;
304			`bd_iser : wb_dat_o <= Bd_isr_enable_reg ;
305			`endcase`
306			`end`
307			`end`
308
309
310
311			`endmodule`