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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 412

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// orpsoc-defines                                               ////
////                                                              ////
//// Top level ORPSoC defines file                                ////
////                                                              ////
//// Included in toplevel and testbench                           ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
// Uncomment a `define BOARD_XYZ to configure design RTL for it.
//
// Mainly presets are for internal frequency settings, and what
// external oscillator is expected (ordb1's were made with various
// XTALs.)
//
//////////////////////////////////////////////////////////////////////
 
 `define XILINX
 `define XILINX_PLL
 `define FPGA_BOARD_XILINX_ML501
 `define IOCONFIG_XILINX_ML501
 `define BOARD_CLOCK_PERIOD 5000 // 200MHz (pS accuracy for Xilinx sims.) 
 
 `define JTAG_DEBUG
// `define RAM_WB
// `define XILINX_SSRAM
 `define XILINX_DDR2
 `define UART0
 `define GPIO0
 `define SPI0
 `define I2C0
 `define I2C1
 `define ETH0
 `define ETH0_PHY_RST
 
// end of included module defines - keep this comment line here, scripts depend on it!!
 
 
//
// Arbiter defines
//
 
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
 
// Data bus arbiter
 
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
 

Line No.	Rev	Author	Line
1	412	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// orpsoc-defines ////`
4			`//// ////`
5			`//// Top level ORPSoC defines file ////`
6			`//// ////`
7			`//// Included in toplevel and testbench ////`
8			`//// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//`
37			// Uncomment a `define BOARD_XYZ to configure design RTL for it.
38			`//`
39			`// Mainly presets are for internal frequency settings, and what`
40			`// external oscillator is expected (ordb1's were made with various`
41			`// XTALs.)`
42			`//`
43			`//////////////////////////////////////////////////////////////////////`
44
45			`define XILINX
46			`define XILINX_PLL
47			`define FPGA_BOARD_XILINX_ML501
48			`define IOCONFIG_XILINX_ML501
49			`define BOARD_CLOCK_PERIOD 5000 // 200MHz (pS accuracy for Xilinx sims.)
50
51			`define JTAG_DEBUG
52			// `define RAM_WB
53			// `define XILINX_SSRAM
54			`define XILINX_DDR2
55			`define UART0
56			`define GPIO0
57			`define SPI0
58			`define I2C0
59			`define I2C1
60			`define ETH0
61			`define ETH0_PHY_RST
62
63			`// end of included module defines - keep this comment line here, scripts depend on it!!`
64
65
66			`//`
67			`// Arbiter defines`
68			`//`
69
70			`// Uncomment to register things through arbiter (hopefully quicker design)`
71			`// Instruction bus arbiter`
72			//`define ARBITER_IBUS_REGISTERING
73			`define ARBITER_IBUS_WATCHDOG
74			`// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
75			`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
76
77			`// Data bus arbiter`
78
79			//`define ARBITER_DBUS_REGISTERING
80			`define ARBITER_DBUS_WATCHDOG
81			`// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
82			`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
83
84			`// Byte bus (peripheral bus) arbiter`
85			`// Don't really need the watchdog here - the databus will pick it up`
86			//`define ARBITER_BYTEBUS_WATCHDOG
87			`// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
88			`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
89

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 412