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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [bench/] [verilog/] [include/] [ddr2_model_parameters.v] - Blame information for rev 570

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1 568 julius 
/****************************************************************************************
2 
*
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*   Disclaimer   This software code and all associated documentation, comments or other
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*  of Warranty:  information (collectively "Software") is provided "AS IS" without
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*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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*                DAMAGES. Because some jurisdictions prohibit the exclusion or
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*                limitation of liability for consequential or incidental damages, the
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*                above limitation may not apply to you.
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*
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*                Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
27 
 
28 
    // Parameters current with 512Mb datasheet rev N
29 
 
30 
    // Timing parameters based on Speed Grade
31 
 
32 
                                          // SYMBOL UNITS DESCRIPTION
33 
//`define sg37E
34 
`define x16
35 
 
36 
`ifdef sg37E
37 
    parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
38 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
39 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
40 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
41 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
42 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
43 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
44 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
45 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
46 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
47 
    parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
48 
    parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
49 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
50 
    parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
51 
    parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
52 
    parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
53 
    parameter TIS              =     250; // tIS    ps    Input Setup Time
54 
    parameter TIH              =     375; // tIH    ps    Input Hold Time
55 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
56 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
57 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
58 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
59 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
60 
    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
61 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
62 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
63 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
64 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
65 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
66 
`else                                          // ------ ----- -----------
67 
`ifdef sg187E
68 
    parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
69 
    parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
70 
    parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
71 
    parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
72 
    parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
73 
    parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
74 
    parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
75 
    parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
76 
    parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
77 
    parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
78 
    parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
79 
    parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
80 
    parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
81 
    parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
82 
    parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
83 
    parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
84 
    parameter TIS              =     125; // tIS    ps    Input Setup Time
85 
    parameter TIH              =     200; // tIH    ps    Input Hold Time
86 
    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
87 
    parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
88 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
89 
    parameter TRP              =   13125; // tRP    ps    Precharge command period
90 
    parameter TRPA             =   13125; // tRPA   ps    Precharge All period
91 
    parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
92 
    parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
93 
    parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
94 
    parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
95 
    parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
96 
    parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
97 
`else `ifdef sg25E
98 
    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
99 
    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
100 
    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
101 
    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
102 
    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
103 
    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
104 
    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
105 
    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
106 
    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
107 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
108 
    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
109 
    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
110 
    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
111 
    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
112 
    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
113 
    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
114 
    parameter TIS              =     175; // tIS    ps    Input Setup Time
115 
    parameter TIH              =     250; // tIH    ps    Input Hold Time
116 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
117 
    parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
118 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
119 
    parameter TRP              =   12500; // tRP    ps    Precharge command period
120 
    parameter TRPA             =   12500; // tRPA   ps    Precharge All period
121 
    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
122 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
123 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
124 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
125 
    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
126 
    parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
127 
`else `ifdef sg25
128 
    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
129 
    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
130 
    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
131 
    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
132 
    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
133 
    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
134 
    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
135 
    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
136 
    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
137 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
138 
    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
139 
    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
140 
    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
141 
    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
142 
    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
143 
    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
144 
    parameter TIS              =     175; // tIS    ps    Input Setup Time
145 
    parameter TIH              =     250; // tIH    ps    Input Hold Time
146 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
147 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
148 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
149 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
150 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
151 
    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
152 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
153 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
154 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
155 
    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
156 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
157 
`else `ifdef sg3E
158 
    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
159 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
160 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
161 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
162 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
163 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
164 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
165 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
166 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
167 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
168 
    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
169 
    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
170 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
171 
    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
172 
    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
173 
    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
174 
    parameter TIS              =     200; // tIS    ps    Input Setup Time
175 
    parameter TIH              =     275; // tIH    ps    Input Hold Time
176 
    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
177 
    parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
178 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
179 
    parameter TRP              =   12000; // tRP    ps    Precharge command period
180 
    parameter TRPA             =   12000; // tRPA   ps    Precharge All period
181 
    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
182 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
183 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
184 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
185 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
186 
    parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
187 
`else `ifdef sg3
188 
    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
189 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
190 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
191 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
192 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
193 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
194 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
195 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
196 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
197 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
198 
    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
199 
    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
200 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
201 
    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
202 
    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
203 
    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
204 
    parameter TIS              =     200; // tIS    ps    Input Setup Time
205 
    parameter TIH              =     275; // tIH    ps    Input Hold Time
206 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
207 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
208 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
209 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
210 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
211 
    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
212 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
213 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
214 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
215 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
216 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
217 
`else `define sg5E
218 
    parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
219 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
220 
    parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
221 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
222 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
223 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
224 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
225 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
226 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
227 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
228 
    parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
229 
    parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
230 
    parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
231 
    parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
232 
    parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
233 
    parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
234 
    parameter TIS              =     350; // tIS    ps    Input Setup Time
235 
    parameter TIH              =     475; // tIH    ps    Input Hold Time
236 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
237 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
238 
    parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
239 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
240 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
241 
    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
242 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
243 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
244 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
245 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
246 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
247 
`endif `endif `endif `endif `endif `endif
248 
 
249 
`ifdef x16
250 
  `ifdef sg187E
251 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
252 
  `else `ifdef sg25E
253 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
254 
  `else `ifdef sg25
255 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
256 
  `else // sg3E, sg3, sg37E, sg5E
257 
    parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
258 
  `endif `endif `endif
259 
`else // x4, x8
260 
  `ifdef sg187E
261 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
262 
  `else `ifdef sg25E
263 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
264 
  `else `ifdef sg25
265 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
266 
  `else // sg3E, sg3, sg37E, sg5E
267 
    parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
268 
  `endif `endif `endif
269 
`endif
270 
 
271 
    // Timing Parameters
272 
 
273 
    // Mode Register
274 
    parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
275 
    parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
276 
    parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
277 
    parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
278 
    parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
279 
    parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
280 
    parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
281 
    parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
282 
    // Clock
283 
    parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
284 
    parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
285 
    parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
286 
    parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
287 
    parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
288 
    // Data
289 
    parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
290 
    parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
291 
    parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
292 
    // Data Strobe
293 
    parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
294 
    parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
295 
    parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
296 
    parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
297 
    parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
298 
    parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
299 
    parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
300 
    // Command and Address
301 
    parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
302 
    parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
303 
    parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
304 
    parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
305 
    parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
306 
    parameter TWR              =   15000; // tWR    ps    Write recovery time
307 
    parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
308 
    parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
309 
    // Refresh
310 
    parameter TRFC_MIN         =  105000; // tRFC   ps    Refresh to Refresh Command interval minimum value
311 
    parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
312 
    // Self Refresh
313 
    parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
314 
    parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
315 
    parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
316 
    // ODT
317 
    parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
318 
    parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
319 
    parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
320 
    parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
321 
    parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
322 
    // Power Down
323 
    parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
324 
 
325 
    // Size Parameters based on Part Width
326 
 
327 
`ifdef x4
328 
    parameter ADDR_BITS        =      14; // Address Bits
329 
    parameter ROW_BITS         =      14; // Number of Address bits
330 
    parameter COL_BITS         =      11; // Number of Column bits
331 
    parameter DM_BITS          =       1; // Number of Data Mask bits
332 
    parameter DQ_BITS          =       4; // Number of Data bits
333 
    parameter DQS_BITS         =       1; // Number of Dqs bits
334 
    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
335 
`else `ifdef x8
336 
    parameter ADDR_BITS        =      14; // Address Bits
337 
    parameter ROW_BITS         =      14; // Number of Address bits
338 
    parameter COL_BITS         =      10; // Number of Column bits
339 
    parameter DM_BITS          =       1; // Number of Data Mask bits
340 
    parameter DQ_BITS          =       8; // Number of Data bits
341 
    parameter DQS_BITS         =       1; // Number of Dqs bits
342 
    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
343 
`else `define x16
344 
    parameter ADDR_BITS        =      13; // Address Bits
345 
    parameter ROW_BITS         =      13; // Number of Address bits
346 
    parameter COL_BITS         =      10; // Number of Column bits
347 
    parameter DM_BITS          =       2; // Number of Data Mask bits
348 
    parameter DQ_BITS          =      16; // Number of Data bits
349 
    parameter DQS_BITS         =       2; // Number of Dqs bits
350 
    parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
351 
`endif `endif
352 
 
353 
`ifdef QUAD_RANK
354 
    `define DUAL_RANK // also define DUAL_RANK
355 
    parameter CS_BITS          =       4; // Number of Chip Select Bits
356 
    parameter RANKS            =       4; // Number of Chip Select Bits
357 
`else `ifdef DUAL_RANK
358 
    parameter CS_BITS          =       2; // Number of Chip Select Bits
359 
    parameter RANKS            =       2; // Number of Chip Select Bits
360 
`else
361 
    parameter CS_BITS          =       2; // Number of Chip Select Bits
362 
    parameter RANKS            =       1; // Number of Chip Select Bits
363 
`endif `endif
364 
 
365 
    // Size Parameters
366 
    parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
367 
// if MEM_BITS== 14, a DQ=16 each part, DQ=64 total (4 parts) => 1MB total (256KB each)
368 
// if MEM_BITS== 15, a DQ=16 each part, DQ=64 total (4 parts) => 2MB total (512KB each)
369 
// if MEM_BITS== 16, a DQ=16 each part, DQ=64 total (4 parts) => 4MB total (1MB each)
370 
// if MEM_BITS== 17, a DQ=16 each part, DQ=64 total (4 parts) => 8MB total (2MB each)
371 
//parameter MEM_BITS         =      14; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
372 
   parameter MEM_BITS         =      17; // Number of write data bursts can be stored in memory.
373 
    parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
374 
    parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
375 
    parameter BO_BITS          =       2; // the number of Burst Order Bits
376 
 
377 
    // Simulation parameters
378 
    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
379 
    parameter DEBUG            =       0; // Turn on Debug messages
380 
    parameter BUS_DELAY        =       0; // delay in nanoseconds
381 
    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
382 
    parameter RANDOM_SEED      = 711689044; //seed value for random generator.
383 
 
384 
    parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
385 
    parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
386 
    parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
387 
    parameter RDQS_PST         =       1; // DQS low time after last valid read strobe
388 
    parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
389 
    parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
390 
    parameter WDQS_PRE         =       1; // DQS half clock periods prior to first write strobe
391 
    parameter WDQS_PST         =       1; // DQS half clock periods after last valid write strobe

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