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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_du.v] - Blame information for rev 815

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1 350 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/project,or1k                       ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
//
45 
// $Log: or1200_du.v,v $
46 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47 
// Minor update:
48 
// Bugs fixed.
49 
 
50 
// synopsys translate_off
51 
`include "timescale.v"
52 
// synopsys translate_on
53 
`include "or1200_defines.v"
54 
 
55 
//
56 
// Debug unit
57 
//
58 
 
59 
module or1200_du(
60 
        // RISC Internal Interface
61 
        clk, rst,
62 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
63 
        dcpu_dat_dc, icpu_cycstb_i,
64 
        ex_freeze, branch_op, ex_insn, id_pc,
65 
        spr_dat_npc, rf_dataw,
66 
        du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
67 
        du_read, du_write, du_except_stop, du_hwbkpt,
68 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
69 
 
70 
        // External Debug Interface
71 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
72 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
73 
);
74 
 
75 
parameter dw = `OR1200_OPERAND_WIDTH;
76 
parameter aw = `OR1200_OPERAND_WIDTH;
77 
 
78 
//
79 
// I/O
80 
//
81 
 
82 
//
83 
// RISC Internal Interface
84 
//
85 
input                           clk;            // Clock
86 
input                           rst;            // Reset
87 
input                           dcpu_cycstb_i;  // LSU status
88 
input                           dcpu_we_i;      // LSU status
89 
input   [31:0]                   dcpu_adr_i;     // LSU addr
90 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
91 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
92 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
93 
input                           ex_freeze;      // EX stage freeze
94 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
95 
input   [dw-1:0]         ex_insn;        // EX insn
96 
input   [31:0]                   id_pc;          // insn fetch EA
97 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
98 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
99 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
100 
output  [24: 0]                  du_dmr1;
101 
output                          du_stall;       // Debug Unit Stall
102 
output  [aw-1:0]         du_addr;        // Debug Unit Address
103 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
104 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
105 
output                          du_read;        // Debug Unit Read Enable
106 
output                          du_write;       // Debug Unit Write Enable
107 
input   [13:0]                   du_except_stop; // Exception masked by DSR
108 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
109 
input                           spr_cs;         // SPR Chip Select
110 
input                           spr_write;      // SPR Read/Write
111 
input   [aw-1:0]         spr_addr;       // SPR Address
112 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
113 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
114 
 
115 
//
116 
// External Debug Interface
117 
//
118 
input                   dbg_stall_i;    // External Stall Input
119 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
120 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
121 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
122 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
123 
output                  dbg_bp_o;       // Breakpoint Output
124 
input                   dbg_stb_i;      // External Address/Data Strobe
125 
input                   dbg_we_i;       // External Write Enable
126 
input   [aw-1:0] dbg_adr_i;      // External Address Input
127 
input   [dw-1:0] dbg_dat_i;      // External Data Input
128 
output  [dw-1:0] dbg_dat_o;      // External Data Output
129 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
130 
reg     [dw-1:0] dbg_dat_o;      // External Data Output
131 
reg                     dbg_ack_o;      // External Data Acknowledge (not WB compatible)
132 
 
133 
 
134 
//
135 
// Some connections go directly from the CPU through DU to Debug I/F
136 
//
137 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
138 
assign dbg_lss_o = 4'b0000;
139 
 
140 
reg     [1:0]                    dbg_is_o;
141 
//
142 
// Show insn activity (temp, must be removed)
143 
//
144 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
145 
        if (rst == `OR1200_RST_VALUE)
146 350 julius 
                dbg_is_o <=  2'b00;
147 
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
148 
                dbg_is_o <=  ~dbg_is_o;
149 
`ifdef UNUSED
150 
assign dbg_is_o = 2'b00;
151 
`endif
152 
`else
153 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
154 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
155 
`endif
156 
assign dbg_wp_o = 11'b000_0000_0000;
157 
 
158 
//
159 
// Some connections go directly from Debug I/F through DU to the CPU
160 
//
161 
assign du_stall = dbg_stall_i;
162 
assign du_addr = dbg_adr_i;
163 
assign du_dat_o = dbg_dat_i;
164 
assign du_read = dbg_stb_i && !dbg_we_i;
165 
assign du_write = dbg_stb_i && dbg_we_i;
166 
 
167 
reg                             dbg_ack;
168 
//
169 
// Generate acknowledge -- just delay stb signal
170 
//
171 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
172 
        if (rst == `OR1200_RST_VALUE) begin
173 350 julius 
                dbg_ack   <=  1'b0;
174 
                dbg_ack_o <=  1'b0;
175 
        end
176 
        else begin
177 
                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i
178 
                dbg_ack_o <=  dbg_ack & dbg_stb_i;      // valid when dbg_dat_o
179 
        end
180 
end
181 
 
182 
//
183 
// Register data output
184 
//
185 
always @(posedge clk)
186 
    dbg_dat_o <=  du_dat_i;
187 
 
188 
`ifdef OR1200_DU_IMPLEMENTED
189 
 
190 
//
191 
// Debug Mode Register 1
192 
//
193 
`ifdef OR1200_DU_DMR1
194 
reg     [24:0]                   dmr1;           // DMR1 implemented
195 
`else
196 
wire    [24:0]                   dmr1;           // DMR1 not implemented
197 
`endif
198 
assign du_dmr1 = dmr1;
199 
 
200 
//
201 
// Debug Mode Register 2
202 
//
203 
`ifdef OR1200_DU_DMR2
204 
reg     [23:0]                   dmr2;           // DMR2 implemented
205 
`else
206 
wire    [23:0]                   dmr2;           // DMR2 not implemented
207 
`endif
208 
 
209 
//
210 
// Debug Stop Register
211 
//
212 
`ifdef OR1200_DU_DSR
213 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
214 
`else
215 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
216 
`endif
217 
 
218 
//
219 
// Debug Reason Register
220 
//
221 
`ifdef OR1200_DU_DRR
222 
reg     [13:0]                   drr;            // DRR implemented
223 
`else
224 
wire    [13:0]                   drr;            // DRR not implemented
225 
`endif
226 
 
227 
//
228 
// Debug Value Register N
229 
//
230 
`ifdef OR1200_DU_DVR0
231 
reg     [31:0]                   dvr0;
232 
`else
233 
wire    [31:0]                   dvr0;
234 
`endif
235 
 
236 
//
237 
// Debug Value Register N
238 
//
239 
`ifdef OR1200_DU_DVR1
240 
reg     [31:0]                   dvr1;
241 
`else
242 
wire    [31:0]                   dvr1;
243 
`endif
244 
 
245 
//
246 
// Debug Value Register N
247 
//
248 
`ifdef OR1200_DU_DVR2
249 
reg     [31:0]                   dvr2;
250 
`else
251 
wire    [31:0]                   dvr2;
252 
`endif
253 
 
254 
//
255 
// Debug Value Register N
256 
//
257 
`ifdef OR1200_DU_DVR3
258 
reg     [31:0]                   dvr3;
259 
`else
260 
wire    [31:0]                   dvr3;
261 
`endif
262 
 
263 
//
264 
// Debug Value Register N
265 
//
266 
`ifdef OR1200_DU_DVR4
267 
reg     [31:0]                   dvr4;
268 
`else
269 
wire    [31:0]                   dvr4;
270 
`endif
271 
 
272 
//
273 
// Debug Value Register N
274 
//
275 
`ifdef OR1200_DU_DVR5
276 
reg     [31:0]                   dvr5;
277 
`else
278 
wire    [31:0]                   dvr5;
279 
`endif
280 
 
281 
//
282 
// Debug Value Register N
283 
//
284 
`ifdef OR1200_DU_DVR6
285 
reg     [31:0]                   dvr6;
286 
`else
287 
wire    [31:0]                   dvr6;
288 
`endif
289 
 
290 
//
291 
// Debug Value Register N
292 
//
293 
`ifdef OR1200_DU_DVR7
294 
reg     [31:0]                   dvr7;
295 
`else
296 
wire    [31:0]                   dvr7;
297 
`endif
298 
 
299 
//
300 
// Debug Control Register N
301 
//
302 
`ifdef OR1200_DU_DCR0
303 
reg     [7:0]                    dcr0;
304 
`else
305 
wire    [7:0]                    dcr0;
306 
`endif
307 
 
308 
//
309 
// Debug Control Register N
310 
//
311 
`ifdef OR1200_DU_DCR1
312 
reg     [7:0]                    dcr1;
313 
`else
314 
wire    [7:0]                    dcr1;
315 
`endif
316 
 
317 
//
318 
// Debug Control Register N
319 
//
320 
`ifdef OR1200_DU_DCR2
321 
reg     [7:0]                    dcr2;
322 
`else
323 
wire    [7:0]                    dcr2;
324 
`endif
325 
 
326 
//
327 
// Debug Control Register N
328 
//
329 
`ifdef OR1200_DU_DCR3
330 
reg     [7:0]                    dcr3;
331 
`else
332 
wire    [7:0]                    dcr3;
333 
`endif
334 
 
335 
//
336 
// Debug Control Register N
337 
//
338 
`ifdef OR1200_DU_DCR4
339 
reg     [7:0]                    dcr4;
340 
`else
341 
wire    [7:0]                    dcr4;
342 
`endif
343 
 
344 
//
345 
// Debug Control Register N
346 
//
347 
`ifdef OR1200_DU_DCR5
348 
reg     [7:0]                    dcr5;
349 
`else
350 
wire    [7:0]                    dcr5;
351 
`endif
352 
 
353 
//
354 
// Debug Control Register N
355 
//
356 
`ifdef OR1200_DU_DCR6
357 
reg     [7:0]                    dcr6;
358 
`else
359 
wire    [7:0]                    dcr6;
360 
`endif
361 
 
362 
//
363 
// Debug Control Register N
364 
//
365 
`ifdef OR1200_DU_DCR7
366 
reg     [7:0]                    dcr7;
367 
`else
368 
wire    [7:0]                    dcr7;
369 
`endif
370 
 
371 
//
372 
// Debug Watchpoint Counter Register 0
373 
//
374 
`ifdef OR1200_DU_DWCR0
375 
reg     [31:0]                   dwcr0;
376 
`else
377 
wire    [31:0]                   dwcr0;
378 
`endif
379 
 
380 
//
381 
// Debug Watchpoint Counter Register 1
382 
//
383 
`ifdef OR1200_DU_DWCR1
384 
reg     [31:0]                   dwcr1;
385 
`else
386 
wire    [31:0]                   dwcr1;
387 
`endif
388 
 
389 
//
390 
// Internal wires
391 
//
392 
wire                            dmr1_sel;       // DMR1 select
393 
wire                            dmr2_sel;       // DMR2 select
394 
wire                            dsr_sel;        // DSR select
395 
wire                            drr_sel;        // DRR select
396 
wire                            dvr0_sel,
397 
                                dvr1_sel,
398 
                                dvr2_sel,
399 
                                dvr3_sel,
400 
                                dvr4_sel,
401 
                                dvr5_sel,
402 
                                dvr6_sel,
403 
                                dvr7_sel;       // DVR selects
404 
wire                            dcr0_sel,
405 
                                dcr1_sel,
406 
                                dcr2_sel,
407 
                                dcr3_sel,
408 
                                dcr4_sel,
409 
                                dcr5_sel,
410 
                                dcr6_sel,
411 
                                dcr7_sel;       // DCR selects
412 
wire                            dwcr0_sel,
413 
                                dwcr1_sel;      // DWCR selects
414 
reg                             dbg_bp_r;
415 815 yannv 
reg                             ex_freeze_q;
416 350 julius 
`ifdef OR1200_DU_HWBKPTS
417 
reg     [31:0]                   match_cond0_ct;
418 
reg     [31:0]                   match_cond1_ct;
419 
reg     [31:0]                   match_cond2_ct;
420 
reg     [31:0]                   match_cond3_ct;
421 
reg     [31:0]                   match_cond4_ct;
422 
reg     [31:0]                   match_cond5_ct;
423 
reg     [31:0]                   match_cond6_ct;
424 
reg     [31:0]                   match_cond7_ct;
425 
reg                             match_cond0_stb;
426 
reg                             match_cond1_stb;
427 
reg                             match_cond2_stb;
428 
reg                             match_cond3_stb;
429 
reg                             match_cond4_stb;
430 
reg                             match_cond5_stb;
431 
reg                             match_cond6_stb;
432 
reg                             match_cond7_stb;
433 
reg                             match0;
434 
reg                             match1;
435 
reg                             match2;
436 
reg                             match3;
437 
reg                             match4;
438 
reg                             match5;
439 
reg                             match6;
440 
reg                             match7;
441 
reg                             wpcntr0_match;
442 
reg                             wpcntr1_match;
443 
reg                             incr_wpcntr0;
444 
reg                             incr_wpcntr1;
445 
reg     [10:0]                   wp;
446 
`endif
447 
wire                            du_hwbkpt;
448 
reg                             du_hwbkpt_hold;
449 
`ifdef OR1200_DU_READREGS
450 
reg     [31:0]                   spr_dat_o;
451 
`endif
452 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
453 
`ifdef OR1200_DU_TB_IMPLEMENTED
454 
wire                            tb_enw;
455 
reg     [7:0]                    tb_wadr;
456 
reg [31:0]                       tb_timstmp;
457 
`endif
458 
wire    [31:0]                   tbia_dat_o;
459 
wire    [31:0]                   tbim_dat_o;
460 
wire    [31:0]                   tbar_dat_o;
461 
wire    [31:0]                   tbts_dat_o;
462 
 
463 
//
464 
// DU registers address decoder
465 
//
466 
`ifdef OR1200_DU_DMR1
467 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
468 
`endif
469 
`ifdef OR1200_DU_DMR2
470 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
471 
`endif
472 
`ifdef OR1200_DU_DSR
473 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
474 
`endif
475 
`ifdef OR1200_DU_DRR
476 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
477 
`endif
478 
`ifdef OR1200_DU_DVR0
479 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
480 
`endif
481 
`ifdef OR1200_DU_DVR1
482 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
483 
`endif
484 
`ifdef OR1200_DU_DVR2
485 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
486 
`endif
487 
`ifdef OR1200_DU_DVR3
488 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
489 
`endif
490 
`ifdef OR1200_DU_DVR4
491 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
492 
`endif
493 
`ifdef OR1200_DU_DVR5
494 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
495 
`endif
496 
`ifdef OR1200_DU_DVR6
497 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
498 
`endif
499 
`ifdef OR1200_DU_DVR7
500 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
501 
`endif
502 
`ifdef OR1200_DU_DCR0
503 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
504 
`endif
505 
`ifdef OR1200_DU_DCR1
506 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
507 
`endif
508 
`ifdef OR1200_DU_DCR2
509 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
510 
`endif
511 
`ifdef OR1200_DU_DCR3
512 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
513 
`endif
514 
`ifdef OR1200_DU_DCR4
515 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
516 
`endif
517 
`ifdef OR1200_DU_DCR5
518 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
519 
`endif
520 
`ifdef OR1200_DU_DCR6
521 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
522 
`endif
523 
`ifdef OR1200_DU_DCR7
524 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
525 
`endif
526 
`ifdef OR1200_DU_DWCR0
527 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
528 
`endif
529 
`ifdef OR1200_DU_DWCR1
530 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
531 
`endif
532 
 
533 815 yannv 
// Track previous ex_freeze to detect when signals are updated
534 
always @(posedge clk)
535 
  ex_freeze_q <= ex_freeze;
536 
 
537 350 julius 
//
538 
// Decode started exception
539 
//
540 
// du_except_stop comes from or1200_except
541 
//
542 815 yannv 
always @(du_except_stop or ex_freeze_q) begin
543 350 julius 
        except_stop = 14'b00_0000_0000_0000;
544 363 julius 
        casez (du_except_stop)
545 
                14'b1?_????_????_????:
546 350 julius 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
547 363 julius 
                14'b01_????_????_????: begin
548 350 julius 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
549 
                end
550 363 julius 
                14'b00_1???_????_????: begin
551 350 julius 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
552 
                end
553 363 julius 
                14'b00_01??_????_????:
554 350 julius 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
555 363 julius 
                14'b00_001?_????_????: begin
556 350 julius 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
557 
                end
558 363 julius 
                14'b00_0001_????_????:
559 350 julius 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
560 363 julius 
                14'b00_0000_1???_????: begin
561 350 julius 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
562 
                end
563 363 julius 
                14'b00_0000_01??_????: begin
564 350 julius 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
565 
                end
566 363 julius 
                14'b00_0000_001?_????:
567 350 julius 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
568 363 julius 
                14'b00_0000_0001_????:
569 350 julius 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
570 363 julius 
                14'b00_0000_0000_1???: begin
571 350 julius 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
572 
                end
573 363 julius 
                14'b00_0000_0000_01??: begin
574 815 yannv 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
575 350 julius 
                end
576 363 julius 
                14'b00_0000_0000_001?: begin
577 350 julius 
                        except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
578 
                end
579 
                14'b00_0000_0000_0001:
580 815 yannv 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
581 350 julius 
                default:
582 
                        except_stop = 14'b00_0000_0000_0000;
583 815 yannv 
        endcase // casez (du_except_stop)
584 350 julius 
end
585 
 
586 
//
587 
// dbg_bp_o is registered
588 
//
589 
assign dbg_bp_o = dbg_bp_r;
590 
 
591 
//
592 
// Breakpoint activation register
593 
//
594 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
595 
        if (rst == `OR1200_RST_VALUE)
596 350 julius 
                dbg_bp_r <=  1'b0;
597 
        else if (!ex_freeze)
598 
                dbg_bp_r <=  |except_stop
599 
`ifdef OR1200_DU_DMR1_ST
600 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
601 
`endif
602 
`ifdef OR1200_DU_DMR1_BT
603 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
604 
`endif
605 
                        ;
606 
        else
607 
                dbg_bp_r <=  |except_stop;
608 
 
609 
//
610 
// Write to DMR1
611 
//
612 
`ifdef OR1200_DU_DMR1
613 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
614 
        if (rst == `OR1200_RST_VALUE)
615 350 julius 
                dmr1 <= 25'h000_0000;
616 
        else if (dmr1_sel && spr_write)
617 
`ifdef OR1200_DU_HWBKPTS
618 
                dmr1 <=  spr_dat_i[24:0];
619 
`else
620 
                dmr1 <=  {1'b0, spr_dat_i[23:22], 22'h00_0000};
621 
`endif
622 
`else
623 
assign dmr1 = 25'h000_0000;
624 
`endif
625 
 
626 
//
627 
// Write to DMR2
628 
//
629 
`ifdef OR1200_DU_DMR2
630 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
631 
        if (rst == `OR1200_RST_VALUE)
632 350 julius 
                dmr2 <= 24'h00_0000;
633 
        else if (dmr2_sel && spr_write)
634 
                dmr2 <=  spr_dat_i[23:0];
635 
`else
636 
assign dmr2 = 24'h00_0000;
637 
`endif
638 
 
639 
//
640 
// Write to DSR
641 
//
642 
`ifdef OR1200_DU_DSR
643 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
644 
        if (rst == `OR1200_RST_VALUE)
645 350 julius 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
646 
        else if (dsr_sel && spr_write)
647 
                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
648 
`else
649 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
650 
`endif
651 
 
652 
//
653 
// Write to DRR
654 
//
655 
`ifdef OR1200_DU_DRR
656 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
657 
        if (rst == `OR1200_RST_VALUE)
658 350 julius 
                drr <= 14'b0;
659 
        else if (drr_sel && spr_write)
660 
                drr <=  spr_dat_i[13:0];
661 
        else
662 
                drr <=  drr | except_stop;
663 
`else
664 
assign drr = 14'b0;
665 
`endif
666 
 
667 
//
668 
// Write to DVR0
669 
//
670 
`ifdef OR1200_DU_DVR0
671 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
672 
        if (rst == `OR1200_RST_VALUE)
673 350 julius 
                dvr0 <= 32'h0000_0000;
674 
        else if (dvr0_sel && spr_write)
675 
                dvr0 <=  spr_dat_i[31:0];
676 
`else
677 
assign dvr0 = 32'h0000_0000;
678 
`endif
679 
 
680 
//
681 
// Write to DVR1
682 
//
683 
`ifdef OR1200_DU_DVR1
684 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
685 
        if (rst == `OR1200_RST_VALUE)
686 350 julius 
                dvr1 <= 32'h0000_0000;
687 
        else if (dvr1_sel && spr_write)
688 
                dvr1 <=  spr_dat_i[31:0];
689 
`else
690 
assign dvr1 = 32'h0000_0000;
691 
`endif
692 
 
693 
//
694 
// Write to DVR2
695 
//
696 
`ifdef OR1200_DU_DVR2
697 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
698 
        if (rst == `OR1200_RST_VALUE)
699 350 julius 
                dvr2 <= 32'h0000_0000;
700 
        else if (dvr2_sel && spr_write)
701 
                dvr2 <=  spr_dat_i[31:0];
702 
`else
703 
assign dvr2 = 32'h0000_0000;
704 
`endif
705 
 
706 
//
707 
// Write to DVR3
708 
//
709 
`ifdef OR1200_DU_DVR3
710 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
711 
        if (rst == `OR1200_RST_VALUE)
712 350 julius 
                dvr3 <= 32'h0000_0000;
713 
        else if (dvr3_sel && spr_write)
714 
                dvr3 <=  spr_dat_i[31:0];
715 
`else
716 
assign dvr3 = 32'h0000_0000;
717 
`endif
718 
 
719 
//
720 
// Write to DVR4
721 
//
722 
`ifdef OR1200_DU_DVR4
723 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
724 
        if (rst == `OR1200_RST_VALUE)
725 350 julius 
                dvr4 <= 32'h0000_0000;
726 
        else if (dvr4_sel && spr_write)
727 
                dvr4 <=  spr_dat_i[31:0];
728 
`else
729 
assign dvr4 = 32'h0000_0000;
730 
`endif
731 
 
732 
//
733 
// Write to DVR5
734 
//
735 
`ifdef OR1200_DU_DVR5
736 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
737 
        if (rst == `OR1200_RST_VALUE)
738 350 julius 
                dvr5 <= 32'h0000_0000;
739 
        else if (dvr5_sel && spr_write)
740 
                dvr5 <=  spr_dat_i[31:0];
741 
`else
742 
assign dvr5 = 32'h0000_0000;
743 
`endif
744 
 
745 
//
746 
// Write to DVR6
747 
//
748 
`ifdef OR1200_DU_DVR6
749 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
750 
        if (rst == `OR1200_RST_VALUE)
751 350 julius 
                dvr6 <= 32'h0000_0000;
752 
        else if (dvr6_sel && spr_write)
753 
                dvr6 <=  spr_dat_i[31:0];
754 
`else
755 
assign dvr6 = 32'h0000_0000;
756 
`endif
757 
 
758 
//
759 
// Write to DVR7
760 
//
761 
`ifdef OR1200_DU_DVR7
762 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
763 
        if (rst == `OR1200_RST_VALUE)
764 350 julius 
                dvr7 <= 32'h0000_0000;
765 
        else if (dvr7_sel && spr_write)
766 
                dvr7 <=  spr_dat_i[31:0];
767 
`else
768 
assign dvr7 = 32'h0000_0000;
769 
`endif
770 
 
771 
//
772 
// Write to DCR0
773 
//
774 
`ifdef OR1200_DU_DCR0
775 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
776 
        if (rst == `OR1200_RST_VALUE)
777 350 julius 
                dcr0 <= 8'h00;
778 
        else if (dcr0_sel && spr_write)
779 
                dcr0 <=  spr_dat_i[7:0];
780 
`else
781 
assign dcr0 = 8'h00;
782 
`endif
783 
 
784 
//
785 
// Write to DCR1
786 
//
787 
`ifdef OR1200_DU_DCR1
788 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
789 
        if (rst == `OR1200_RST_VALUE)
790 350 julius 
                dcr1 <= 8'h00;
791 
        else if (dcr1_sel && spr_write)
792 
                dcr1 <=  spr_dat_i[7:0];
793 
`else
794 
assign dcr1 = 8'h00;
795 
`endif
796 
 
797 
//
798 
// Write to DCR2
799 
//
800 
`ifdef OR1200_DU_DCR2
801 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
802 
        if (rst == `OR1200_RST_VALUE)
803 350 julius 
                dcr2 <= 8'h00;
804 
        else if (dcr2_sel && spr_write)
805 
                dcr2 <=  spr_dat_i[7:0];
806 
`else
807 
assign dcr2 = 8'h00;
808 
`endif
809 
 
810 
//
811 
// Write to DCR3
812 
//
813 
`ifdef OR1200_DU_DCR3
814 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
815 
        if (rst == `OR1200_RST_VALUE)
816 350 julius 
                dcr3 <= 8'h00;
817 
        else if (dcr3_sel && spr_write)
818 
                dcr3 <=  spr_dat_i[7:0];
819 
`else
820 
assign dcr3 = 8'h00;
821 
`endif
822 
 
823 
//
824 
// Write to DCR4
825 
//
826 
`ifdef OR1200_DU_DCR4
827 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
828 
        if (rst == `OR1200_RST_VALUE)
829 350 julius 
                dcr4 <= 8'h00;
830 
        else if (dcr4_sel && spr_write)
831 
                dcr4 <=  spr_dat_i[7:0];
832 
`else
833 
assign dcr4 = 8'h00;
834 
`endif
835 
 
836 
//
837 
// Write to DCR5
838 
//
839 
`ifdef OR1200_DU_DCR5
840 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
841 
        if (rst == `OR1200_RST_VALUE)
842 350 julius 
                dcr5 <= 8'h00;
843 
        else if (dcr5_sel && spr_write)
844 
                dcr5 <=  spr_dat_i[7:0];
845 
`else
846 
assign dcr5 = 8'h00;
847 
`endif
848 
 
849 
//
850 
// Write to DCR6
851 
//
852 
`ifdef OR1200_DU_DCR6
853 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
854 
        if (rst == `OR1200_RST_VALUE)
855 350 julius 
                dcr6 <= 8'h00;
856 
        else if (dcr6_sel && spr_write)
857 
                dcr6 <=  spr_dat_i[7:0];
858 
`else
859 
assign dcr6 = 8'h00;
860 
`endif
861 
 
862 
//
863 
// Write to DCR7
864 
//
865 
`ifdef OR1200_DU_DCR7
866 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
867 
        if (rst == `OR1200_RST_VALUE)
868 350 julius 
                dcr7 <= 8'h00;
869 
        else if (dcr7_sel && spr_write)
870 
                dcr7 <=  spr_dat_i[7:0];
871 
`else
872 
assign dcr7 = 8'h00;
873 
`endif
874 
 
875 
//
876 
// Write to DWCR0
877 
//
878 
`ifdef OR1200_DU_DWCR0
879 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
880 
        if (rst == `OR1200_RST_VALUE)
881 350 julius 
                dwcr0 <= 32'h0000_0000;
882 
        else if (dwcr0_sel && spr_write)
883 
                dwcr0 <=  spr_dat_i[31:0];
884 
        else if (incr_wpcntr0)
885 
                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
886 
`else
887 
assign dwcr0 = 32'h0000_0000;
888 
`endif
889 
 
890 
//
891 
// Write to DWCR1
892 
//
893 
`ifdef OR1200_DU_DWCR1
894 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
895 
        if (rst == `OR1200_RST_VALUE)
896 350 julius 
                dwcr1 <= 32'h0000_0000;
897 
        else if (dwcr1_sel && spr_write)
898 
                dwcr1 <=  spr_dat_i[31:0];
899 
        else if (incr_wpcntr1)
900 
                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
901 
`else
902 
assign dwcr1 = 32'h0000_0000;
903 
`endif
904 
 
905 
//
906 
// Read DU registers
907 
//
908 
`ifdef OR1200_DU_READREGS
909 
always @(spr_addr or dsr or drr or dmr1 or dmr2
910 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
911 
        or dvr5 or dvr6 or dvr7
912 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
913 
        or dcr5 or dcr6 or dcr7
914 
        or dwcr0 or dwcr1
915 
`ifdef OR1200_DU_TB_IMPLEMENTED
916 
        or tb_wadr or tbia_dat_o or tbim_dat_o
917 
        or tbar_dat_o or tbts_dat_o
918 
`endif
919 
        )
920 363 julius 
        casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
921 350 julius 
`ifdef OR1200_DU_DVR0
922 
                `OR1200_DU_DVR0:
923 
                        spr_dat_o = dvr0;
924 
`endif
925 
`ifdef OR1200_DU_DVR1
926 
                `OR1200_DU_DVR1:
927 
                        spr_dat_o = dvr1;
928 
`endif
929 
`ifdef OR1200_DU_DVR2
930 
                `OR1200_DU_DVR2:
931 
                        spr_dat_o = dvr2;
932 
`endif
933 
`ifdef OR1200_DU_DVR3
934 
                `OR1200_DU_DVR3:
935 
                        spr_dat_o = dvr3;
936 
`endif
937 
`ifdef OR1200_DU_DVR4
938 
                `OR1200_DU_DVR4:
939 
                        spr_dat_o = dvr4;
940 
`endif
941 
`ifdef OR1200_DU_DVR5
942 
                `OR1200_DU_DVR5:
943 
                        spr_dat_o = dvr5;
944 
`endif
945 
`ifdef OR1200_DU_DVR6
946 
                `OR1200_DU_DVR6:
947 
                        spr_dat_o = dvr6;
948 
`endif
949 
`ifdef OR1200_DU_DVR7
950 
                `OR1200_DU_DVR7:
951 
                        spr_dat_o = dvr7;
952 
`endif
953 
`ifdef OR1200_DU_DCR0
954 
                `OR1200_DU_DCR0:
955 
                        spr_dat_o = {24'h00_0000, dcr0};
956 
`endif
957 
`ifdef OR1200_DU_DCR1
958 
                `OR1200_DU_DCR1:
959 
                        spr_dat_o = {24'h00_0000, dcr1};
960 
`endif
961 
`ifdef OR1200_DU_DCR2
962 
                `OR1200_DU_DCR2:
963 
                        spr_dat_o = {24'h00_0000, dcr2};
964 
`endif
965 
`ifdef OR1200_DU_DCR3
966 
                `OR1200_DU_DCR3:
967 
                        spr_dat_o = {24'h00_0000, dcr3};
968 
`endif
969 
`ifdef OR1200_DU_DCR4
970 
                `OR1200_DU_DCR4:
971 
                        spr_dat_o = {24'h00_0000, dcr4};
972 
`endif
973 
`ifdef OR1200_DU_DCR5
974 
                `OR1200_DU_DCR5:
975 
                        spr_dat_o = {24'h00_0000, dcr5};
976 
`endif
977 
`ifdef OR1200_DU_DCR6
978 
                `OR1200_DU_DCR6:
979 
                        spr_dat_o = {24'h00_0000, dcr6};
980 
`endif
981 
`ifdef OR1200_DU_DCR7
982 
                `OR1200_DU_DCR7:
983 
                        spr_dat_o = {24'h00_0000, dcr7};
984 
`endif
985 
`ifdef OR1200_DU_DMR1
986 
                `OR1200_DU_DMR1:
987 
                        spr_dat_o = {7'h00, dmr1};
988 
`endif
989 
`ifdef OR1200_DU_DMR2
990 
                `OR1200_DU_DMR2:
991 
                        spr_dat_o = {8'h00, dmr2};
992 
`endif
993 
`ifdef OR1200_DU_DWCR0
994 
                `OR1200_DU_DWCR0:
995 
                        spr_dat_o = dwcr0;
996 
`endif
997 
`ifdef OR1200_DU_DWCR1
998 
                `OR1200_DU_DWCR1:
999 
                        spr_dat_o = dwcr1;
1000 
`endif
1001 
`ifdef OR1200_DU_DSR
1002 
                `OR1200_DU_DSR:
1003 
                        spr_dat_o = {18'b0, dsr};
1004 
`endif
1005 
`ifdef OR1200_DU_DRR
1006 
                `OR1200_DU_DRR:
1007 
                        spr_dat_o = {18'b0, drr};
1008 
`endif
1009 
`ifdef OR1200_DU_TB_IMPLEMENTED
1010 
                `OR1200_DU_TBADR:
1011 
                        spr_dat_o = {24'h000000, tb_wadr};
1012 
                `OR1200_DU_TBIA:
1013 
                        spr_dat_o = tbia_dat_o;
1014 
                `OR1200_DU_TBIM:
1015 
                        spr_dat_o = tbim_dat_o;
1016 
                `OR1200_DU_TBAR:
1017 
                        spr_dat_o = tbar_dat_o;
1018 
                `OR1200_DU_TBTS:
1019 
                        spr_dat_o = tbts_dat_o;
1020 
`endif
1021 
                default:
1022 
                        spr_dat_o = 32'h0000_0000;
1023 
        endcase
1024 
`endif
1025 
 
1026 
//
1027 
// DSR alias
1028 
//
1029 
assign du_dsr = dsr;
1030 
 
1031 
`ifdef OR1200_DU_HWBKPTS
1032 
 
1033 
//
1034 
// Compare To What (Match Condition 0)
1035 
//
1036 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1037 
        or dcpu_dat_lsu or dcpu_we_i)
1038 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1039 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1040 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1041 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1042 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1043 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1044 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1045 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1046 
        endcase
1047 
 
1048 
//
1049 
// When To Compare (Match Condition 0)
1050 
//
1051 
always @(dcr0 or dcpu_cycstb_i)
1052 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1053 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1054 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1055 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1056 
        endcase
1057 
 
1058 
//
1059 
// Match Condition 0
1060 
//
1061 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1062 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1063 
                4'b0_xxx,
1064 
                4'b1_000,
1065 
                4'b1_111: match0 = 1'b0;
1066 
                4'b1_001: match0 =
1067 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
1068 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1069 
                4'b1_010: match0 =
1070 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
1071 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1072 
                4'b1_011: match0 =
1073 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
1074 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1075 
                4'b1_100: match0 =
1076 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
1077 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1078 
                4'b1_101: match0 =
1079 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
1080 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1081 
                4'b1_110: match0 =
1082 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
1083 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1084 
        endcase
1085 
 
1086 
//
1087 
// Watchpoint 0
1088 
//
1089 
always @(dmr1 or match0)
1090 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1091 
                2'b00: wp[0] = match0;
1092 
                2'b01: wp[0] = match0;
1093 
                2'b10: wp[0] = match0;
1094 
                2'b11: wp[0] = 1'b0;
1095 
        endcase
1096 
 
1097 
//
1098 
// Compare To What (Match Condition 1)
1099 
//
1100 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1101 
        or dcpu_dat_lsu or dcpu_we_i)
1102 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1103 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1104 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1105 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1106 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1107 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1108 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1109 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1110 
        endcase
1111 
 
1112 
//
1113 
// When To Compare (Match Condition 1)
1114 
//
1115 
always @(dcr1 or dcpu_cycstb_i)
1116 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1117 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1118 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1119 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1120 
        endcase
1121 
 
1122 
//
1123 
// Match Condition 1
1124 
//
1125 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1126 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1127 
                4'b0_xxx,
1128 
                4'b1_000,
1129 
                4'b1_111: match1 = 1'b0;
1130 
                4'b1_001: match1 =
1131 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
1132 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1133 
                4'b1_010: match1 =
1134 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
1135 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1136 
                4'b1_011: match1 =
1137 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
1138 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1139 
                4'b1_100: match1 =
1140 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
1141 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1142 
                4'b1_101: match1 =
1143 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
1144 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1145 
                4'b1_110: match1 =
1146 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
1147 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1148 
        endcase
1149 
 
1150 
//
1151 
// Watchpoint 1
1152 
//
1153 
always @(dmr1 or match1 or wp)
1154 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1155 
                2'b00: wp[1] = match1;
1156 
                2'b01: wp[1] = match1 & wp[0];
1157 
                2'b10: wp[1] = match1 | wp[0];
1158 
                2'b11: wp[1] = 1'b0;
1159 
        endcase
1160 
 
1161 
//
1162 
// Compare To What (Match Condition 2)
1163 
//
1164 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1165 
        or dcpu_dat_lsu or dcpu_we_i)
1166 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1167 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1168 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1169 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1170 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1171 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1172 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1173 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1174 
        endcase
1175 
 
1176 
//
1177 
// When To Compare (Match Condition 2)
1178 
//
1179 
always @(dcr2 or dcpu_cycstb_i)
1180 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1181 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1182 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1183 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1184 
        endcase
1185 
 
1186 
//
1187 
// Match Condition 2
1188 
//
1189 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1190 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1191 
                4'b0_xxx,
1192 
                4'b1_000,
1193 
                4'b1_111: match2 = 1'b0;
1194 
                4'b1_001: match2 =
1195 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
1196 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1197 
                4'b1_010: match2 =
1198 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
1199 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1200 
                4'b1_011: match2 =
1201 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
1202 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1203 
                4'b1_100: match2 =
1204 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
1205 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1206 
                4'b1_101: match2 =
1207 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
1208 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1209 
                4'b1_110: match2 =
1210 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
1211 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1212 
        endcase
1213 
 
1214 
//
1215 
// Watchpoint 2
1216 
//
1217 
always @(dmr1 or match2 or wp)
1218 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1219 
                2'b00: wp[2] = match2;
1220 
                2'b01: wp[2] = match2 & wp[1];
1221 
                2'b10: wp[2] = match2 | wp[1];
1222 
                2'b11: wp[2] = 1'b0;
1223 
        endcase
1224 
 
1225 
//
1226 
// Compare To What (Match Condition 3)
1227 
//
1228 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1229 
        or dcpu_dat_lsu or dcpu_we_i)
1230 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1231 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1232 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1233 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1234 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1235 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1236 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1237 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1238 
        endcase
1239 
 
1240 
//
1241 
// When To Compare (Match Condition 3)
1242 
//
1243 
always @(dcr3 or dcpu_cycstb_i)
1244 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1245 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1246 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1247 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1248 
        endcase
1249 
 
1250 
//
1251 
// Match Condition 3
1252 
//
1253 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1254 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1255 
                4'b0_xxx,
1256 
                4'b1_000,
1257 
                4'b1_111: match3 = 1'b0;
1258 
                4'b1_001: match3 =
1259 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
1260 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1261 
                4'b1_010: match3 =
1262 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
1263 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1264 
                4'b1_011: match3 =
1265 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
1266 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1267 
                4'b1_100: match3 =
1268 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
1269 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1270 
                4'b1_101: match3 =
1271 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
1272 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1273 
                4'b1_110: match3 =
1274 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
1275 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1276 
        endcase
1277 
 
1278 
//
1279 
// Watchpoint 3
1280 
//
1281 
always @(dmr1 or match3 or wp)
1282 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1283 
                2'b00: wp[3] = match3;
1284 
                2'b01: wp[3] = match3 & wp[2];
1285 
                2'b10: wp[3] = match3 | wp[2];
1286 
                2'b11: wp[3] = 1'b0;
1287 
        endcase
1288 
 
1289 
//
1290 
// Compare To What (Match Condition 4)
1291 
//
1292 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1293 
        or dcpu_dat_lsu or dcpu_we_i)
1294 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1295 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1296 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1297 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1298 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1299 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1300 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1301 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1302 
        endcase
1303 
 
1304 
//
1305 
// When To Compare (Match Condition 4)
1306 
//
1307 
always @(dcr4 or dcpu_cycstb_i)
1308 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1309 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1310 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1311 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1312 
        endcase
1313 
 
1314 
//
1315 
// Match Condition 4
1316 
//
1317 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1318 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1319 
                4'b0_xxx,
1320 
                4'b1_000,
1321 
                4'b1_111: match4 = 1'b0;
1322 
                4'b1_001: match4 =
1323 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
1324 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1325 
                4'b1_010: match4 =
1326 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
1327 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1328 
                4'b1_011: match4 =
1329 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
1330 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1331 
                4'b1_100: match4 =
1332 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
1333 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1334 
                4'b1_101: match4 =
1335 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
1336 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1337 
                4'b1_110: match4 =
1338 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
1339 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1340 
        endcase
1341 
 
1342 
//
1343 
// Watchpoint 4
1344 
//
1345 
always @(dmr1 or match4 or wp)
1346 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1347 
                2'b00: wp[4] = match4;
1348 
                2'b01: wp[4] = match4 & wp[3];
1349 
                2'b10: wp[4] = match4 | wp[3];
1350 
                2'b11: wp[4] = 1'b0;
1351 
        endcase
1352 
 
1353 
//
1354 
// Compare To What (Match Condition 5)
1355 
//
1356 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1357 
        or dcpu_dat_lsu or dcpu_we_i)
1358 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1359 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1360 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1361 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1362 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1363 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1364 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1365 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1366 
        endcase
1367 
 
1368 
//
1369 
// When To Compare (Match Condition 5)
1370 
//
1371 
always @(dcr5 or dcpu_cycstb_i)
1372 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1373 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1374 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1375 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1376 
        endcase
1377 
 
1378 
//
1379 
// Match Condition 5
1380 
//
1381 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1382 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1383 
                4'b0_xxx,
1384 
                4'b1_000,
1385 
                4'b1_111: match5 = 1'b0;
1386 
                4'b1_001: match5 =
1387 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
1388 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1389 
                4'b1_010: match5 =
1390 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
1391 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1392 
                4'b1_011: match5 =
1393 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
1394 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1395 
                4'b1_100: match5 =
1396 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
1397 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1398 
                4'b1_101: match5 =
1399 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
1400 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1401 
                4'b1_110: match5 =
1402 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
1403 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1404 
        endcase
1405 
 
1406 
//
1407 
// Watchpoint 5
1408 
//
1409 
always @(dmr1 or match5 or wp)
1410 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1411 
                2'b00: wp[5] = match5;
1412 
                2'b01: wp[5] = match5 & wp[4];
1413 
                2'b10: wp[5] = match5 | wp[4];
1414 
                2'b11: wp[5] = 1'b0;
1415 
        endcase
1416 
 
1417 
//
1418 
// Compare To What (Match Condition 6)
1419 
//
1420 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1421 
        or dcpu_dat_lsu or dcpu_we_i)
1422 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1423 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1424 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1425 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1426 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1427 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1428 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1429 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1430 
        endcase
1431 
 
1432 
//
1433 
// When To Compare (Match Condition 6)
1434 
//
1435 
always @(dcr6 or dcpu_cycstb_i)
1436 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1437 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1438 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1439 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1440 
        endcase
1441 
 
1442 
//
1443 
// Match Condition 6
1444 
//
1445 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1446 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1447 
                4'b0_xxx,
1448 
                4'b1_000,
1449 
                4'b1_111: match6 = 1'b0;
1450 
                4'b1_001: match6 =
1451 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
1452 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1453 
                4'b1_010: match6 =
1454 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
1455 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1456 
                4'b1_011: match6 =
1457 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
1458 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1459 
                4'b1_100: match6 =
1460 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
1461 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1462 
                4'b1_101: match6 =
1463 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
1464 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1465 
                4'b1_110: match6 =
1466 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
1467 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1468 
        endcase
1469 
 
1470 
//
1471 
// Watchpoint 6
1472 
//
1473 
always @(dmr1 or match6 or wp)
1474 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1475 
                2'b00: wp[6] = match6;
1476 
                2'b01: wp[6] = match6 & wp[5];
1477 
                2'b10: wp[6] = match6 | wp[5];
1478 
                2'b11: wp[6] = 1'b0;
1479 
        endcase
1480 
 
1481 
//
1482 
// Compare To What (Match Condition 7)
1483 
//
1484 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1485 
        or dcpu_dat_lsu or dcpu_we_i)
1486 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1487 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1488 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1489 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1490 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1491 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1492 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1493 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1494 
        endcase
1495 
 
1496 
//
1497 
// When To Compare (Match Condition 7)
1498 
//
1499 
always @(dcr7 or dcpu_cycstb_i)
1500 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1501 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1502 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1503 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1504 
        endcase
1505 
 
1506 
//
1507 
// Match Condition 7
1508 
//
1509 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1510 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1511 
                4'b0_xxx,
1512 
                4'b1_000,
1513 
                4'b1_111: match7 = 1'b0;
1514 
                4'b1_001: match7 =
1515 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
1516 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1517 
                4'b1_010: match7 =
1518 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
1519 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1520 
                4'b1_011: match7 =
1521 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
1522 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1523 
                4'b1_100: match7 =
1524 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
1525 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1526 
                4'b1_101: match7 =
1527 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
1528 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1529 
                4'b1_110: match7 =
1530 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
1531 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1532 
        endcase
1533 
 
1534 
//
1535 
// Watchpoint 7
1536 
//
1537 
always @(dmr1 or match7 or wp)
1538 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1539 
                2'b00: wp[7] = match7;
1540 
                2'b01: wp[7] = match7 & wp[6];
1541 
                2'b10: wp[7] = match7 | wp[6];
1542 
                2'b11: wp[7] = 1'b0;
1543 
        endcase
1544 
 
1545 
//
1546 
// Increment Watchpoint Counter 0
1547 
//
1548 
always @(wp or dmr2)
1549 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1550 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1551 
        else
1552 
                incr_wpcntr0 = 1'b0;
1553 
 
1554 
//
1555 
// Match Condition Watchpoint Counter 0
1556 
//
1557 
always @(dwcr0)
1558 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1559 
                wpcntr0_match = 1'b1;
1560 
        else
1561 
                wpcntr0_match = 1'b0;
1562 
 
1563 
 
1564 
//
1565 
// Watchpoint 8
1566 
//
1567 
always @(dmr1 or wpcntr0_match or wp)
1568 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1569 
                2'b00: wp[8] = wpcntr0_match;
1570 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1571 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1572 
                2'b11: wp[8] = 1'b0;
1573 
        endcase
1574 
 
1575 
 
1576 
//
1577 
// Increment Watchpoint Counter 1
1578 
//
1579 
always @(wp or dmr2)
1580 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1581 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1582 
        else
1583 
                incr_wpcntr1 = 1'b0;
1584 
 
1585 
//
1586 
// Match Condition Watchpoint Counter 1
1587 
//
1588 
always @(dwcr1)
1589 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1590 
                wpcntr1_match = 1'b1;
1591 
        else
1592 
                wpcntr1_match = 1'b0;
1593 
 
1594 
//
1595 
// Watchpoint 9
1596 
//
1597 
always @(dmr1 or wpcntr1_match or wp)
1598 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1599 
                2'b00: wp[9] = wpcntr1_match;
1600 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1601 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1602 
                2'b11: wp[9] = 1'b0;
1603 
        endcase
1604 
 
1605 
//
1606 
// Watchpoint 10
1607 
//
1608 
always @(dmr1 or dbg_ewt_i or wp)
1609 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1610 
                2'b00: wp[10] = dbg_ewt_i;
1611 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1612 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1613 
                2'b11: wp[10] = 1'b0;
1614 
        endcase
1615 
 
1616 
`endif
1617 
 
1618 
//
1619 
// Watchpoints can cause trap exception
1620 
//
1621 
`ifdef OR1200_DU_HWBKPTS
1622 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
1623 
`else
1624 
assign du_hwbkpt = 1'b0;
1625 
`endif
1626 
 
1627 
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
1628 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1629 
        if (rst == `OR1200_RST_VALUE)
1630 350 julius 
                du_hwbkpt_hold <=  1'b0;
1631 
        else if (du_hwbkpt & ex_freeze)
1632 
                du_hwbkpt_hold <=  1'b1;
1633 
        else if (!ex_freeze)
1634 
                du_hwbkpt_hold <=  1'b0;
1635 
 
1636 
`ifdef OR1200_DU_TB_IMPLEMENTED
1637 
//
1638 
// Simple trace buffer
1639 
// (right now hardcoded for Xilinx Virtex FPGAs)
1640 
//
1641 
// Stores last 256 instruction addresses, instruction
1642 
// machine words and ALU results
1643 
//
1644 
 
1645 
//
1646 
// Trace buffer write enable
1647 
//
1648 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1649 
 
1650 
//
1651 
// Trace buffer write address pointer
1652 
//
1653 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1654 
        if (rst == `OR1200_RST_VALUE)
1655 350 julius 
                tb_wadr <=  8'h00;
1656 
        else if (tb_enw)
1657 
                tb_wadr <=  tb_wadr + 8'd1;
1658 
 
1659 
//
1660 
// Free running counter (time stamp)
1661 
//
1662 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1663 
        if (rst == `OR1200_RST_VALUE)
1664 350 julius 
                tb_timstmp <=  32'h00000000;
1665 
        else if (!dbg_bp_r)
1666 
                tb_timstmp <=  tb_timstmp + 32'd1;
1667 
 
1668 
//
1669 
// Trace buffer RAMs
1670 
//
1671 
 
1672 
or1200_dpram_256x32 tbia_ram(
1673 
        .clk_a(clk),
1674 
        .rst_a(1'b0),
1675 
        .addr_a(spr_addr[7:0]),
1676 
        .ce_a(1'b1),
1677 
        .oe_a(1'b1),
1678 
        .do_a(tbia_dat_o),
1679 
 
1680 
        .clk_b(clk),
1681 
        .rst_b(1'b0),
1682 
        .addr_b(tb_wadr),
1683 
        .di_b(spr_dat_npc),
1684 
        .ce_b(1'b1),
1685 
        .we_b(tb_enw)
1686 
 
1687 
);
1688 
 
1689 
or1200_dpram_256x32 tbim_ram(
1690 
        .clk_a(clk),
1691 
        .rst_a(1'b0),
1692 
        .addr_a(spr_addr[7:0]),
1693 
        .ce_a(1'b1),
1694 
        .oe_a(1'b1),
1695 
        .do_a(tbim_dat_o),
1696 
 
1697 
        .clk_b(clk),
1698 
        .rst_b(1'b0),
1699 
        .addr_b(tb_wadr),
1700 
        .di_b(ex_insn),
1701 
        .ce_b(1'b1),
1702 
        .we_b(tb_enw)
1703 
);
1704 
 
1705 
or1200_dpram_256x32 tbar_ram(
1706 
        .clk_a(clk),
1707 
        .rst_a(1'b0),
1708 
        .addr_a(spr_addr[7:0]),
1709 
        .ce_a(1'b1),
1710 
        .oe_a(1'b1),
1711 
        .do_a(tbar_dat_o),
1712 
 
1713 
        .clk_b(clk),
1714 
        .rst_b(1'b0),
1715 
        .addr_b(tb_wadr),
1716 
        .di_b(rf_dataw),
1717 
        .ce_b(1'b1),
1718 
        .we_b(tb_enw)
1719 
);
1720 
 
1721 
or1200_dpram_256x32 tbts_ram(
1722 
        .clk_a(clk),
1723 
        .rst_a(1'b0),
1724 
        .addr_a(spr_addr[7:0]),
1725 
        .ce_a(1'b1),
1726 
        .oe_a(1'b1),
1727 
        .do_a(tbts_dat_o),
1728 
 
1729 
        .clk_b(clk),
1730 
        .rst_b(1'b0),
1731 
        .addr_b(tb_wadr),
1732 
        .di_b(tb_timstmp),
1733 
        .ce_b(1'b1),
1734 
        .we_b(tb_enw)
1735 
);
1736 
 
1737 
`else
1738 
 
1739 
assign tbia_dat_o = 32'h0000_0000;
1740 
assign tbim_dat_o = 32'h0000_0000;
1741 
assign tbar_dat_o = 32'h0000_0000;
1742 
assign tbts_dat_o = 32'h0000_0000;
1743 
 
1744 
`endif  // OR1200_DU_TB_IMPLEMENTED
1745 
 
1746 
`else   // OR1200_DU_IMPLEMENTED
1747 
 
1748 
//
1749 
// When DU is not implemented, drive all outputs as would when DU is disabled
1750 
//
1751 
assign dbg_bp_o = 1'b0;
1752 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1753 
assign du_dmr1 = {25{1'b0}};
1754 
assign du_hwbkpt = 1'b0;
1755 
 
1756 
//
1757 
// Read DU registers
1758 
//
1759 
`ifdef OR1200_DU_READREGS
1760 
assign spr_dat_o = 32'h0000_0000;
1761 
`ifdef OR1200_DU_UNUSED_ZERO
1762 
`endif
1763 
`endif
1764 
 
1765 
`endif
1766 
 
1767 
endmodule

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