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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [utils/] [or32-idecode/] [or32-opc.c] - Blame information for rev 261

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1 6 julius
/* Table of opcodes for the OpenRISC 1000 ISA.
2
   Copyright 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
3
   Contributed by Damjan Lampret (lampret@opencores.org).
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
 
22
/* We treat all letters the same in encode/decode routines so
23
   we need to assign some characteristics to them like signess etc.  */
24
#include <string.h>
25
#include <stdio.h>
26
#include <stdlib.h>
27
//#include "safe-ctype.h"
28
#include <ctype.h>
29
#include "ansidecl.h"
30
/*
31
#ifdef HAVE_CONFIG_H
32
# include "config.h"
33
#endif
34
#ifdef HAS_EXECUTION
35
# ifdef HAVE_INTTYPES_H
36
#  include <inttypes.h> // ...but to get arch.h we need uint{8,16,32}_t..
37
# endif
38
# include "port.h"
39
# include "arch.h" // ...but to get abstract.h, we need oraddr_t...
40
# include "abstract.h" // To get struct iqueue_entry...
41
# include "debug.h" // To get debug()
42
#endif
43
*/
44
#include "or32.h"
45
 
46
const struct or32_letter or32_letters[] =
47
{
48
  { 'A', NUM_UNSIGNED },
49
  { 'B', NUM_UNSIGNED },
50
  { 'D', NUM_UNSIGNED },
51
  { 'I', NUM_SIGNED },
52
  { 'K', NUM_UNSIGNED },
53
  { 'L', NUM_UNSIGNED },
54
  { 'N', NUM_SIGNED },
55
  { '0', NUM_UNSIGNED },
56
  { '\0', 0 }     /* Dummy entry.  */
57
};
58
 
59
/* Opcode encoding:
60
   machine[31:30]: first two bits of opcode
61
                   00 - neither of source operands is GPR
62
                   01 - second source operand is GPR (rB)
63
                   10 - first source operand is GPR (rA)
64
                   11 - both source operands are GPRs (rA and rB)
65
   machine[29:26]: next four bits of opcode
66
   machine[25:00]: instruction operands (specific to individual instruction)
67
 
68
  Recommendation: irrelevant instruction bits should be set with a value of
69
  bits in same positions of instruction preceding current instruction in the
70
  code (when assembling).  */
71
 
72
#ifdef HAS_EXECUTION
73
# if SIMPLE_EXECUTION
74
#  define EFN &l_none
75
#  define EF(func) &(func)
76
#  define EFI &l_invalid
77
# elif COMPLEX_EXECUTION
78
#  define EFN "l_none"
79
#  define EFI "l_invalid"
80
#  ifdef __GNUC__
81
#   define EF(func) #func
82
#  else
83
#   define EF(func) "func"
84
#  endif
85
# else /* DYNAMIC_EXECUTION */
86
#  define EFN &l_none
87
#  define EF(func) &(gen_ ##func)
88
#  define EFI &gen_l_invalid
89
# endif
90
#else /* HAS_EXECUTION */
91
# define EFN &l_none
92
# define EF(func) EFN
93
# define EFI EFN
94
#endif /* HAS_EXECUTION */
95
 
96
const struct or32_opcode or32_opcodes[] = {
97
  { "l.j",        "N",           "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY, it_jump },
98
  { "l.jal",      "N",           "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY, it_jump },
99
  { "l.bnf",      "N",           "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
100
  { "l.bf",       "N",           "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
101
  { "l.nop",      "K",           "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0, it_nop },
102
  { "l.movhi",    "rD,K",        "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0, it_movimm },
103
  { "l.macrc",    "rD",          "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0, it_mac },
104
  { "l.sys",      "K",           "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0, it_exception },
105
  { "l.trap",     "K",           "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0, it_exception },
106
  { "l.msync",    "",            "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
107
  { "l.psync",    "",            "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
108
  { "l.csync",    "",            "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
109
  { "l.rfe",      "",            "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), 0, it_exception },
110
  { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_unknown },
111
  { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_unknown },
112
  { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_unknown },
113
  { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_unknown },
114
  { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4",   EFI, 0, it_unknown },
115
  { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5",   EFI, 0, it_unknown },
116
  { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_unknown },
117
  { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_unknown },
118
  { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_unknown },
119
  { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_unknown },
120
  { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_unknown },
121
  { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_unknown },
122
  { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0",   EFI, 0, it_unknown },
123
  { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1",   EFI, 0, it_unknown },
124
  { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2",   EFI, 0, it_unknown },
125
  { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3",   EFI, 0, it_unknown },
126
  { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4",   EFI, 0, it_unknown },
127
  { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5",   EFI, 0, it_unknown },
128
  { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6",   EFI, 0, it_unknown },
129
  { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7",   EFI, 0, it_unknown },
130
  { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8",   EFI, 0, it_unknown },
131
  { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9",   EFI, 0, it_unknown },
132
  { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA",   EFI, 0, it_unknown },
133
  { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB",   EFI, 0, it_unknown },
134
  { "lv.add.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0",   EFI, 0, it_unknown },
135
  { "lv.add.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1",   EFI, 0, it_unknown },
136
  { "lv.adds.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2",   EFI, 0, it_unknown },
137
  { "lv.adds.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3",   EFI, 0, it_unknown },
138
  { "lv.addu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4",   EFI, 0, it_unknown },
139
  { "lv.addu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5",   EFI, 0, it_unknown },
140
  { "lv.addus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6",   EFI, 0, it_unknown },
141
  { "lv.addus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7",   EFI, 0, it_unknown },
142
  { "lv.and",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8",   EFI, 0, it_unknown },
143
  { "lv.avg.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9",   EFI, 0, it_unknown },
144
  { "lv.avg.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA",   EFI, 0, it_unknown },
145
  { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0",   EFI, 0, it_unknown },
146
  { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1",   EFI, 0, it_unknown },
147
  { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2",   EFI, 0, it_unknown },
148
  { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3",   EFI, 0, it_unknown },
149
  { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4",   EFI, 0, it_unknown },
150
  { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5",   EFI, 0, it_unknown },
151
  { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6",   EFI, 0, it_unknown },
152
  { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7",   EFI, 0, it_unknown },
153
  { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8",   EFI, 0, it_unknown },
154
  { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9",   EFI, 0, it_unknown },
155
  { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA",   EFI, 0, it_unknown },
156
  { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB",   EFI, 0, it_unknown },
157
  { "lv.madds.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4",   EFI, 0, it_unknown },
158
  { "lv.max.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5",   EFI, 0, it_unknown },
159
  { "lv.max.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6",   EFI, 0, it_unknown },
160
  { "lv.merge.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7",   EFI, 0, it_unknown },
161
  { "lv.merge.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8",   EFI, 0, it_unknown },
162
  { "lv.min.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9",   EFI, 0, it_unknown },
163
  { "lv.min.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA",   EFI, 0, it_unknown },
164
  { "lv.msubs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB",   EFI, 0, it_unknown },
165
  { "lv.muls.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC",   EFI, 0, it_unknown },
166
  { "lv.nand",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD",   EFI, 0, it_unknown },
167
  { "lv.nor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE",   EFI, 0, it_unknown },
168
  { "lv.or",      "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF",   EFI, 0, it_unknown },
169
  { "lv.pack.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0",   EFI, 0, it_unknown },
170
  { "lv.pack.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1",   EFI, 0, it_unknown },
171
  { "lv.packs.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2",   EFI, 0, it_unknown },
172
  { "lv.packs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3",   EFI, 0, it_unknown },
173
  { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4",   EFI, 0, it_unknown },
174
  { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5",   EFI, 0, it_unknown },
175
  { "lv.perm.n",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6",   EFI, 0, it_unknown },
176
  { "lv.rl.b",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7",   EFI, 0, it_unknown },
177
  { "lv.rl.h",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8",   EFI, 0, it_unknown },
178
  { "lv.sll.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9",   EFI, 0, it_unknown },
179
  { "lv.sll.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA",   EFI, 0, it_unknown },
180
  { "lv.sll",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB",   EFI, 0, it_unknown },
181
  { "lv.srl.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC",   EFI, 0, it_unknown },
182
  { "lv.srl.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD",   EFI, 0, it_unknown },
183
  { "lv.sra.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE",   EFI, 0, it_unknown },
184
  { "lv.sra.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF",   EFI, 0, it_unknown },
185
  { "lv.srl",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0",   EFI, 0, it_unknown },
186
  { "lv.sub.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1",   EFI, 0, it_unknown },
187
  { "lv.sub.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2",   EFI, 0, it_unknown },
188
  { "lv.subs.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3",   EFI, 0, it_unknown },
189
  { "lv.subs.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4",   EFI, 0, it_unknown },
190
  { "lv.subu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5",   EFI, 0, it_unknown },
191
  { "lv.subu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6",   EFI, 0, it_unknown },
192
  { "lv.subus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7",   EFI, 0, it_unknown },
193
  { "lv.subus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8",   EFI, 0, it_unknown },
194
  { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9",   EFI, 0, it_unknown },
195
  { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA",   EFI, 0, it_unknown },
196
  { "lv.xor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB",   EFI, 0, it_unknown },
197
  { "lv.cust1",   "",            "00 0xA  ----- ----- ---- ---- 0xC ----",  EFI, 0, it_unknown },
198
  { "lv.cust2",   "",            "00 0xA  ----- ----- ---- ---- 0xD ----",  EFI, 0, it_unknown },
199
  { "lv.cust3",   "",            "00 0xA  ----- ----- ---- ---- 0xE ----",  EFI, 0, it_unknown },
200
  { "lv.cust4",   "",            "00 0xA  ----- ----- ---- ---- 0xF ----",  EFI, 0, it_unknown },
201
 
202
  { "l.jr",       "rB",          "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY, it_jump },
203
  { "l.jalr",     "rB",          "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY, it_jump },
204
  { "l.maci",     "rA,I",        "01 0x3  IIIII AAAAA ---- -III IIII IIII", EF(l_mac), 0, it_mac },
205
  { "l.cust1",    "",            "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0, it_unknown },
206
  { "l.cust2",    "",            "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0, it_unknown },
207
  { "l.cust3",    "",            "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0, it_unknown },
208
  { "l.cust4",    "",            "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0, it_unknown },
209
 
210
  { "l.ld",       "rD,I(rA)",    "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
211
  { "l.lwz",      "rD,I(rA)",    "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0, it_load },
212
  { "l.lws",      "rD,I(rA)",    "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
213
  { "l.lbz",      "rD,I(rA)",    "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0, it_load },
214
  { "l.lbs",      "rD,I(rA)",    "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0, it_load },
215
  { "l.lhz",      "rD,I(rA)",    "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0, it_load },
216
  { "l.lhs",      "rD,I(rA)",    "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0, it_load },
217
 
218
  { "l.addi",     "rD,rA,I",     "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), OR32_W_FLAG, it_arith },
219
  { "l.addic",    "rD,rA,I",     "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_arith },
220
  { "l.andi",     "rD,rA,K",     "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), OR32_W_FLAG, it_arith },
221
  { "l.ori",      "rD,rA,K",     "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0, it_arith },
222
  { "l.xori",     "rD,rA,I",     "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0, it_arith },
223
  { "l.muli",     "rD,rA,I",     "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EF(l_mul), 0, it_arith },
224
  { "l.mfspr",    "rD,rA,K",     "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0, it_move },
225
  { "l.slli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0, it_shift },
226
  { "l.srli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0, it_shift },
227
  { "l.srai",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0, it_shift },
228
  { "l.rori",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0, it_shift },
229
 
230
  { "l.sfeqi",    "rA,I",        "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG, it_compare },
231
  { "l.sfnei",    "rA,I",        "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG, it_compare },
232
  { "l.sfgtui",   "rA,I",        "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG, it_compare },
233
  { "l.sfgeui",   "rA,I",        "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG, it_compare },
234
  { "l.sfltui",   "rA,I",        "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG, it_compare },
235
  { "l.sfleui",   "rA,I",        "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG, it_compare },
236
  { "l.sfgtsi",   "rA,I",        "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG, it_compare },
237
  { "l.sfgesi",   "rA,I",        "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG, it_compare },
238
  { "l.sfltsi",   "rA,I",        "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG, it_compare },
239
  { "l.sflesi",   "rA,I",        "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG, it_compare },
240
 
241
  { "l.mtspr",    "rA,rB,K",     "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0, it_move },
242
  { "l.mac",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x1",  EF(l_mac), 0, it_mac },
243
  { "l.msb",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x2",  EF(l_msb), 0, it_mac },
244
 
245
  { "lf.add.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x0",   EF(lf_add_s), 0, it_float },
246
  { "lf.sub.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x1",   EF(lf_sub_s), 0, it_float },
247
  { "lf.mul.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x2",   EF(lf_mul_s), 0, it_float },
248
  { "lf.div.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x3",   EF(lf_div_s), 0, it_float },
249
  { "lf.itof.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x4",   EF(lf_itof_s), 0, it_float },
250
  { "lf.ftoi.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x5",   EF(lf_ftoi_s), 0, it_float },
251
  { "lf.rem.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x6",   EF(lf_rem_s), 0, it_float },
252
  { "lf.madd.s",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x7",   EF(lf_madd_s), 0, it_float },
253
  { "lf.sfeq.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x8",   EF(lf_sfeq_s), 0, it_float },
254
  { "lf.sfne.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x9",   EF(lf_sfne_s), 0, it_float },
255
  { "lf.sfgt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xA",   EF(lf_sfgt_s), 0, it_float },
256
  { "lf.sfge.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xB",   EF(lf_sfge_s), 0, it_float },
257
  { "lf.sflt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xC",   EF(lf_sflt_s), 0, it_float },
258
  { "lf.sfle.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xD",   EF(lf_sfle_s), 0, it_float },
259
  { "lf.cust1.s", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xD ----",  EFI, 0, it_float },
260
 
261
  { "lf.add.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_float },
262
  { "lf.sub.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_float },
263
  { "lf.mul.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_float },
264
  { "lf.div.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_float },
265
  { "lf.itof.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x4",   EFI, 0, it_float },
266
  { "lf.ftoi.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x5",   EFI, 0, it_float },
267
  { "lf.rem.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_float },
268
  { "lf.madd.d",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_float },
269
  { "lf.sfeq.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_float },
270
  { "lf.sfne.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_float },
271
  { "lf.sfgt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_float },
272
  { "lf.sfge.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_float },
273
  { "lf.sflt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xC",   EFI, 0, it_float },
274
  { "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD",   EFI, 0, it_float },
275
  { "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----",  EFI, 0, it_float },
276
 
277
  { "l.sd",       "I(rD),rB",    "11 0x4  IIIII DDDDD BBBB BIII IIII IIII", EFI, 0, it_store },
278
  { "l.sw",       "I(rD),rB",    "11 0x5  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sw), 0, it_store },
279
  { "l.sb",       "I(rD),rB",    "11 0x6  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sb), 0, it_store },
280
  { "l.sh",       "I(rD),rB",    "11 0x7  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sh), 0, it_store },
281
 
282
  { "l.add",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",  EF(l_add), OR32_W_FLAG, it_arith },
283
  { "l.addc",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",  EF(l_addc), OR32_W_FLAG, it_arith },
284
  { "l.sub",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2",  EF(l_sub), 0, it_arith },
285
  { "l.and",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3",  EF(l_and), OR32_W_FLAG, it_arith },
286
  { "l.or",       "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4",  EF(l_or), 0, it_arith },
287
  { "l.xor",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5",  EF(l_xor), 0, it_arith },
288
  { "l.mul",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6",  EF(l_mul), 0, it_arith },
289
 
290
  { "l.sll",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8",  EF(l_sll), 0, it_shift },
291
  { "l.srl",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8",  EF(l_srl), 0, it_shift },
292
  { "l.sra",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8",  EF(l_sra), 0, it_shift },
293
  { "l.ror",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8",  EFI, 0, it_shift },
294
  { "l.div",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x9",  EF(l_div), 0, it_arith },
295
  { "l.divu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xA",  EF(l_divu), 0, it_arith },
296
  { "l.mulu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB",  EFI, 0, it_arith },
297
  { "l.extbs",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xC",  EF(l_extbs), 0, it_move },
298
  { "l.exths",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xC",  EF(l_exths), 0, it_move },
299
  { "l.extws",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xD",  EF(l_extws), 0, it_move },
300
  { "l.extbz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 11-- 0xC",  EF(l_extbz), 0, it_move },
301
  { "l.exthz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 10-- 0xC",  EF(l_exthz), 0, it_move },
302
  { "l.extwz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xD",  EF(l_extwz), 0, it_move },
303
  { "l.cmov",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE",  EF(l_cmov), OR32_R_FLAG, it_move },
304
  { "l.ff1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 ---- 0xF",  EF(l_ff1), 0, it_arith },
305
  { "l.fl1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --01 ---- 0xF",  EFI, 0, it_arith },
306
 
307
  { "l.sfeq",     "rA,rB",       "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG, it_compare },
308
  { "l.sfne",     "rA,rB",       "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG, it_compare },
309
  { "l.sfgtu",    "rA,rB",       "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG, it_compare },
310
  { "l.sfgeu",    "rA,rB",       "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG, it_compare },
311
  { "l.sfltu",    "rA,rB",       "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG, it_compare },
312
  { "l.sfleu",    "rA,rB",       "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG, it_compare },
313
  { "l.sfgts",    "rA,rB",       "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG, it_compare },
314
  { "l.sfges",    "rA,rB",       "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG, it_compare },
315
  { "l.sflts",    "rA,rB",       "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG, it_compare },
316
  { "l.sfles",    "rA,rB",       "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG, it_compare },
317
 
318
  { "l.cust5",    "rD,rA,rB,L,K","11 0xC  DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI, 0, it_unknown },
319
  { "l.cust6",    "",            "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
320
  { "l.cust7",    "",            "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
321
  { "l.cust8",    "",            "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
322
 
323
  /* This section should not be defined in or1ksim, since it contains duplicates,
324
     which would cause machine builder to complain.  */
325
#ifdef HAS_CUST
326
  { "l.cust5_1",  "rD",          "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
327
  { "l.cust5_2",  "rD,rA"   ,    "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
328
  { "l.cust5_3",  "rD,rA,rB",    "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
329
 
330
  { "l.cust6_1",  "rD",          "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
331
  { "l.cust6_2",  "rD,rA"   ,    "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
332
  { "l.cust6_3",  "rD,rA,rB",    "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
333
 
334
  { "l.cust7_1",  "rD",          "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
335
  { "l.cust7_2",  "rD,rA"   ,    "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
336
  { "l.cust7_3",  "rD,rA,rB",    "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
337
 
338
  { "l.cust8_1",  "rD",          "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
339
  { "l.cust8_2",  "rD,rA"   ,    "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
340
  { "l.cust8_3",  "rD,rA,rB",    "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
341
#endif
342
 
343
  /* Dummy entry, not included in num_opcodes.  This
344
     lets code examine entry i+1 without checking
345
     if we've run off the end of the table.  */
346
  { "", "", "", EFI, 0, 0 }
347
};
348
 
349
#undef EFI
350
#undef EFN
351
#undef EF 
352
 
353
/* Define dummy, if debug is not defined.  */
354
#ifndef HAS_DEBUG
355
#define debug(l, fmt...) ;
356
#endif
357
 
358
const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
359
 
360
/* Calculates instruction length in bytes. Always 4 for OR32.  */
361
 
362
int
363
insn_len (int insn_index ATTRIBUTE_UNUSED)
364
{
365
  insn_index = 0; /* Just to get rid that warning.  */
366
  return 4;
367
}
368
 
369
/* Is individual insn's operand signed or unsigned?  */
370
 
371
int
372
letter_signed (char l)
373
{
374
  const struct or32_letter *pletter;
375
 
376
  for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
377
    if (pletter->letter == l)
378
      return pletter->sign;
379
 
380
  printf ("letter_signed(%c): Unknown letter.\n", l);
381
  return 0;
382
}
383
 
384
/* Simple cache for letter ranges */
385
static int range_cache[256] = {0};
386
 
387
/* Number of letters in the individual lettered operand.  */
388
int
389
letter_range (char l)
390
{
391
  const struct or32_opcode *pinsn;
392
  char *enc;
393
  int range = 0;
394
 
395
  /* Is value cached? */
396
  if ((range = range_cache[(unsigned char)l])) return range;
397
 
398
  for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
399
    {
400
      if (strchr (pinsn->encoding,l))
401
        {
402
          for (enc = pinsn->encoding; *enc != '\0'; enc ++)
403
            if ((*enc == '0') && (*(enc + 1) == 'x'))
404
              enc += 2;
405
            else if (*enc == l)
406
              range++;
407
          return range_cache[(unsigned char)l] = range;
408
        }
409
    }
410
 
411
  printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
412
  exit (1);
413
}
414
 
415
/* MM: Returns index of given instruction name.  */
416
 
417
int
418
insn_index (char *insn)
419
{
420
  unsigned int i;
421
  int found = -1;
422
 
423
  for (i = 0; i < or32_num_opcodes; i++)
424
    if (!strcmp (or32_opcodes[i].name, insn))
425
      {
426
        found = i;
427
        break;
428
      }
429
  return found;
430
}
431
 
432
const char *
433
insn_name (int index)
434
{
435
  if (index >= 0 && index < (int) or32_num_opcodes)
436
    return or32_opcodes[index].name;
437
  else
438
    return "???";
439
}
440
 
441
#if defined(HAS_EXECUTION) && SIMPLE_EXECUTION
442
void
443
l_none(struct iqueue_entry *current)
444
{
445
}
446
#elif defined(HAS_EXECUTION) && DYNAMIC_EXECUTION
447
void
448
l_none(struct op_queue *opq, int *param_t, orreg_t *param, int delay_slot)
449
{
450
}
451
#else
452
void
453
l_none (void)
454
{
455
}
456
#endif
457
 
458
/* Finite automata for instruction decoding building code.  */
459
 
460
/* Find simbols in encoding.  */
461
 
462
unsigned long
463
insn_extract (char param_ch, char *enc_initial)
464
{
465
  char *enc;
466
  unsigned long ret = 0;
467
  unsigned opc_pos = 32;
468
 
469
  for (enc = enc_initial; *enc != '\0'; )
470
    if ((*enc == '0') && (*(enc + 1) == 'x'))
471
      {
472
        unsigned long tmp = strtol (enc+2, NULL, 16);
473
 
474
        opc_pos -= 4;
475
        if (param_ch == '0' || param_ch == '1')
476
          {
477
            if (param_ch == '0')
478
              tmp = 15 - tmp;
479
            ret |= tmp << opc_pos;
480
          }
481
        enc += 3;
482
      }
483
    else
484
      {
485
        //if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
486
        if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha (*enc))
487
          {
488
            opc_pos--;
489
            if (param_ch == *enc)
490
              ret |= 1 << opc_pos;
491
          }
492
        enc++;
493
      }
494
  return ret;
495
}
496
 
497
#define MAX_AUTOMATA_SIZE  1200
498
#define MAX_OP_TABLE_SIZE  1200
499
#define MAX_LEN            8
500
 
501
#ifndef MIN
502
#define MIN(x, y)          ((x) < (y) ? (x) : (y))
503
#endif
504
 
505
unsigned long *automata;
506
int nuncovered;
507
int curpass = 0;
508
 
509
/* MM: Struct that hold runtime build information about instructions.  */
510
struct temp_insn_struct *ti;
511
 
512
struct insn_op_struct *op_data, **op_start;
513
 
514
/* Recursive utility function used to find best match and to build automata.  */
515
 
516
static unsigned long *
517
cover_insn (unsigned long * cur, int pass, unsigned int mask)
518
{
519
  int best_first = 0, last_match = -1, ninstr = 0;
520
  unsigned int best_len = 0;
521
  unsigned int i;
522
  unsigned long cur_mask = mask;
523
  unsigned long *next;
524
 
525
  for (i = 0; i < or32_num_opcodes; i++)
526
    if (ti[i].in_pass == pass)
527
      {
528
        cur_mask &= ti[i].insn_mask;
529
        ninstr++;
530
        last_match = i;
531
      }
532
 
533
  debug (8, "%08X %08lX\n", mask, cur_mask);
534
 
535
  if (ninstr == 0)
536
    return 0;
537
 
538
  if (ninstr == 1)
539
    {
540
      /* Leaf holds instruction index.  */
541
      debug (8, "%li>I%i %s\n",
542
             (long)(cur - automata), last_match, or32_opcodes[last_match].name);
543
 
544
      *cur = LEAF_FLAG | last_match;
545
      cur++;
546
      nuncovered--;
547
    }
548
  else
549
    {
550
      /* Find longest match.  */
551
      for (i = 0; i < 32; i++)
552
        {
553
          unsigned int len;
554
 
555
          for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
556
            {
557
              unsigned long m = (1UL << ((unsigned long) len)) - 1;
558
 
559
              debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)",
560
                     len,m, cur_mask, i, (cur_mask >> (unsigned)i),
561
                     (cur_mask >> (unsigned) i) & m);
562
 
563
              if ((m & (cur_mask >> (unsigned) i)) == m)
564
                {
565
                  best_len = len;
566
                  best_first = i;
567
                  debug (9, "!");
568
                }
569
              else
570
                break;
571
            }
572
        }
573
 
574
      debug (9, "\n");
575
 
576
      if (!best_len)
577
        {
578
          fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
579
 
580
          for (i = 0; i < or32_num_opcodes; i++)
581
            if (ti[i].in_pass == pass)
582
              fprintf (stderr, "%s ", or32_opcodes[i].name);
583
 
584
          fprintf (stderr, "\n");
585
          exit (1);
586
        }
587
 
588
      debug (8, "%li> #### %i << %i (%i) ####\n",
589
             (long)(cur - automata), best_len, best_first, ninstr);
590
 
591
      *cur = best_first;
592
      cur++;
593
      *cur = (1 << best_len) - 1;
594
      cur++;
595
      next = cur;
596
 
597
      /* Allocate space for pointers.  */
598
      cur += 1 << best_len;
599
      cur_mask = (1 << (unsigned long) best_len) - 1;
600
 
601
      for (i = 0; i < ((unsigned) 1 << best_len); i++)
602
        {
603
          unsigned int j;
604
          unsigned long *c;
605
 
606
          curpass++;
607
          for (j = 0; j < or32_num_opcodes; j++)
608
            if (ti[j].in_pass == pass
609
                && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
610
                && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
611
              ti[j].in_pass = curpass;
612
 
613
          debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
614
          c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
615
          if (c)
616
            {
617
              debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i, (long)(cur - automata));
618
              *next = cur - automata;
619
              cur = c;
620
            }
621
          else
622
            {
623
              debug (8, "%li> N/A\n", (long)(next - automata));
624
              *next = 0;
625
            }
626
          next++;
627
        }
628
    }
629
  return cur;
630
}
631
 
632
/* Returns number of nonzero bits.  */
633
 
634
static int
635
num_ones (unsigned long value)
636
{
637
  int c = 0;
638
 
639
  while (value)
640
    {
641
      if (value & 1)
642
        c++;
643
      value >>= 1;
644
    }
645
  return c;
646
}
647
 
648
/* Utility function, which converts parameters from or32_opcode
649
   format to more binary form.  Parameters are stored in ti struct.  */
650
 
651
static struct insn_op_struct *
652
parse_params (const struct or32_opcode * opcode,
653
              struct insn_op_struct * cur)
654
{
655
  char *args = opcode->args;
656
  int i, type;
657
  int num_cur_op = 0;
658
 
659
  i = 0;
660
  type = 0;
661
  /* In case we don't have any parameters, we add dummy read from r0.  */
662
 
663
  if (!(*args))
664
    {
665
      cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
666
      cur->data = 0;
667
      debug (9, "#%08lX %08lX\n", cur->type, cur->data);
668
      cur++;
669
      return cur;
670
  }
671
 
672
  while (*args != '\0')
673
    {
674
      if (*args == 'r')
675
        {
676
          args++;
677
          type |= OPTYPE_REG;
678
    if (*args == 'D')
679
      type |= OPTYPE_DST;
680
        }
681
      //else if (ISALPHA (*args))
682
      else if (isalpha (*args))
683
        {
684
          unsigned long arg;
685
 
686
          arg = insn_extract (*args, opcode->encoding);
687
          debug (9, "%s : %08lX ------\n", opcode->name, arg);
688
          if (letter_signed (*args))
689
            {
690
              type |= OPTYPE_SIG;
691
              type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
692
            }
693
 
694
    num_cur_op = 0;
695
          /* Split argument to sequences of consecutive ones.  */
696
          while (arg)
697
            {
698
              int shr = 0;
699
              unsigned long tmp = arg, mask = 0;
700
 
701
              while ((tmp & 1) == 0)
702
                {
703
                  shr++;
704
                  tmp >>= 1;
705
                }
706
              while (tmp & 1)
707
                {
708
                  mask++;
709
                  tmp >>= 1;
710
                }
711
              cur->type = type | shr;
712
              cur->data = mask;
713
              arg &= ~(((1 << mask) - 1) << shr);
714
              debug (6, "|%08lX %08lX\n", cur->type, cur->data);
715
              cur++;
716
        num_cur_op++;
717
            }
718
          args++;
719
        }
720
      else if (*args == '(')
721
        {
722
          /* Next param is displacement.
723
             Later we will treat them as one operand.  */
724
    /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
725
     * operand */
726
    while(num_cur_op > 0) {
727
            cur[-num_cur_op].type |= type | OPTYPE_DIS;
728
      num_cur_op--;
729
    }
730
    cur[-1].type |= OPTYPE_OP;
731
          debug(9, ">%08X %08X\n", cur->type, cur->data);
732
          type = 0;
733
          i++;
734
          args++;
735
        }
736
      else if (*args == OPERAND_DELIM)
737
        {
738
          cur--;
739
          cur->type = type | cur->type | OPTYPE_OP;
740
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
741
          cur++;
742
          type = 0;
743
          i++;
744
          args++;
745
        }
746
      else if (*args == '0')
747
        {
748
          cur->type = type;
749
          cur->data = 0;
750
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
751
          cur++;
752
          type = 0;
753
          i++;
754
          args++;
755
        }
756
      else if (*args == ')')
757
        args++;
758
      else
759
        {
760
          fprintf (stderr, "%s : parse error in args.\n", opcode->name);
761
          exit (1);
762
        }
763
    }
764
 
765
  cur--;
766
  cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
767
  debug (9, "#%08lX %08lX\n", cur->type, cur->data);
768
  cur++;
769
 
770
  return cur;
771
}
772
 
773
/* Constructs new automata based on or32_opcodes array.  */
774
 
775
void
776
build_automata (void)
777
{
778
  unsigned int i;
779
  unsigned long *end;
780
  struct insn_op_struct *cur;
781
 
782
  automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
783
  ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
784
 
785
  nuncovered = or32_num_opcodes;
786
  printf ("Building automata... ");
787
  /* Build temporary information about instructions.  */
788
  for (i = 0; i < or32_num_opcodes; i++)
789
    {
790
      unsigned long ones, zeros;
791
      char *encoding = or32_opcodes[i].encoding;
792
 
793
      ones  = insn_extract('1', encoding);
794
      zeros = insn_extract('0', encoding);
795
 
796
      ti[i].insn_mask = ones | zeros;
797
      ti[i].insn = ones;
798
      ti[i].in_pass = curpass = 0;
799
 
800
      /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
801
        or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
802
    }
803
 
804
  /* Until all are covered search for best criteria to separate them.  */
805
  end = cover_insn (automata, curpass, 0xFFFFFFFF);
806
 
807
  if (end - automata > MAX_AUTOMATA_SIZE)
808
    {
809
      fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
810
      exit (1);
811
    }
812
 
813
  printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
814
  printf ("Parsing operands data... ");
815
 
816
  op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
817
  op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
818
  cur = op_data;
819
 
820
  for (i = 0; i < or32_num_opcodes; i++)
821
    {
822
      op_start[i] = cur;
823
      cur = parse_params (&or32_opcodes[i], cur);
824
 
825
      if (cur - op_data > MAX_OP_TABLE_SIZE)
826
        {
827
          fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
828
          exit (1);
829
        }
830
    }
831
  printf ("done.\n");
832
}
833
 
834
void
835
destruct_automata (void)
836
{
837
  free (ti);
838
  free (automata);
839
  free (op_data);
840
  free (op_start);
841
}
842
 
843
/* Decodes instruction and returns instruction index.  */
844
 
845
int
846
insn_decode (unsigned int insn)
847
{
848
  unsigned long *a = automata;
849
  int i;
850
 
851
  while (!(*a & LEAF_FLAG))
852
    {
853
      unsigned int first = *a;
854
 
855
      debug (9, "%li ", (long)(a - automata));
856
 
857
      a++;
858
      i = (insn >> first) & *a;
859
      a++;
860
      if (!*(a + i))
861
        {
862
          /* Invalid instruction found?  */
863
          debug (9, "XXX\n");
864
          return -1;
865
        }
866
      a = automata + *(a + i);
867
    }
868
 
869
  i = *a & ~LEAF_FLAG;
870
 
871
  debug (9, "%i\n", i);
872
 
873
  /* Final check - do we have direct match?
874
     (based on or32_opcodes this should be the only possibility,
875
     but in case of invalid/missing instruction we must perform a check)  */
876
  if ((ti[i].insn_mask & insn) == ti[i].insn)
877
    return i;
878
  else
879
    return -1;
880
}
881
 
882
static char disassembled_str[50];
883
char *disassembled = &disassembled_str[0];
884
 
885
/* Automagically does zero- or sign- extension and also finds correct
886
   sign bit position if sign extension is correct extension. Which extension
887
   is proper is figured out from letter description.  */
888
 
889
unsigned long
890
extend_imm (unsigned long imm, char l)
891
{
892
  unsigned long mask;
893
  int letter_bits;
894
 
895
  /* First truncate all bits above valid range for this letter
896
     in case it is zero extend.  */
897
  letter_bits = letter_range (l);
898
  mask = (1 << letter_bits) - 1;
899
  imm &= mask;
900
 
901
  /* Do sign extend if this is the right one.  */
902
  if (letter_signed(l) && (imm >> (letter_bits - 1)))
903
    imm |= (~mask);
904
 
905
  return imm;
906
}
907
 
908
static unsigned long
909
or32_extract (char param_ch, char *enc_initial, unsigned long insn)
910
{
911
  char *enc;
912
  unsigned long ret = 0;
913
  int opc_pos = 0;
914
  int param_pos = 0;
915
 
916
  for (enc = enc_initial; *enc != '\0'; enc++)
917
    if (*enc == param_ch)
918
      {
919
        if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
920
          continue;
921
        else
922
          param_pos++;
923
      }
924
 
925
#if DEBUG
926
  printf ("or32_extract: %x ", param_pos);
927
#endif
928
  opc_pos = 32;
929
 
930
  for (enc = enc_initial; *enc != '\0'; )
931
    if ((*enc == '0') && (*(enc + 1) == 'x'))
932
      {
933
        opc_pos -= 4;
934
        if ((param_ch == '0') || (param_ch == '1'))
935
          {
936
            unsigned long tmp = strtol (enc, NULL, 16);
937
#if DEBUG
938
            printf (" enc=%s, tmp=%x ", enc, tmp);
939
#endif
940
            if (param_ch == '0')
941
              tmp = 15 - tmp;
942
            ret |= tmp << opc_pos;
943
          }
944
        enc += 3;
945
      }
946
    else if ((*enc == '0') || (*enc == '1'))
947
      {
948
        opc_pos--;
949
        if (param_ch == *enc)
950
          ret |= 1 << opc_pos;
951
        enc++;
952
      }
953
    else if (*enc == param_ch)
954
      {
955
        opc_pos--;
956
        param_pos--;
957
#if DEBUG
958
        printf ("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
959
#endif  
960
        //if (ISLOWER (param_ch))
961
        if (islower (param_ch))
962
          ret -= ((insn >> opc_pos) & 0x1) << param_pos;
963
        else
964
          ret += ((insn >> opc_pos) & 0x1) << param_pos;
965
        enc++;
966
      }
967
  //else if (ISALPHA (*enc)) 
968
  else if (isalpha (*enc))
969
      {
970
        opc_pos--;
971
        enc++;
972
      }
973
    else if (*enc == '-')
974
      {
975
        opc_pos--;
976
        enc++;
977
      }
978
    else
979
      enc++;
980
 
981
#if DEBUG
982
  printf ("ret=%x\n", ret);
983
#endif
984
  return ret;
985
}
986
 
987
/* Print register. Used only by print_insn.  */
988
 
989
static char *
990
or32_print_register (char *dest, char param_ch, char *encoding, unsigned long insn)
991
{
992
  int regnum = or32_extract(param_ch, encoding, insn);
993
 
994
  sprintf (dest, "r%d", regnum);
995
  while (*dest) dest++;
996
  return dest;
997
}
998
 
999
/* Print immediate. Used only by print_insn.  */
1000
 
1001
static char *
1002
or32_print_immediate (char *dest, char param_ch, char *encoding, unsigned long insn)
1003
{
1004
  int imm = or32_extract (param_ch, encoding, insn);
1005
 
1006
  imm = extend_imm (imm, param_ch);
1007
 
1008
  if (letter_signed (param_ch))
1009
    {
1010
      if (imm < 0)
1011
        sprintf (dest, "%d", imm);
1012
      else
1013
        sprintf (dest, "0x%x", imm);
1014
    }
1015
  else
1016
    sprintf (dest, "%#x", imm);
1017
  while (*dest) dest++;
1018
  return dest;
1019
}
1020
 
1021
/* Disassemble one instruction from insn index.
1022
   Return the size of the instruction.  */
1023
 
1024
int
1025
disassemble_index (insn, index)
1026
     unsigned long insn;
1027
     int index;
1028
{
1029
  char *dest = disassembled;
1030
 
1031
  if (index >= 0)
1032
    {
1033
      struct or32_opcode const *opcode = &or32_opcodes[index];
1034
      char *s;
1035
 
1036
      strcpy (dest, opcode->name);
1037
      while (*dest) dest++;
1038
      *dest++ = ' ';
1039
      *dest = 0;
1040
 
1041
      for (s = opcode->args; *s != '\0'; ++s)
1042
        {
1043
          switch (*s)
1044
            {
1045
            case '\0':
1046
              return insn_len (insn);
1047
 
1048
            case 'r':
1049
              dest = or32_print_register(dest, *++s, opcode->encoding, insn);
1050
              break;
1051
 
1052
            default:
1053
              if (strchr (opcode->encoding, *s))
1054
                dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
1055
              else {
1056
                *dest++ = *s;
1057
                *dest = 0;
1058
              }
1059
            }
1060
        }
1061
    }
1062
  else
1063
    {
1064
      /* This used to be %8x for binutils.  */
1065
      sprintf(dest, ".word 0x%08lx", insn);
1066
      while (*dest) dest++;
1067
    }
1068
 
1069
  return insn_len (insn);
1070
}
1071
 
1072
/* Disassemble one instruction from insn to disassemble.
1073
   Return the size of the instruction.  */
1074
 
1075
int
1076
disassemble_insn (unsigned long insn)
1077
{
1078
  return disassemble_index (insn, insn_decode (insn));
1079
}
1080
 

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