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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [devs/] [eth/] [powerpc/] [quicc/] [v2_0/] [src/] [if_quicc.c] - Blame information for rev 365

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//==========================================================================
2
//
3
//      dev/if_quicc.c
4
//
5
//      Ethernet device driver for PowerPC QUICC (MPC8xx) boards
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
// Copyright (C) 2002 Gary Thomas
13
// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later version.
18
//
19
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22
// for more details.
23
//
24
// You should have received a copy of the GNU General Public License along
25
// with eCos; if not, write to the Free Software Foundation, Inc.,
26
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27
//
28
// As a special exception, if other files instantiate templates or use macros
29
// or inline functions from this file, or you compile this file and link it
30
// with other works to produce a work based on this file, this file does not
31
// by itself cause the resulting work to be covered by the GNU General Public
32
// License. However the source code for this file must still be made available
33
// in accordance with section (3) of the GNU General Public License.
34
//
35
// This exception does not invalidate any other reasons why a work based on
36
// this file might be covered by the GNU General Public License.
37
//
38
// Alternative licenses for eCos may be arranged by contacting the copyright
39
// holders.
40
// -------------------------------------------
41
//####ECOSGPLCOPYRIGHTEND####
42
//####BSDCOPYRIGHTBEGIN####
43
//
44
// -------------------------------------------
45
//
46
// Portions of this software may have been derived from OpenBSD or other sources,
47
// and are covered by the appropriate copyright disclaimers included herein.
48
//
49
// -------------------------------------------
50
//
51
//####BSDCOPYRIGHTEND####
52
//==========================================================================
53
//#####DESCRIPTIONBEGIN####
54
//
55
// Author(s):    gthomas
56
// Contributors: gthomas, nickg
57
// Date:         2000-01-10
58
// Purpose:      
59
// Description:  hardware driver for MPC8xx QUICC
60
//              
61
//
62
//####DESCRIPTIONEND####
63
//
64
//==========================================================================
65
 
66
// Ethernet device driver for MPC8xx QUICC
67
 
68
#include <pkgconf/system.h>
69
#include <pkgconf/devs_eth_powerpc_quicc.h>
70
#include <pkgconf/io_eth_drivers.h>
71
 
72
#ifdef CYGPKG_NET
73
#include <pkgconf/net.h>
74
#endif
75
 
76
#include <cyg/infra/cyg_type.h>
77
#include <cyg/infra/diag.h>
78
 
79
#include <cyg/hal/hal_arch.h>
80
#include <cyg/hal/hal_cache.h>
81
#include <cyg/hal/hal_intr.h>
82
#include <cyg/hal/drv_api.h>
83
 
84
#include <cyg/io/eth/netdev.h>
85
#include <cyg/io/eth/eth_drv.h>
86
 
87
#include "quicc_eth.h"
88
 
89
static unsigned char quicc_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM]
90
                                     [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
91
static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM]
92
                                     [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
93
 
94
static struct quicc_eth_info quicc_eth0_info;
95
static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8};
96
static unsigned char enaddr[6];
97
#ifdef CYGPKG_REDBOOT
98
#include <pkgconf/redboot.h>
99
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
100
#include <redboot.h>
101
#include <flash_config.h>
102
RedBoot_config_option("Network hardware address [MAC]",
103
                      quicc_esa,
104
                      ALWAYS_ENABLED, true,
105
                      CONFIG_ESA, 0
106
    );
107
#endif
108
#endif
109
 
110
// For fetching the ESA from RedBoot
111
#include <cyg/hal/hal_if.h>
112
#ifndef CONFIG_ESA
113
#define CONFIG_ESA 6
114
#endif
115
 
116
ETH_DRV_SC(quicc_eth0_sc,
117
           &quicc_eth0_info,   // Driver specific data
118
           "eth0",             // Name for this interface
119
           quicc_eth_start,
120
           quicc_eth_stop,
121
           quicc_eth_control,
122
           quicc_eth_can_send,
123
           quicc_eth_send,
124
           quicc_eth_recv,
125
           quicc_eth_deliver,
126
           quicc_eth_int,
127
           quicc_eth_int_vector);
128
 
129
NETDEVTAB_ENTRY(quicc_netdev,
130
                "quicc_eth",
131
                quicc_eth_init,
132
                &quicc_eth0_sc);
133
 
134
// LED activity [exclusive of hardware bits]
135
#ifndef _get_led
136
#define _get_led()  
137
#define _set_led(v) 
138
#endif
139
#ifndef LED_TxACTIVE
140
#define LED_TxACTIVE  7
141
#define LED_RxACTIVE  6
142
#define LED_IntACTIVE 5
143
#endif
144
 
145
static void
146
set_led(int bit)
147
{
148
  _set_led(_get_led() | (1<<bit));
149
}
150
 
151
static void
152
clear_led(int bit)
153
{
154
  _set_led(_get_led() & ~(1<<bit));
155
}
156
 
157
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
158
static cyg_interrupt quicc_eth_interrupt;
159
static cyg_handle_t  quicc_eth_interrupt_handle;
160
#endif
161
static void          quicc_eth_int(struct eth_drv_sc *data);
162
 
163
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
164
// This ISR is called when the ethernet interrupt occurs
165
static int
166
quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
167
{
168
    cyg_drv_interrupt_mask(QUICC_ETH_INT);
169
    cyg_drv_interrupt_acknowledge(QUICC_ETH_INT);
170
    return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
171
}
172
#endif
173
 
174
// Deliver function (ex-DSR) handles the ethernet [logical] processing
175
static void
176
quicc_eth_deliver(struct eth_drv_sc * sc)
177
{
178
    quicc_eth_int(sc);
179
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
180
    // Allow interrupts to happen again
181
    cyg_drv_interrupt_unmask(QUICC_ETH_INT);
182
#endif
183
}
184
 
185
//
186
// Initialize the interface - performed at system startup
187
// This function must set up the interface, including arranging to
188
// handle interrupts, etc, so that it may be "started" cheaply later.
189
//
190
static bool
191
quicc_eth_init(struct cyg_netdevtab_entry *tab)
192
{
193
    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
194
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
195
    volatile EPPC *eppc = (volatile EPPC *)eppc_base();
196
    struct cp_bufdesc *rxbd, *txbd;
197
    unsigned char *RxBUF, *TxBUF, *ep, *ap;
198
    volatile struct ethernet_pram *enet_pram;
199
    volatile struct scc_regs *scc;
200
    int TxBD, RxBD;
201
    int cache_state;
202
    int i;
203
    bool esa_ok = false;
204
 
205
#ifdef QUICC_ETH_FETCH_ESA
206
    QUICC_ETH_FETCH_ESA(esa_ok);
207
#endif
208
 
209
    if (!esa_ok) {
210
#if defined(CYGPKG_REDBOOT) && \
211
    defined(CYGSEM_REDBOOT_FLASH_CONFIG)
212
        esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA);
213
#else
214
        esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
215
                                             "quicc_esa", enaddr, CONFIG_ESA);
216
#endif
217
        if (!esa_ok) {
218
            // Can't figure out ESA
219
            diag_printf("QUICC_ETH - Warning! ESA unknown\n");
220
            memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
221
        }
222
    }
223
 
224
    // Ensure consistent state between cache and what the QUICC sees
225
    HAL_DCACHE_IS_ENABLED(cache_state);
226
    HAL_DCACHE_SYNC();
227
    HAL_DCACHE_DISABLE();
228
 
229
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
230
    // Set up to handle interrupts
231
    cyg_drv_interrupt_create(QUICC_ETH_INT,
232
                             CYGARC_SIU_PRIORITY_HIGH,
233
                             (cyg_addrword_t)sc, //  Data item passed to interrupt handler
234
                             (cyg_ISR_t *)quicc_eth_isr,
235
                             (cyg_DSR_t *)eth_drv_dsr,
236
                             &quicc_eth_interrupt_handle,
237
                             &quicc_eth_interrupt);
238
    cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
239
    cyg_drv_interrupt_acknowledge(QUICC_ETH_INT);
240
    cyg_drv_interrupt_unmask(QUICC_ETH_INT);
241
#endif
242
 
243
    qi->pram = enet_pram = &eppc->pram[QUICC_ETH_SCC].enet_scc;
244
    qi->ctl = scc = &eppc->scc_regs[QUICC_ETH_SCC];  // Use SCCx
245
 
246
    // Shut down ethernet, in case it is already running
247
    scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
248
 
249
    memset((void *)enet_pram, 0, sizeof(*enet_pram));
250
 
251
    TxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc));
252
    RxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM * sizeof(struct cp_bufdesc));
253
 
254
    txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
255
    rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
256
    qi->tbase = txbd;
257
    qi->txbd = txbd;
258
    qi->tnext = txbd;
259
    qi->rbase = rxbd;
260
    qi->rxbd = rxbd;
261
    qi->rnext = rxbd;
262
    qi->txactive = 0;
263
 
264
    RxBUF = &quicc_eth_rxbufs[0][0];
265
    TxBUF = &quicc_eth_txbufs[0][0];
266
 
267
    // setup buffer descriptors
268
    for (i = 0;  i < CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM;  i++) {
269
        rxbd->length = 0;
270
        rxbd->buffer = RxBUF;
271
        rxbd->ctrl   = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
272
        RxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
273
        rxbd++;
274
    }
275
    rxbd--;
276
    rxbd->ctrl |= QUICC_BD_CTL_Wrap;  // Last buffer
277
    for (i = 0;  i < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM;  i++) {
278
        txbd->length = 0;
279
        txbd->buffer = TxBUF;
280
        txbd->ctrl   = 0;
281
        TxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
282
        txbd++;
283
    }
284
    txbd--;
285
    txbd->ctrl |= QUICC_BD_CTL_Wrap;  // Last buffer
286
 
287
    // Set up parallel ports for connection to ethernet tranceiver
288
    eppc->pio_papar |= (QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
289
    eppc->pio_padir &= ~(QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
290
    eppc->pio_paodr &= ~QUICC_ETH_PA_TXD;
291
 
292
    eppc->pio_pcpar &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
293
    eppc->pio_pcdir &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
294
    eppc->pio_pcso  |= (QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
295
 
296
    eppc->pio_papar |= (QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
297
    eppc->pio_padir &= ~(QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
298
 
299
    // Set up clock routing
300
    eppc->si_sicr &= ~QUICC_ETH_SICR_MASK;
301
    eppc->si_sicr |= QUICC_ETH_SICR_ENET;
302
    eppc->si_sicr &= ~QUICC_ETH_SICR_ENABLE;
303
 
304
    // Set up DMA mode
305
    eppc->dma_sdcr = 0x0001;
306
 
307
    // Initialize shared PRAM
308
    enet_pram->rbase = RxBD;
309
    enet_pram->tbase = TxBD;
310
 
311
    // Set Big Endian mode
312
    enet_pram->rfcr = QUICC_SCC_FCR_BE;
313
    enet_pram->tfcr = QUICC_SCC_FCR_BE;
314
 
315
    // Size of receive buffers
316
    enet_pram->mrblr = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
317
 
318
    // Initialize CRC calculations
319
    enet_pram->c_pres = 0xFFFFFFFF;
320
    enet_pram->c_mask = 0xDEBB20E3;  // Actual CRC formula
321
    enet_pram->crcec = 0;
322
    enet_pram->alec = 0;
323
    enet_pram->disfc = 0;
324
 
325
    // Frame padding
326
    enet_pram->pads = 0x8888;
327
    enet_pram->pads = 0x0000;
328
 
329
    // Retries
330
    enet_pram->ret_lim = 15;
331
    enet_pram->ret_cnt = 0;
332
 
333
    // Frame sizes
334
    enet_pram->mflr = IEEE_8023_MAX_FRAME;
335
    enet_pram->minflr = IEEE_8023_MIN_FRAME;
336
    enet_pram->maxd1 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
337
    enet_pram->maxd2 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
338
 
339
    // Group address hash
340
    enet_pram->gaddr1 = 0;
341
    enet_pram->gaddr2 = 0;
342
    enet_pram->gaddr3 = 0;
343
    enet_pram->gaddr4 = 0;
344
 
345
    // Device physical address
346
    ep = &enaddr[sizeof(enaddr)];
347
    ap = (unsigned char *)&enet_pram->paddr_h;
348
    for (i = 0;  i < sizeof(enaddr);  i++) {
349
        *ap++ = *--ep;
350
    }
351
 
352
    // Persistence counter
353
    enet_pram->p_per = 0;
354
 
355
    // Individual address filter
356
    enet_pram->iaddr1 = 0;
357
    enet_pram->iaddr2 = 0;
358
    enet_pram->iaddr3 = 0;
359
    enet_pram->iaddr4 = 0;
360
 
361
    // Temp address
362
    enet_pram->taddr_h = 0;
363
    enet_pram->taddr_m = 0;
364
    enet_pram->taddr_l = 0;
365
 
366
    // Initialize the CPM (set up buffer pointers, etc).
367
    eppc->cp_cr = QUICC_CPM_SCCx | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
368
    while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
369
 
370
    // Clear any pending interrupt/exceptions
371
    scc->scc_scce = 0xFFFF;
372
 
373
    // Enable interrupts
374
    scc->scc_sccm = QUICC_SCCE_INTS | QUICC_SCCE_GRC | QUICC_SCCE_BSY;
375
 
376
    // Set up SCCx to run in ethernet mode
377
    scc->scc_gsmr_h = 0;
378
    scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
379
        QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
380
 
381
    // Sync delimiters
382
    scc->scc_dsr = 0xD555;
383
 
384
    // Protocol specifics (as if GSML wasn't enough)
385
    scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
386
        QUICC_PMSR_RCV_SHORT_FRAMES;
387
 
388
#ifdef QUICC_ETH_ENABLE
389
    QUICC_ETH_ENABLE();
390
#endif
391
 
392
#ifdef QUICC_ETH_RESET_PHY
393
    QUICC_ETH_RESET_PHY();
394
#endif
395
 
396
    // Enable ethernet interface
397
#ifdef QUICC_ETH_PC_Tx_ENABLE
398
    eppc->pio_pcpar |= QUICC_ETH_PC_Tx_ENABLE;
399
    eppc->pio_pcdir &= ~QUICC_ETH_PC_Tx_ENABLE;
400
#else
401
    eppc->pip_pbpar |= QUICC_ETH_PB_Tx_ENABLE;
402
    eppc->pip_pbdir |= QUICC_ETH_PB_Tx_ENABLE;
403
#endif
404
 
405
    if (cache_state)
406
        HAL_DCACHE_ENABLE();
407
 
408
    // Initialize upper level driver
409
    (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
410
 
411
    // Set LED state
412
    clear_led(LED_TxACTIVE);
413
    clear_led(LED_RxACTIVE);
414
 
415
    return true;
416
}
417
 
418
//
419
// This function is called to shut down the interface.
420
//
421
static void
422
quicc_eth_stop(struct eth_drv_sc *sc)
423
{
424
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
425
    volatile struct scc_regs *scc = qi->ctl;
426
 
427
    // Disable the device!
428
    scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
429
}
430
 
431
//
432
// This function is called to "start up" the interface.  It may be called
433
// multiple times, even when the hardware is already running.  It will be
434
// called whenever something "hardware oriented" changes and should leave
435
// the hardware ready to send/receive packets.
436
//
437
static void
438
quicc_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
439
{
440
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
441
    volatile struct scc_regs *scc = qi->ctl;
442
 
443
    // Enable the device!
444
    scc->scc_gsmr_l |= QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT;
445
}
446
 
447
//
448
// This function is called for low level "control" operations
449
//
450
static int
451
quicc_eth_control(struct eth_drv_sc *sc, unsigned long key,
452
                  void *data, int length)
453
{
454
    switch (key) {
455
    case ETH_DRV_SET_MAC_ADDRESS:
456
        return 0;
457
        break;
458
 
459
#ifdef ETH_DRV_GET_IF_STATS
460
    case ETH_DRV_GET_IF_STATS:
461
    {
462
        struct ether_drv_stats *p = (struct ether_drv_stats *)data;
463
        struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
464
 
465
        strcpy( p->description, "QUICC (MPC8xx) SCC Ethernet" );
466
        CYG_ASSERT( 48 > strlen(p->description), "Description too long" );
467
 
468
        // Really need to determine the following values properly, for
469
        // now just assume the link is up, full duplex, unknown speed.
470
 
471
        p->operational = 3;            // LINK UP
472
        p->duplex = 1;
473
        p->speed = 0;
474
 
475
        {
476
            p->supports_dot3        = false;
477
 
478
            // Those commented out are not available on this chip.
479
 
480
            p->tx_good              = qi->tx_good             ;
481
            //p->tx_max_collisions    = qi->tx_max_collisions ;
482
            p->tx_late_collisions   = qi->tx_late_collisions  ;
483
            p->tx_underrun          = qi->tx_underrun         ;
484
            p->tx_carrier_loss      = qi->tx_carrier_loss     ;
485
            p->tx_deferred          = qi->tx_deferred         ;
486
            //p->tx_sqetesterrors   = qi->tx_sqetesterrors    ;
487
            //p->tx_single_collisions = qi->tx_single_collisions;
488
            //p->tx_mult_collisions   = qi->tx_mult_collisions  ;
489
            //p->tx_total_collisions  = qi->tx_total_collisions ;
490
            p->rx_good              = qi->rx_good             ;
491
            p->rx_crc_errors        = qi->rx_crc_errors       ;
492
            p->rx_align_errors      = qi->rx_align_errors     ;
493
            p->rx_resource_errors   = qi->rx_resource_errors  ;
494
            p->rx_overrun_errors    = qi->rx_overrun_errors   ;
495
            p->rx_collisions        = qi->rx_collisions       ;
496
            p->rx_short_frames      = qi->rx_short_frames     ;
497
            p->rx_too_long_frames   = qi->rx_long_frames      ;
498
            //p->rx_symbol_errors   = qi->rx_symbol_errors    ;
499
 
500
            p->interrupts           = qi->interrupts          ;
501
            p->rx_count             = qi->rx_count            ;
502
            p->rx_deliver           = qi->rx_deliver          ;
503
            p->rx_resource          = qi->rx_resource         ;
504
            p->rx_restart           = qi->rx_restart          ;
505
            p->tx_count             = qi->tx_count            ;
506
            p->tx_complete          = qi->tx_complete         ;
507
            p->tx_dropped           = qi->tx_dropped          ;
508
        }
509
 
510
        p->tx_queue_len = CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM;
511
 
512
        return 0; // OK
513
    }
514
#endif
515
 
516
 
517
    default:
518
        return 1;
519
        break;
520
    }
521
}
522
 
523
//
524
// This function is called to see if another packet can be sent.
525
// It should return the number of packets which can be handled.
526
// Zero should be returned if the interface is busy and can not send any more.
527
//
528
static int
529
quicc_eth_can_send(struct eth_drv_sc *sc)
530
{
531
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
532
 
533
    return (qi->txactive < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM);
534
}
535
 
536
//
537
// This routine is called to send data to the hardware.
538
static void
539
quicc_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
540
               int total_len, unsigned long key)
541
{
542
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
543
    volatile struct cp_bufdesc *txbd, *txfirst;
544
    volatile char *bp;
545
    int i, txindex, cache_state;
546
    unsigned int ctrl;
547
 
548
    qi->tx_count++;
549
 
550
    // Find a free buffer
551
    txbd = txfirst = qi->txbd;
552
    if ((txbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int )))
553
#ifdef CYGPKG_NET
554
            panic ("No free xmit buffers");
555
#else
556
            diag_printf("QUICC Ethernet: No free xmit buffers\n");
557
#endif
558
 
559
    // Remember the next buffer to try
560
    if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
561
        qi->txbd = qi->tbase;
562
    } else {
563
        qi->txbd = txbd+1;
564
    }
565
    txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
566
    qi->txkey[txindex] = key;
567
    // Set up buffer
568
    txbd->length = total_len;
569
    bp = txbd->buffer;
570
    for (i = 0;  i < sg_len;  i++) {
571
        memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
572
        bp += sg_list[i].len;
573
    }
574
    // Note: the MPC8xx does not seem to snoop/invalidate the data cache properly!
575
    HAL_DCACHE_IS_ENABLED(cache_state);
576
    if (cache_state) {
577
        HAL_DCACHE_FLUSH(txbd->buffer, txbd->length);  // Make sure no stale data
578
    }
579
    // Send it on it's way
580
    ctrl = txbd->ctrl & ~QUICC_BD_TX_PAD;
581
    if (txbd->length < IEEE_8023_MIN_FRAME) {
582
        ctrl |= QUICC_BD_TX_PAD;
583
    }
584
    txbd->ctrl = ctrl | QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int |
585
        QUICC_BD_TX_LAST | QUICC_BD_TX_TC;
586
    qi->txactive++;
587
    set_led(LED_TxACTIVE);
588
}
589
 
590
//
591
// This function is called when a packet has been received.  It's job is
592
// to prepare to unload the packet from the hardware.  Once the length of
593
// the packet is known, the upper layer of the driver can be told.  When
594
// the upper layer is ready to unload the packet, the internal function
595
// 'quicc_eth_recv' will be called to actually fetch it from the hardware.
596
//
597
static void
598
quicc_eth_RxEvent(struct eth_drv_sc *sc)
599
{
600
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
601
    volatile struct cp_bufdesc *rxbd;
602
 
603
 
604
    rxbd = qi->rnext;
605
    while ((rxbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
606
 
607
        qi->rx_count++;
608
 
609
        if( rxbd->ctrl & QUICC_BD_RX_MISS )
610
        {
611
            qi->rx_miss++;
612
        }
613
        if( rxbd->ctrl & QUICC_BD_RX_LG )
614
        {
615
            qi->rx_long_frames++;
616
        }
617
        if( rxbd->ctrl & QUICC_BD_RX_NO )
618
        {
619
            qi->rx_align_errors++;
620
        }
621
        if( rxbd->ctrl & QUICC_BD_RX_SH )
622
        {
623
            qi->rx_short_frames++;
624
        }
625
        if( rxbd->ctrl & QUICC_BD_RX_CR )
626
        {
627
            qi->rx_crc_errors++;
628
        }
629
        if( rxbd->ctrl & QUICC_BD_RX_OV )
630
        {
631
            qi->rx_overrun_errors++;
632
        }
633
 
634
        if( rxbd->ctrl & QUICC_BD_RX_CL )
635
        {
636
            qi->rx_collisions++;
637
        }
638
 
639
        if( (rxbd->ctrl & QUICC_BD_RX_ERRORS) == 0 )
640
        {
641
            qi->rx_good++;
642
 
643
            // OK frame - Prepare for callback
644
            qi->rxbd = rxbd;  // Save for callback
645
            set_led(LED_RxACTIVE);
646
 
647
            (sc->funs->eth_drv->recv)(sc, rxbd->length);
648
 
649
            clear_led(LED_RxACTIVE);
650
        }
651
 
652
 
653
        // Clear flags and wrap if needed else step up BD pointer 
654
        if (rxbd->ctrl & QUICC_BD_CTL_Wrap)
655
        {
656
            rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int | QUICC_BD_CTL_Wrap;
657
            rxbd = qi->rbase;
658
        }
659
        else
660
        {
661
            rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
662
            rxbd++;
663
        }
664
 
665
    }
666
    // Remember where we left off
667
    qi->rnext = (struct cp_bufdesc *)rxbd;
668
}
669
 
670
//
671
// This function is called as a result of the "eth_drv_recv()" call above.
672
// It's job is to actually fetch data for a packet from the hardware once
673
// memory buffers have been allocated for the packet.  Note that the buffers
674
// may come in pieces, using a scatter-gather list.  This allows for more
675
// efficient processing in the upper layers of the stack.
676
//
677
static void
678
quicc_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
679
{
680
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
681
    unsigned char *bp;
682
    int i, cache_state;
683
    int sg_list_null_buffer = 0;
684
 
685
    bp = (unsigned char *)qi->rxbd->buffer;
686
    // Note: the MPC8xx does not seem to snoop/invalidate the data cache properly!
687
    HAL_DCACHE_IS_ENABLED(cache_state);
688
    if (cache_state) {
689
        HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length);  // Make sure no stale data
690
    }
691
    for (i = 0;  i < sg_len;  i++) {
692
        if (sg_list[i].buf != 0) {
693
            memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
694
            bp += sg_list[i].len;
695
        }
696
        else
697
            sg_list_null_buffer = 1;
698
    }
699
 
700
    // A NULL sg_list buffer usually means no mbufs, so we don't count
701
    // it as a delivery, instead we count it as a resource error.
702
 
703
    if (!sg_list_null_buffer)
704
        qi->rx_deliver++;
705
    else
706
        qi->rx_resource++;
707
 
708
}
709
 
710
 
711
static void
712
quicc_eth_command( struct eth_drv_sc *sc, unsigned long cmd)
713
{
714
   volatile EPPC *eppc = (volatile EPPC *)eppc_base();
715
 
716
   eppc->cp_cr = QUICC_CPM_SCCx | cmd | QUICC_CPM_CR_BUSY;
717
 
718
   while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
719
       continue;
720
}
721
 
722
static void
723
quicc_eth_TxEvent(struct eth_drv_sc *sc, int stat)
724
{
725
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
726
    volatile struct cp_bufdesc *txbd;
727
    int txindex;
728
    bool restart = false;
729
 
730
    txbd = qi->tnext;
731
 
732
    while ((txbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
733
 
734
        txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
735
 
736
        qi->tx_complete++;
737
 
738
        (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
739
        txbd->ctrl &= ~QUICC_BD_CTL_Int;  // Reset int pending bit
740
 
741
        if (txbd->ctrl & QUICC_BD_TX_LC )
742
            qi->tx_late_collisions++, restart = true;
743
        if (txbd->ctrl & QUICC_BD_TX_RL )
744
            qi->tx_retransmit_error++, restart = true;
745
        if (txbd->ctrl & QUICC_BD_TX_UN )
746
            qi->tx_underrun++, restart = true;
747
        if (txbd->ctrl & QUICC_BD_TX_CSL )
748
            qi->tx_carrier_loss++;
749
        if (txbd->ctrl & QUICC_BD_TX_HB )
750
            qi->tx_heartbeat_loss++;
751
        if (txbd->ctrl & QUICC_BD_TX_DEF )
752
            qi->tx_deferred++;
753
 
754
        if( (txbd->ctrl & QUICC_BD_TX_ERRORS) == 0 )
755
            qi->tx_good++;
756
 
757
 
758
        if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
759
            txbd->ctrl = QUICC_BD_CTL_Wrap;
760
            txbd = qi->tbase;
761
        } else {
762
            txbd->ctrl = 0;
763
            txbd++;
764
        }
765
        qi->txactive--;
766
    }
767
 
768
    if (qi->txactive == 0) {
769
        clear_led(LED_TxACTIVE);
770
    }
771
 
772
    // Remember where we left off
773
    qi->tnext = (struct cp_bufdesc *)txbd;
774
 
775
    if (restart)
776
    {
777
        quicc_eth_command(sc,QUICC_CPM_CR_RESTART_TX);
778
        qi->tx_restart++;
779
    }
780
 
781
}
782
 
783
//
784
// Interrupt processing
785
//
786
static void
787
quicc_eth_int(struct eth_drv_sc *sc)
788
{
789
    struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
790
    volatile struct scc_regs *scc = qi->ctl;
791
    unsigned short scce;
792
 
793
    qi->interrupts++;
794
 
795
    while ( (scce = scc->scc_scce) != 0 )
796
    {
797
        scc->scc_scce = scce;
798
 
799
        if ( (scce & (QUICC_SCCE_TXE | QUICC_SCCE_TX)) != 0)
800
        {
801
            quicc_eth_TxEvent(sc, scce);
802
        }
803
        if ( (scce & ( QUICC_SCCE_RXF | QUICC_SCCE_RX )) != 0)
804
        {
805
            quicc_eth_RxEvent(sc);
806
        }
807
        if ( (scce & QUICC_SCCE_BSY) != 0)
808
        {
809
            qi->rx_resource_errors++;
810
        }
811
        if ( (scce & QUICC_SCCE_GRC) != 0 )
812
        {
813
            quicc_eth_command(sc, QUICC_CPM_CR_RESTART_TX);
814
            qi->tx_restart++;
815
            quicc_eth_command(sc, QUICC_CPM_CR_HUNT_MODE);
816
            qi->rx_restart++;
817
        }
818
    }
819
}
820
 
821
//
822
// Interrupt vector
823
//
824
static int
825
quicc_eth_int_vector(struct eth_drv_sc *sc)
826
{
827
    return (QUICC_ETH_INT);
828
}

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