| 1 |
27 |
unneback |
//==========================================================================
|
| 2 |
|
|
//
|
| 3 |
|
|
// hal_pxa2x0.h
|
| 4 |
|
|
//
|
| 5 |
|
|
// HAL misc board support definitions for PXA250/210
|
| 6 |
|
|
//
|
| 7 |
|
|
//==========================================================================
|
| 8 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
// -------------------------------------------
|
| 10 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 12 |
|
|
//
|
| 13 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 16 |
|
|
//
|
| 17 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 18 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 19 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 20 |
|
|
// for more details.
|
| 21 |
|
|
//
|
| 22 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 23 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 24 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 25 |
|
|
//
|
| 26 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 27 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 28 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 29 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 30 |
|
|
// License. However the source code for this file must still be made available
|
| 31 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 32 |
|
|
//
|
| 33 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 34 |
|
|
// this file might be covered by the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 37 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 38 |
|
|
// -------------------------------------------
|
| 39 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 40 |
|
|
//==========================================================================
|
| 41 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 42 |
|
|
//
|
| 43 |
|
|
// Author(s): <knud.woehler@microplex.de>
|
| 44 |
|
|
// Date: 2003-01-06
|
| 45 |
|
|
//
|
| 46 |
|
|
//####DESCRIPTIONEND####
|
| 47 |
|
|
//
|
| 48 |
|
|
//==========================================================================
|
| 49 |
|
|
#ifndef CYGONCE_HAL_ARM_PXA2X0_H
|
| 50 |
|
|
#define CYGONCE_HAL_ARM_PXA2X0_H
|
| 51 |
|
|
|
| 52 |
|
|
#include <pkgconf/system.h>
|
| 53 |
|
|
#include <cyg/hal/hal_xscale.h>
|
| 54 |
|
|
|
| 55 |
|
|
#ifdef __ASSEMBLER__
|
| 56 |
|
|
#define PXA2X0_REGISTER(a) (a)
|
| 57 |
|
|
#else
|
| 58 |
|
|
#define PXA2X0_REGISTER(a) ((volatile unsigned long *)(a))
|
| 59 |
|
|
#endif
|
| 60 |
|
|
|
| 61 |
|
|
// Memory layout
|
| 62 |
|
|
#define PXA2X0_CS0_BASE (0x00000000)
|
| 63 |
|
|
#define PXA2X0_CS1_BASE (0x04000000)
|
| 64 |
|
|
#define PXA2X0_CS2_BASE (0x08000000)
|
| 65 |
|
|
#define PXA2X0_CS3_BASE (0x0c000000)
|
| 66 |
|
|
#define PXA2X0_CS4_BASE (0x10000000)
|
| 67 |
|
|
#define PXA2X0_CS5_BASE (0x14000000)
|
| 68 |
|
|
|
| 69 |
|
|
#define PXA2X0_PCMCIA0_BASE (0x20000000)
|
| 70 |
|
|
#define PXA2X0_PCMCIA1_BASE (0x30000000)
|
| 71 |
|
|
|
| 72 |
|
|
#define PXA2X0_PERIPHERALS_BASE (0x40000000)
|
| 73 |
|
|
#define PXA2X0_LCD_BASE (0x44000000)
|
| 74 |
|
|
#define PXA2X0_MEMORY_CTL_BASE (0x48000000)
|
| 75 |
|
|
|
| 76 |
|
|
#define PXA2X0_RAM_BANK0_BASE (0xA0000000)
|
| 77 |
|
|
#define PXA2X0_RAM_BANK1_BASE (0xA4000000)
|
| 78 |
|
|
#define PXA2X0_RAM_BANK2_BASE (0xA8000000)
|
| 79 |
|
|
#define PXA2X0_RAM_BANK3_BASE (0xAc000000)
|
| 80 |
|
|
|
| 81 |
|
|
#define PXA2X0_CACHE_FLUSH_BASE (0xc0000000)
|
| 82 |
|
|
|
| 83 |
|
|
#define DCACHE_FLUSH_AREA 0xc0000000
|
| 84 |
|
|
|
| 85 |
|
|
// DMA Controller
|
| 86 |
|
|
#define PXA2X0_DMA_CTL_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0000000 )
|
| 87 |
|
|
#define PXA2X0_DCSR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0000 )
|
| 88 |
|
|
#define PXA2X0_DCSR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0004 )
|
| 89 |
|
|
#define PXA2X0_DCSR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0008 )
|
| 90 |
|
|
#define PXA2X0_DCSR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x000c )
|
| 91 |
|
|
#define PXA2X0_DCSR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0010 )
|
| 92 |
|
|
#define PXA2X0_DCSR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0014 )
|
| 93 |
|
|
#define PXA2X0_DCSR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0018 )
|
| 94 |
|
|
#define PXA2X0_DCSR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x001c )
|
| 95 |
|
|
#define PXA2X0_DCSR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0020 )
|
| 96 |
|
|
#define PXA2X0_DCSR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0024 )
|
| 97 |
|
|
#define PXA2X0_DCSR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0028 )
|
| 98 |
|
|
#define PXA2X0_DCSR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x002c )
|
| 99 |
|
|
#define PXA2X0_DCSR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0030 )
|
| 100 |
|
|
#define PXA2X0_DCSR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0034 )
|
| 101 |
|
|
#define PXA2X0_DCSR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0038 )
|
| 102 |
|
|
#define PXA2X0_DCSR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x003c )
|
| 103 |
|
|
#define PXA2X0_DINT PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x00f0 )
|
| 104 |
|
|
#define PXA2X0_DRCMR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0100 )
|
| 105 |
|
|
#define PXA2X0_DRCMR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0104 )
|
| 106 |
|
|
#define PXA2X0_DRCMR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0108 )
|
| 107 |
|
|
#define PXA2X0_DRCMR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x010c )
|
| 108 |
|
|
#define PXA2X0_DRCMR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0110 )
|
| 109 |
|
|
#define PXA2X0_DRCMR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0114 )
|
| 110 |
|
|
#define PXA2X0_DRCMR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0118 )
|
| 111 |
|
|
#define PXA2X0_DRCMR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x011c )
|
| 112 |
|
|
#define PXA2X0_DRCMR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0120 )
|
| 113 |
|
|
#define PXA2X0_DRCMR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0124 )
|
| 114 |
|
|
#define PXA2X0_DRCMR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0128 )
|
| 115 |
|
|
#define PXA2X0_DRCMR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x012c )
|
| 116 |
|
|
#define PXA2X0_DRCMR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0130 )
|
| 117 |
|
|
#define PXA2X0_DRCMR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0134 )
|
| 118 |
|
|
#define PXA2X0_DRCMR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0138 )
|
| 119 |
|
|
#define PXA2X0_DRCMR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x013c )
|
| 120 |
|
|
#define PXA2X0_DRCMR16 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0140 )
|
| 121 |
|
|
#define PXA2X0_DRCMR17 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0144 )
|
| 122 |
|
|
#define PXA2X0_DRCMR18 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0148 )
|
| 123 |
|
|
#define PXA2X0_DRCMR19 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x014c )
|
| 124 |
|
|
#define PXA2X0_DRCMR20 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0150 )
|
| 125 |
|
|
#define PXA2X0_DRCMR21 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0154 )
|
| 126 |
|
|
#define PXA2X0_DRCMR22 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0158 )
|
| 127 |
|
|
#define PXA2X0_DRCMR23 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x015c )
|
| 128 |
|
|
#define PXA2X0_DRCMR24 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0160 )
|
| 129 |
|
|
#define PXA2X0_DRCMR25 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0164 )
|
| 130 |
|
|
#define PXA2X0_DRCMR26 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0168 )
|
| 131 |
|
|
#define PXA2X0_DRCMR27 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x016c )
|
| 132 |
|
|
#define PXA2X0_DRCMR28 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0170 )
|
| 133 |
|
|
#define PXA2X0_DRCMR29 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0174 )
|
| 134 |
|
|
#define PXA2X0_DRCMR30 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0178 )
|
| 135 |
|
|
#define PXA2X0_DRCMR31 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x017c )
|
| 136 |
|
|
#define PXA2X0_DRCMR32 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0180 )
|
| 137 |
|
|
#define PXA2X0_DRCMR33 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0184 )
|
| 138 |
|
|
#define PXA2X0_DRCMR34 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0188 )
|
| 139 |
|
|
#define PXA2X0_DRCMR35 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x018c )
|
| 140 |
|
|
#define PXA2X0_DRCMR36 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0190 )
|
| 141 |
|
|
#define PXA2X0_DRCMR37 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0194 )
|
| 142 |
|
|
#define PXA2X0_DRCMR38 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0198 )
|
| 143 |
|
|
#define PXA2X0_DRCMR39 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x019c )
|
| 144 |
|
|
#define PXA2X0_DDADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0200 )
|
| 145 |
|
|
#define PXA2X0_DSADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0204 )
|
| 146 |
|
|
#define PXA2X0_DTADR0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0208 )
|
| 147 |
|
|
#define PXA2X0_DCMD0 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x020c )
|
| 148 |
|
|
#define PXA2X0_DDADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0210 )
|
| 149 |
|
|
#define PXA2X0_DSADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0214 )
|
| 150 |
|
|
#define PXA2X0_DTADR1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0218 )
|
| 151 |
|
|
#define PXA2X0_DCMD1 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x021c )
|
| 152 |
|
|
#define PXA2X0_DDADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0220 )
|
| 153 |
|
|
#define PXA2X0_DSADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0224 )
|
| 154 |
|
|
#define PXA2X0_DTADR2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0228 )
|
| 155 |
|
|
#define PXA2X0_DCMD2 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x022c )
|
| 156 |
|
|
#define PXA2X0_DDADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0230 )
|
| 157 |
|
|
#define PXA2X0_DSADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0234 )
|
| 158 |
|
|
#define PXA2X0_DTADR3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0238 )
|
| 159 |
|
|
#define PXA2X0_DCMD3 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x023c )
|
| 160 |
|
|
#define PXA2X0_DDADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0240 )
|
| 161 |
|
|
#define PXA2X0_DSADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0244 )
|
| 162 |
|
|
#define PXA2X0_DTADR4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0248 )
|
| 163 |
|
|
#define PXA2X0_DCMD4 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x024c )
|
| 164 |
|
|
#define PXA2X0_DDADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0250 )
|
| 165 |
|
|
#define PXA2X0_DSADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0254 )
|
| 166 |
|
|
#define PXA2X0_DTADR5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0258 )
|
| 167 |
|
|
#define PXA2X0_DCMD5 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x025c )
|
| 168 |
|
|
#define PXA2X0_DDADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0260 )
|
| 169 |
|
|
#define PXA2X0_DSADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0264 )
|
| 170 |
|
|
#define PXA2X0_DTADR6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0268 )
|
| 171 |
|
|
#define PXA2X0_DCMD6 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x026c )
|
| 172 |
|
|
#define PXA2X0_DDADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0270 )
|
| 173 |
|
|
#define PXA2X0_DSADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0274 )
|
| 174 |
|
|
#define PXA2X0_DTADR7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0278 )
|
| 175 |
|
|
#define PXA2X0_DCMD7 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x027c )
|
| 176 |
|
|
#define PXA2X0_DDADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0280 )
|
| 177 |
|
|
#define PXA2X0_DSADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0284 )
|
| 178 |
|
|
#define PXA2X0_DTADR8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0288 )
|
| 179 |
|
|
#define PXA2X0_DCMD8 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x028c )
|
| 180 |
|
|
#define PXA2X0_DDADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0290 )
|
| 181 |
|
|
#define PXA2X0_DSADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0294 )
|
| 182 |
|
|
#define PXA2X0_DTADR9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0298 )
|
| 183 |
|
|
#define PXA2X0_DCMD9 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x029c )
|
| 184 |
|
|
#define PXA2X0_DDADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a0 )
|
| 185 |
|
|
#define PXA2X0_DSADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a4 )
|
| 186 |
|
|
#define PXA2X0_DTADR10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a8 )
|
| 187 |
|
|
#define PXA2X0_DCMD10 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ac )
|
| 188 |
|
|
#define PXA2X0_DDADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b0 )
|
| 189 |
|
|
#define PXA2X0_DSADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b4 )
|
| 190 |
|
|
#define PXA2X0_DTADR11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b8 )
|
| 191 |
|
|
#define PXA2X0_DCMD11 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02bc )
|
| 192 |
|
|
#define PXA2X0_DDADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c0 )
|
| 193 |
|
|
#define PXA2X0_DSADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c4 )
|
| 194 |
|
|
#define PXA2X0_DTADR12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c8 )
|
| 195 |
|
|
#define PXA2X0_DCMD12 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02cc )
|
| 196 |
|
|
#define PXA2X0_DDADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d0 )
|
| 197 |
|
|
#define PXA2X0_DSADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d4 )
|
| 198 |
|
|
#define PXA2X0_DTADR13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d8 )
|
| 199 |
|
|
#define PXA2X0_DCMD13 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02dc )
|
| 200 |
|
|
#define PXA2X0_DDADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e0 )
|
| 201 |
|
|
#define PXA2X0_DSADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e4 )
|
| 202 |
|
|
#define PXA2X0_DTADR14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e8 )
|
| 203 |
|
|
#define PXA2X0_DCMD14 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ec )
|
| 204 |
|
|
#define PXA2X0_DDADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f0 )
|
| 205 |
|
|
#define PXA2X0_DSADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f4 )
|
| 206 |
|
|
#define PXA2X0_DTADR15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f8 )
|
| 207 |
|
|
#define PXA2X0_DCMD15 PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02fc )
|
| 208 |
|
|
|
| 209 |
|
|
// Full Function UART
|
| 210 |
|
|
#define PXA2X0_FFUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0100000 )
|
| 211 |
|
|
#define PXA2X0_FFRBR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
|
| 212 |
|
|
#define PXA2X0_FFTHR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
|
| 213 |
|
|
#define PXA2X0_FFIER PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 )
|
| 214 |
|
|
#define PXA2X0_FFIIR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
|
| 215 |
|
|
#define PXA2X0_FFFCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
|
| 216 |
|
|
#define PXA2X0_FFLCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x000c )
|
| 217 |
|
|
#define PXA2X0_FFMCR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0010 )
|
| 218 |
|
|
#define PXA2X0_FFLSR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0014 )
|
| 219 |
|
|
#define PXA2X0_FFMSR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0018 )
|
| 220 |
|
|
#define PXA2X0_FFSPR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x001c )
|
| 221 |
|
|
#define PXA2X0_FFISR PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0020 )
|
| 222 |
|
|
#define PXA2X0_FFDLL PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
|
| 223 |
|
|
#define PXA2X0_FFDLH PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 )
|
| 224 |
|
|
|
| 225 |
|
|
// Bluetooth UART
|
| 226 |
|
|
#define PXA2X0_BTUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0200000 )
|
| 227 |
|
|
#define PXA2X0_BTRBR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
|
| 228 |
|
|
#define PXA2X0_BTTHR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
|
| 229 |
|
|
#define PXA2X0_BTIER PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 )
|
| 230 |
|
|
#define PXA2X0_BTIIR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 )
|
| 231 |
|
|
#define PXA2X0_BTFCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 )
|
| 232 |
|
|
#define PXA2X0_BTLCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x000c )
|
| 233 |
|
|
#define PXA2X0_BTMCR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0010 )
|
| 234 |
|
|
#define PXA2X0_BTLSR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0014 )
|
| 235 |
|
|
#define PXA2X0_BTMSR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0018 )
|
| 236 |
|
|
#define PXA2X0_BTSPR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x001c )
|
| 237 |
|
|
#define PXA2X0_BTISR PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0020 )
|
| 238 |
|
|
#define PXA2X0_BTDLL PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
|
| 239 |
|
|
#define PXA2X0_BTDLH PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 )
|
| 240 |
|
|
|
| 241 |
|
|
// I2C
|
| 242 |
|
|
#define PXA2X0_I2C_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0300000 )
|
| 243 |
|
|
#define PXA2X0_IBMR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1680 )
|
| 244 |
|
|
#define PXA2X0_IDBR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1688 )
|
| 245 |
|
|
#define PXA2X0_ICR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1690 )
|
| 246 |
|
|
#define PXA2X0_ISR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1698 )
|
| 247 |
|
|
#define PXA2X0_ISAR PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x16a0 )
|
| 248 |
|
|
|
| 249 |
|
|
|
| 250 |
|
|
// I2S
|
| 251 |
|
|
#define PXA2X0_I2S_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0400000 )
|
| 252 |
|
|
#define PXA2X0_SACR0 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0000 )
|
| 253 |
|
|
#define PXA2X0_SACR1 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0004 )
|
| 254 |
|
|
#define PXA2X0_SASR0 PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x000c )
|
| 255 |
|
|
#define PXA2X0_SAIMR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0014 )
|
| 256 |
|
|
#define PXA2X0_SAICR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0018 )
|
| 257 |
|
|
#define PXA2X0_SADIV PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0060 )
|
| 258 |
|
|
#define PXA2X0_SADR PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0080 )
|
| 259 |
|
|
|
| 260 |
|
|
// AC97
|
| 261 |
|
|
#define PXA2X0_AC97_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0500000 )
|
| 262 |
|
|
#define PXA2X0_POCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0000 )
|
| 263 |
|
|
#define PXA2X0_PICR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0004 )
|
| 264 |
|
|
#define PXA2X0_MCCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0008 )
|
| 265 |
|
|
#define PXA2X0_GCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x000c )
|
| 266 |
|
|
#define PXA2X0_POSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0010 )
|
| 267 |
|
|
#define PXA2X0_PISR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0014 )
|
| 268 |
|
|
#define PXA2X0_MCSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0018 )
|
| 269 |
|
|
#define PXA2X0_GSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x001c )
|
| 270 |
|
|
#define PXA2X0_CAR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0020 )
|
| 271 |
|
|
#define PXA2X0_PCDR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0040 )
|
| 272 |
|
|
#define PXA2X0_MCDR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0060 )
|
| 273 |
|
|
#define PXA2X0_MOCR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0100 )
|
| 274 |
|
|
#define PXA2X0_MICR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0108 )
|
| 275 |
|
|
#define PXA2X0_MOSR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0110 )
|
| 276 |
|
|
#define PXA2X0_MISR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0118 )
|
| 277 |
|
|
#define PXA2X0_MODR PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0140 )
|
| 278 |
|
|
#define PXA2X0_AC97_PRIM_AUDIO_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0200 )
|
| 279 |
|
|
#define PXA2X0_AC97_SEC_AUDIO_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0300 )
|
| 280 |
|
|
#define PXA2X0_AC97_PRIM_MODEM_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0400 )
|
| 281 |
|
|
#define PXA2X0_AC97_SEC_MODEM_BASE PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0500 )
|
| 282 |
|
|
|
| 283 |
|
|
// UDC
|
| 284 |
|
|
#define PXA2X0_UDC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0600000 )
|
| 285 |
|
|
#define PXA2X0_UDCCR PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0000 )
|
| 286 |
|
|
#define PXA2X0_UDCCS0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0010 )
|
| 287 |
|
|
#define PXA2X0_UDCCS1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0014 )
|
| 288 |
|
|
#define PXA2X0_UDCCS2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0018 )
|
| 289 |
|
|
#define PXA2X0_UDCCS3 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x001c )
|
| 290 |
|
|
#define PXA2X0_UDCCS4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0020 )
|
| 291 |
|
|
#define PXA2X0_UDCCS5 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0024 )
|
| 292 |
|
|
#define PXA2X0_UDCCS6 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0028 )
|
| 293 |
|
|
#define PXA2X0_UDCCS7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x002c )
|
| 294 |
|
|
#define PXA2X0_UDCCS8 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0030 )
|
| 295 |
|
|
#define PXA2X0_UDCCS9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0034 )
|
| 296 |
|
|
#define PXA2X0_UDCCS10 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0038 )
|
| 297 |
|
|
#define PXA2X0_UDCCS11 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x003c )
|
| 298 |
|
|
#define PXA2X0_UDCCS12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0040 )
|
| 299 |
|
|
#define PXA2X0_UDCCS13 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0044 )
|
| 300 |
|
|
#define PXA2X0_UDCCS14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0048 )
|
| 301 |
|
|
#define PXA2X0_UDCCS15 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x004c )
|
| 302 |
|
|
#define PXA2X0_UFNRH PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0060 )
|
| 303 |
|
|
#define PXA2X0_UFNRL PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0064 )
|
| 304 |
|
|
#define PXA2X0_UBCR2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0068 )
|
| 305 |
|
|
#define PXA2X0_UBCR4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x006c )
|
| 306 |
|
|
#define PXA2X0_UBCR7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0070 )
|
| 307 |
|
|
#define PXA2X0_UBCR9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0074 )
|
| 308 |
|
|
#define PXA2X0_UBCR12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0078 )
|
| 309 |
|
|
#define PXA2X0_UBCR14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x007c )
|
| 310 |
|
|
#define PXA2X0_UDDR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0080 )
|
| 311 |
|
|
#define PXA2X0_UDDR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0100 )
|
| 312 |
|
|
#define PXA2X0_UDDR2 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0180 )
|
| 313 |
|
|
#define PXA2X0_UDDR3 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0200 )
|
| 314 |
|
|
#define PXA2X0_UDDR4 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0400 )
|
| 315 |
|
|
#define PXA2X0_UDDR5 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00a0 )
|
| 316 |
|
|
#define PXA2X0_UDDR6 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0600 )
|
| 317 |
|
|
#define PXA2X0_UDDR7 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0680 )
|
| 318 |
|
|
#define PXA2X0_UDDR8 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0700 )
|
| 319 |
|
|
#define PXA2X0_UDDR9 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0900 )
|
| 320 |
|
|
#define PXA2X0_UDDR10 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00c0 )
|
| 321 |
|
|
#define PXA2X0_UDDR11 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b00 )
|
| 322 |
|
|
#define PXA2X0_UDDR12 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b80 )
|
| 323 |
|
|
#define PXA2X0_UDDR13 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0c00 )
|
| 324 |
|
|
#define PXA2X0_UDDR14 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0e00 )
|
| 325 |
|
|
#define PXA2X0_UDDR15 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00e0 )
|
| 326 |
|
|
#define PXA2X0_UICR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0050 )
|
| 327 |
|
|
#define PXA2X0_UICR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0054 )
|
| 328 |
|
|
#define PXA2X0_USIR0 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0058 )
|
| 329 |
|
|
#define PXA2X0_USIR1 PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x005c )
|
| 330 |
|
|
|
| 331 |
|
|
// Standard UART
|
| 332 |
|
|
#define PXA2X0_STUART_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0700000 )
|
| 333 |
|
|
#define PXA2X0_STRBR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
|
| 334 |
|
|
#define PXA2X0_STTHR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
|
| 335 |
|
|
#define PXA2X0_STIER PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 )
|
| 336 |
|
|
#define PXA2X0_STIIR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 )
|
| 337 |
|
|
#define PXA2X0_STFCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 )
|
| 338 |
|
|
#define PXA2X0_STLCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x000c )
|
| 339 |
|
|
#define PXA2X0_STMCR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0010 )
|
| 340 |
|
|
#define PXA2X0_STLSR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0014 )
|
| 341 |
|
|
#define PXA2X0_STMSR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0018 )
|
| 342 |
|
|
#define PXA2X0_STSPR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x001c )
|
| 343 |
|
|
#define PXA2X0_STISR PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0020 )
|
| 344 |
|
|
#define PXA2X0_STDLL PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
|
| 345 |
|
|
#define PXA2X0_STDLH PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 )
|
| 346 |
|
|
|
| 347 |
|
|
// ICP
|
| 348 |
|
|
#define PXA2X0_ICP_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0800000 )
|
| 349 |
|
|
#define PXA2X0_ICCR0 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0000 )
|
| 350 |
|
|
#define PXA2X0_ICCR1 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0004 )
|
| 351 |
|
|
#define PXA2X0_ICCR2 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0008 )
|
| 352 |
|
|
#define PXA2X0_ICDR PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x000c )
|
| 353 |
|
|
#define PXA2X0_ICSR0 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0014 )
|
| 354 |
|
|
#define PXA2X0_ICSR1 PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0018 )
|
| 355 |
|
|
|
| 356 |
|
|
// RTC
|
| 357 |
|
|
#define PXA2X0_RTC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0900000 )
|
| 358 |
|
|
#define PXA2X0_RCNR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0000 )
|
| 359 |
|
|
#define PXA2X0_RTAR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0004 )
|
| 360 |
|
|
#define PXA2X0_RTSR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0008 )
|
| 361 |
|
|
#define PXA2X0_RTTR PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x000c )
|
| 362 |
|
|
|
| 363 |
|
|
// OS Timer
|
| 364 |
|
|
#define PXA2X0_OSTIMER_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0a00000 )
|
| 365 |
|
|
#define PXA2X0_OSMR0 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0000 )
|
| 366 |
|
|
#define PXA2X0_OSMR1 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0004 )
|
| 367 |
|
|
#define PXA2X0_OSMR2 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0008 )
|
| 368 |
|
|
#define PXA2X0_OSMR3 PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x000c )
|
| 369 |
|
|
#define PXA2X0_OSCR PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0010 )
|
| 370 |
|
|
#define PXA2X0_OSSR PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0014 )
|
| 371 |
|
|
#define PXA2X0_OWER PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0018 )
|
| 372 |
|
|
#define PXA2X0_OIER PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x001c )
|
| 373 |
|
|
|
| 374 |
|
|
#define PXA2X0_OSSR_TIMER0 (0x1 << 0)
|
| 375 |
|
|
#define PXA2X0_OSSR_TIMER1 (0x1 << 1)
|
| 376 |
|
|
#define PXA2X0_OSSR_TIMER2 (0x1 << 2)
|
| 377 |
|
|
#define PXA2X0_OSSR_TIMER3 (0x1 << 3)
|
| 378 |
|
|
|
| 379 |
|
|
#define PXA2X0_OIER_TIMER0 (0x1 << 0)
|
| 380 |
|
|
#define PXA2X0_OIER_TIMER1 (0x1 << 1)
|
| 381 |
|
|
#define PXA2X0_OIER_TIMER2 (0x1 << 2)
|
| 382 |
|
|
#define PXA2X0_OIER_TIMER3 (0x1 << 3)
|
| 383 |
|
|
|
| 384 |
|
|
#define PXA2X0_OWER_WME (0x1 << 0)
|
| 385 |
|
|
|
| 386 |
|
|
// PWM 0
|
| 387 |
|
|
#define PXA2X0_PWM0_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0b00000 )
|
| 388 |
|
|
#define PXA2X0_PWM_CTRL0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0000 )
|
| 389 |
|
|
#define PXA2X0_PWM_PWDUTY0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0004 )
|
| 390 |
|
|
#define PXA2X0_PWM_PERVAL0 PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0008 )
|
| 391 |
|
|
|
| 392 |
|
|
// PWM 1
|
| 393 |
|
|
#define PXA2X0_PWM1_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0c00000 )
|
| 394 |
|
|
#define PXA2X0_PWM_CTRL1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0000 )
|
| 395 |
|
|
#define PXA2X0_PWM_PWDUTY1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0004 )
|
| 396 |
|
|
#define PXA2X0_PWM_PERVAL1 PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0008 )
|
| 397 |
|
|
|
| 398 |
|
|
// Interrupt Control
|
| 399 |
|
|
#define PXA2X0_IC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0d00000 )
|
| 400 |
|
|
#define PXA2X0_ICIP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0000 )
|
| 401 |
|
|
#define PXA2X0_ICMR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0004 )
|
| 402 |
|
|
#define PXA2X0_ICLR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0008 )
|
| 403 |
|
|
#define PXA2X0_ICFP PXA2X0_REGISTER( PXA2X0_IC_BASE+0x000c )
|
| 404 |
|
|
#define PXA2X0_ICPR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0010 )
|
| 405 |
|
|
#define PXA2X0_ICCR PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0014 )
|
| 406 |
|
|
|
| 407 |
|
|
// GPIO
|
| 408 |
|
|
#define PXA2X0_GPIO_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0e00000 )
|
| 409 |
|
|
#define PXA2X0_GPLR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0000 )
|
| 410 |
|
|
#define PXA2X0_GPLR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0004 )
|
| 411 |
|
|
#define PXA2X0_GPLR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0008 )
|
| 412 |
|
|
#define PXA2X0_GPDR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x000c )
|
| 413 |
|
|
#define PXA2X0_GPDR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0010 )
|
| 414 |
|
|
#define PXA2X0_GPDR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0014 )
|
| 415 |
|
|
#define PXA2X0_GPSR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0018 )
|
| 416 |
|
|
#define PXA2X0_GPSR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x001c )
|
| 417 |
|
|
#define PXA2X0_GPSR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0020 )
|
| 418 |
|
|
#define PXA2X0_GPCR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0024 )
|
| 419 |
|
|
#define PXA2X0_GPCR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0028 )
|
| 420 |
|
|
#define PXA2X0_GPCR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x002c )
|
| 421 |
|
|
#define PXA2X0_GRER0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0030 )
|
| 422 |
|
|
#define PXA2X0_GRER1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0034 )
|
| 423 |
|
|
#define PXA2X0_GRER2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0038 )
|
| 424 |
|
|
#define PXA2X0_GFER0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x003c )
|
| 425 |
|
|
#define PXA2X0_GFER1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0040 )
|
| 426 |
|
|
#define PXA2X0_GFER2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0044 )
|
| 427 |
|
|
#define PXA2X0_GEDR0 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0048 )
|
| 428 |
|
|
#define PXA2X0_GEDR1 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x004c )
|
| 429 |
|
|
#define PXA2X0_GEDR2 PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0050 )
|
| 430 |
|
|
#define PXA2X0_GAFR0_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0054 )
|
| 431 |
|
|
#define PXA2X0_GAFR0_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0058 )
|
| 432 |
|
|
#define PXA2X0_GAFR1_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x005c )
|
| 433 |
|
|
#define PXA2X0_GAFR1_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 )
|
| 434 |
|
|
#define PXA2X0_GAFR2_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 )
|
| 435 |
|
|
#define PXA2X0_GAFR2_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 )
|
| 436 |
|
|
|
| 437 |
|
|
// Power Manager and Reset Control
|
| 438 |
|
|
#define PXA2X0_PM_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0f00000 )
|
| 439 |
|
|
#define PXA2X0_PMCR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0000 )
|
| 440 |
|
|
#define PXA2X0_PSSR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0004 )
|
| 441 |
|
|
#define PXA2X0_PSPR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0008 )
|
| 442 |
|
|
#define PXA2X0_PWER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x000c )
|
| 443 |
|
|
#define PXA2X0_PRER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0010 )
|
| 444 |
|
|
#define PXA2X0_PFER PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0014 )
|
| 445 |
|
|
#define PXA2X0_PEDR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0018 )
|
| 446 |
|
|
#define PXA2X0_PCFR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x001c )
|
| 447 |
|
|
#define PXA2X0_PGSR0 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0020 )
|
| 448 |
|
|
#define PXA2X0_PGSR1 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0024 )
|
| 449 |
|
|
#define PXA2X0_PGSR2 PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0028 )
|
| 450 |
|
|
#define PXA2X0_RCSR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0030 )
|
| 451 |
|
|
|
| 452 |
|
|
// SSP
|
| 453 |
|
|
#define PXA2X0_SSP_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1000000 )
|
| 454 |
|
|
#define PXA2X0_SSCR0 PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0000 )
|
| 455 |
|
|
#define PXA2X0_SSCR1 PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0004 )
|
| 456 |
|
|
#define PXA2X0_SSSR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0008 )
|
| 457 |
|
|
#define PXA2X0_SSITR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x000c )
|
| 458 |
|
|
#define PXA2X0_SSDR PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0010 )
|
| 459 |
|
|
|
| 460 |
|
|
// MMC Controller
|
| 461 |
|
|
#define PXA2X0_MMC_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1100000 )
|
| 462 |
|
|
#define PXA2X0_MMC_STRPCL PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0000 )
|
| 463 |
|
|
#define PXA2X0_MMC_STAT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0004 )
|
| 464 |
|
|
#define PXA2X0_MMC_CLKRT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0008 )
|
| 465 |
|
|
#define PXA2X0_MMC_SPI PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x000c )
|
| 466 |
|
|
#define PXA2X0_MMC_CMDAT PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0010 )
|
| 467 |
|
|
#define PXA2X0_MMC_RESTO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0014 )
|
| 468 |
|
|
#define PXA2X0_MMC_RDTO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0018 )
|
| 469 |
|
|
#define PXA2X0_MMC_BLKLEN PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x001c )
|
| 470 |
|
|
#define PXA2X0_MMC_NOB PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0020 )
|
| 471 |
|
|
#define PXA2X0_MMC_PRTBUF PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0024 )
|
| 472 |
|
|
#define PXA2X0_MMC_I_MASK PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0028 )
|
| 473 |
|
|
#define PXA2X0_MMC_I_REG PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x002c )
|
| 474 |
|
|
#define PXA2X0_MMC_CMD PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0030 )
|
| 475 |
|
|
#define PXA2X0_MMC_ARGH PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0034 )
|
| 476 |
|
|
#define PXA2X0_MMC_ARGL PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0038 )
|
| 477 |
|
|
#define PXA2X0_MMC_RES PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x003c )
|
| 478 |
|
|
#define PXA2X0_MMC_RXFIFO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0040 )
|
| 479 |
|
|
#define PXA2X0_MMC_TXFIFO PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0044 )
|
| 480 |
|
|
|
| 481 |
|
|
// Clocks Manager
|
| 482 |
|
|
#define PXA2X0_CLK_BASE ( PXA2X0_PERIPHERALS_BASE + 0x1300000 )
|
| 483 |
|
|
#define PXA2X0_CCCR PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0000 )
|
| 484 |
|
|
#define PXA2X0_CKEN PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0004 )
|
| 485 |
|
|
#define PXA2X0_CSCC PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0008 )
|
| 486 |
|
|
// Memory Clock
|
| 487 |
|
|
#define PXA2X0_CCCR_L09 (0x1f)
|
| 488 |
|
|
#define PXA2X0_CCCR_L27 (0x01)
|
| 489 |
|
|
#define PXA2X0_CCCR_L32 (0x02)
|
| 490 |
|
|
#define PXA2X0_CCCR_L36 (0x03)
|
| 491 |
|
|
#define PXA2X0_CCCR_L40 (0x04)
|
| 492 |
|
|
#define PXA2X0_CCCR_L45 (0x05)
|
| 493 |
|
|
// Memory-to-Run-Mode multiplier
|
| 494 |
|
|
#define PXA2X0_CCCR_M1 (0x1 << 5)
|
| 495 |
|
|
#define PXA2X0_CCCR_M2 (0x2 << 5)
|
| 496 |
|
|
#define PXA2X0_CCCR_M4 (0x3 << 5)
|
| 497 |
|
|
// Run-Mode-to-Turbo-Mode multiplier
|
| 498 |
|
|
#define PXA2X0_CCCR_N10 (0x2 << 7) // N=1.0
|
| 499 |
|
|
#define PXA2X0_CCCR_N15 (0x3 << 7) // N=1.5
|
| 500 |
|
|
#define PXA2X0_CCCR_N20 (0x4 << 7) // N=2.0
|
| 501 |
|
|
#define PXA2X0_CCCR_N25 (0x5 << 7) // N=2.5
|
| 502 |
|
|
#define PXA2X0_CCCR_N30 (0x6 << 7) // N=3.0
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
// LCD Controller
|
| 506 |
|
|
#define PXA2X0_LCCR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0000 )
|
| 507 |
|
|
#define PXA2X0_LCCR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0004 )
|
| 508 |
|
|
#define PXA2X0_LCCR2 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0008 )
|
| 509 |
|
|
#define PXA2X0_LCCR3 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x000c )
|
| 510 |
|
|
#define PXA2X0_FDADR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0200 )
|
| 511 |
|
|
#define PXA2X0_FSADR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0204 )
|
| 512 |
|
|
#define PXA2X0_FIDR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0208 )
|
| 513 |
|
|
#define PXA2X0_LDCMD0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x020c )
|
| 514 |
|
|
#define PXA2X0_FDADR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0210 )
|
| 515 |
|
|
#define PXA2X0_FSADR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0214 )
|
| 516 |
|
|
#define PXA2X0_FIDR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0218 )
|
| 517 |
|
|
#define PXA2X0_LDCMD1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x021c )
|
| 518 |
|
|
#define PXA2X0_FBR0 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0020 )
|
| 519 |
|
|
#define PXA2X0_FBR1 PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0024 )
|
| 520 |
|
|
#define PXA2X0_LCSR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0038 )
|
| 521 |
|
|
#define PXA2X0_LIIDR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x003c )
|
| 522 |
|
|
#define PXA2X0_TRGBR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0040 )
|
| 523 |
|
|
#define PXA2X0_TCR PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0044 )
|
| 524 |
|
|
|
| 525 |
|
|
// Memory Controller
|
| 526 |
|
|
#define PXA2X0_MDCNFG PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0000 )
|
| 527 |
|
|
#define PXA2X0_MDREFR PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0004 )
|
| 528 |
|
|
#define PXA2X0_MSC0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0008 )
|
| 529 |
|
|
#define PXA2X0_MSC1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x000c )
|
| 530 |
|
|
#define PXA2X0_MSC2 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0010 )
|
| 531 |
|
|
#define PXA2X0_MECR PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0014 )
|
| 532 |
|
|
#define PXA2X0_SXCNFG PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x001c )
|
| 533 |
|
|
#define PXA2X0_SXMRS PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0024 )
|
| 534 |
|
|
#define PXA2X0_MCMEM0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0028 )
|
| 535 |
|
|
#define PXA2X0_MCMEM1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x002c )
|
| 536 |
|
|
#define PXA2X0_MCATT0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0030 )
|
| 537 |
|
|
#define PXA2X0_MCATT1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0034 )
|
| 538 |
|
|
#define PXA2X0_MCIO0 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0038 )
|
| 539 |
|
|
#define PXA2X0_MCIO1 PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x003c )
|
| 540 |
|
|
#define PXA2X0_MDMRS PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0040 )
|
| 541 |
|
|
#define PXA2X0_BOOT_DEF PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0044 )
|
| 542 |
|
|
|
| 543 |
|
|
// UART definitions
|
| 544 |
|
|
// Register offsets
|
| 545 |
|
|
#define PXA2X0_UART_RBR ( 0x0000 ) // Receive Buffer Register
|
| 546 |
|
|
#define PXA2X0_UART_THR ( 0x0000 ) // Transmit Hold Register
|
| 547 |
|
|
#define PXA2X0_UART_IER ( 0x0004 ) // Interrupt Enable Register
|
| 548 |
|
|
#define PXA2X0_UART_IIR ( 0x0008 ) // Interrupt ID Register
|
| 549 |
|
|
#define PXA2X0_UART_FCR ( 0x0008 )
|
| 550 |
|
|
#define PXA2X0_UART_LCR ( 0x000c )
|
| 551 |
|
|
#define PXA2X0_UART_MCR ( 0x0010 )
|
| 552 |
|
|
#define PXA2X0_UART_LSR ( 0x0014 )
|
| 553 |
|
|
#define PXA2X0_UART_MSR ( 0x0018 )
|
| 554 |
|
|
#define PXA2X0_UART_SPR ( 0x001c )
|
| 555 |
|
|
#define PXA2X0_UART_ISR ( 0x0020 )
|
| 556 |
|
|
#define PXA2X0_UART_DLL ( 0x0000 )
|
| 557 |
|
|
#define PXA2X0_UART_DLH ( 0x0004 )
|
| 558 |
|
|
|
| 559 |
|
|
|
| 560 |
|
|
// The interrupt enable register bits.
|
| 561 |
|
|
#define PXA2X0_UART_IER_RAVIE 0x01 // enable received data available irq
|
| 562 |
|
|
#define PXA2X0_UART_IER_TIE 0x02 // enable transmit data request interrupt
|
| 563 |
|
|
#define PXA2X0_UART_IER_RLSE 0x04 // enable receiver line status irq
|
| 564 |
|
|
#define PXA2X0_UART_IER_MIE 0x08 // enable modem status interrupt
|
| 565 |
|
|
#define PXA2X0_UART_IER_RTOIE 0x10 // enable Rx timeout interrupt
|
| 566 |
|
|
#define PXA2X0_UART_IER_NRZE 0x20 // enable NRZ coding
|
| 567 |
|
|
#define PXA2X0_UART_IER_UUE 0x40 // enable the UART unit
|
| 568 |
|
|
#define PXA2X0_UART_IER_DMAE 0x80 // enable DMA requests
|
| 569 |
|
|
|
| 570 |
|
|
// The interrupt identification register bits.
|
| 571 |
|
|
#define PXA2X0_UART_IIR_IP 0x01 // 0 if interrupt pending
|
| 572 |
|
|
#define PXA2X0_UART_Tx 0x02
|
| 573 |
|
|
#define PXA2X0_UART_Rx 0x04
|
| 574 |
|
|
#define PXA2X0_UART_IIR_ID_MASK 0xff // mask for interrupt ID bits
|
| 575 |
|
|
|
| 576 |
|
|
// The line status register bits.
|
| 577 |
|
|
#define PXA2X0_UART_LSR_DR 0x01 // data ready
|
| 578 |
|
|
#define PXA2X0_UART_LSR_OE 0x02 // overrun error
|
| 579 |
|
|
#define PXA2X0_UART_LSR_PE 0x04 // parity error
|
| 580 |
|
|
#define PXA2X0_UART_LSR_FE 0x08 // framing error
|
| 581 |
|
|
#define PXA2X0_UART_LSR_BI 0x10 // break interrupt
|
| 582 |
|
|
#define PXA2X0_UART_LSR_THRE 0x20 // transmitter holding register empty
|
| 583 |
|
|
#define PXA2X0_UART_LSR_TEMT 0x40 // transmitter holding and Tx shift registers empty
|
| 584 |
|
|
#define PXA2X0_UART_LSR_ERR 0x80 // any error condition (FIFOE)
|
| 585 |
|
|
|
| 586 |
|
|
// The modem status register bits.
|
| 587 |
|
|
#define PXA2X0_UART_MSR_DCTS 0x01 // delta clear to send
|
| 588 |
|
|
#define PXA2X0_UART_MSR_DDSR 0x02 // delta data set ready
|
| 589 |
|
|
#define PXA2X0_UART_MSR_TERI 0x04 // trailing edge ring indicator
|
| 590 |
|
|
#define PXA2X0_UART_MSR_DDCD 0x08 // delta data carrier detect
|
| 591 |
|
|
#define PXA2X0_UART_MSR_CTS 0x10 // clear to send
|
| 592 |
|
|
#define PXA2X0_UART_MSR_DSR 0x20 // data set ready
|
| 593 |
|
|
#define PXA2X0_UART_MSR_RI 0x40 // ring indicator
|
| 594 |
|
|
#define PXA2X0_UART_MSR_DCD 0x80 // data carrier detect
|
| 595 |
|
|
|
| 596 |
|
|
// The line control register bits.
|
| 597 |
|
|
#define PXA2X0_UART_LCR_WLS0 0x01 // word length select bit 0
|
| 598 |
|
|
#define PXA2X0_UART_LCR_WLS1 0x02 // word length select bit 1
|
| 599 |
|
|
#define PXA2X0_UART_LCR_STB 0x04 // number of stop bits
|
| 600 |
|
|
#define PXA2X0_UART_LCR_PEN 0x08 // parity enable
|
| 601 |
|
|
#define PXA2X0_UART_LCR_EPS 0x10 // even parity select
|
| 602 |
|
|
#define PXA2X0_UART_LCR_SP 0x20 // stick parity
|
| 603 |
|
|
#define PXA2X0_UART_LCR_SB 0x40 // set break
|
| 604 |
|
|
#define PXA2X0_UART_LCR_DLAB 0x80 // divisor latch access bit
|
| 605 |
|
|
|
| 606 |
|
|
// The FIFO control register
|
| 607 |
|
|
#define PXA2X0_UART_FCR_FCR0 0x01 // enable xmit and rcvr fifos
|
| 608 |
|
|
#define PXA2X0_UART_FCR_FCR1 0x02 // clear RCVR FIFO
|
| 609 |
|
|
#define PXA2X0_UART_FCR_FCR2 0x04 // clear XMIT FIFO
|
| 610 |
|
|
#define PXA2X0_UART_FCR_ITL0 0x40 // Interrupt trigger level (ITL) bit 0
|
| 611 |
|
|
#define PXA2X0_UART_FCR_ITL1 0x80 // Interrupt trigger level (ITL) bit 1
|
| 612 |
|
|
#define PXA2X0_UART_FCR_ITL_1BYTE 0x00 // i byte triggers interrupt
|
| 613 |
|
|
|
| 614 |
|
|
#define PXA2X0_UART_BAUD_RATE_DIVISOR(x) ((14745600/(16*(x))))
|
| 615 |
|
|
|
| 616 |
|
|
#endif // CYGONCE_HAL_ARM_PXA2X0_H
|
| 617 |
|
|
// EOF hal_pxa2x0.h
|
| 618 |
|
|
|
