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#ifndef CYGONCE_HAL_VAR_INTS_H
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#define CYGONCE_HAL_VAR_INTS_H
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//==========================================================================
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//
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// hal_var_ints.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): <knud.woehler@microplex.de>
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// Date: 2002-09-02
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <cyg/hal/hal_pxa2x0.h>
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// 1st level
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// 0-7 Reserved
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#define CYGNUM_HAL_INTERRUPT_GPIO0 8
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#define CYGNUM_HAL_INTERRUPT_GPIO1 9
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#define CYGNUM_HAL_INTERRUPT_GPIO 10
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#define CYGNUM_HAL_INTERRUPT_USB 11
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#define CYGNUM_HAL_INTERRUPT_PMU 12
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#define CYGNUM_HAL_INTERRUPT_I2S 13
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#define CYGNUM_HAL_INTERRUPT_AC97 14
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// 15,16 Reserved
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#define CYGNUM_HAL_INTERRUPT_LCD 17
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#define CYGNUM_HAL_INTERRUPT_I2C 18
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#define CYGNUM_HAL_INTERRUPT_ICP 19
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#define CYGNUM_HAL_INTERRUPT_STUART 20
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#define CYGNUM_HAL_INTERRUPT_BTUART 21
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#define CYGNUM_HAL_INTERRUPT_FFUART 22
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#define CYGNUM_HAL_INTERRUPT_MMC 23
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#define CYGNUM_HAL_INTERRUPT_SSP 24
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#define CYGNUM_HAL_INTERRUPT_DMA 25
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#define CYGNUM_HAL_INTERRUPT_TIMER0 26
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#define CYGNUM_HAL_INTERRUPT_TIMER1 27
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#define CYGNUM_HAL_INTERRUPT_TIMER2 28
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#define CYGNUM_HAL_INTERRUPT_TIMER3 29
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#define CYGNUM_HAL_INTERRUPT_HZ 30
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#define CYGNUM_HAL_INTERRUPT_ALARM 31
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// 2nd level
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#define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2)
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#define CYGNUM_HAL_INTERRUPT_GPIO3 (32+3)
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#define CYGNUM_HAL_INTERRUPT_GPIO4 (32+4)
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#define CYGNUM_HAL_INTERRUPT_GPIO5 (32+5)
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#define CYGNUM_HAL_INTERRUPT_GPIO6 (32+6)
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#define CYGNUM_HAL_INTERRUPT_GPIO7 (32+7)
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#define CYGNUM_HAL_INTERRUPT_GPIO8 (32+8)
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#define CYGNUM_HAL_INTERRUPT_GPIO9 (32+9)
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#define CYGNUM_HAL_INTERRUPT_GPIO10 (32+10)
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#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
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#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
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#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
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#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
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#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
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#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
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#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
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#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
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#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
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#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
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#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
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#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
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#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
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#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
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#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
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#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
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#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
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#define CYGNUM_HAL_INTERRUPT_GPIO28 (32+28)
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#define CYGNUM_HAL_INTERRUPT_GPIO29 (32+29)
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#define CYGNUM_HAL_INTERRUPT_GPIO30 (32+30)
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#define CYGNUM_HAL_INTERRUPT_GPIO31 (32+31)
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#define CYGNUM_HAL_INTERRUPT_GPIO32 (64+0)
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#define CYGNUM_HAL_INTERRUPT_GPIO33 (64+1)
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#define CYGNUM_HAL_INTERRUPT_GPIO34 (64+2)
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#define CYGNUM_HAL_INTERRUPT_GPIO35 (64+3)
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#define CYGNUM_HAL_INTERRUPT_GPIO36 (64+4)
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#define CYGNUM_HAL_INTERRUPT_GPIO37 (64+5)
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#define CYGNUM_HAL_INTERRUPT_GPIO38 (64+6)
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#define CYGNUM_HAL_INTERRUPT_GPIO39 (64+7)
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#define CYGNUM_HAL_INTERRUPT_GPIO40 (64+8)
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#define CYGNUM_HAL_INTERRUPT_GPIO41 (64+9)
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#define CYGNUM_HAL_INTERRUPT_GPIO42 (64+10)
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#define CYGNUM_HAL_INTERRUPT_GPIO43 (64+11)
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#define CYGNUM_HAL_INTERRUPT_GPIO44 (64+12)
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#define CYGNUM_HAL_INTERRUPT_GPIO45 (64+13)
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#define CYGNUM_HAL_INTERRUPT_GPIO46 (64+14)
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#define CYGNUM_HAL_INTERRUPT_GPIO47 (64+15)
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#define CYGNUM_HAL_INTERRUPT_GPIO48 (64+16)
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#define CYGNUM_HAL_INTERRUPT_GPIO49 (64+17)
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#define CYGNUM_HAL_INTERRUPT_GPIO50 (64+18)
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#define CYGNUM_HAL_INTERRUPT_GPIO51 (64+19)
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#define CYGNUM_HAL_INTERRUPT_GPIO52 (64+20)
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#define CYGNUM_HAL_INTERRUPT_GPIO53 (64+21)
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#define CYGNUM_HAL_INTERRUPT_GPIO54 (64+22)
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#define CYGNUM_HAL_INTERRUPT_GPIO55 (64+23)
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#define CYGNUM_HAL_INTERRUPT_GPIO56 (64+24)
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#define CYGNUM_HAL_INTERRUPT_GPIO57 (64+25)
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#define CYGNUM_HAL_INTERRUPT_GPIO58 (64+26)
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#define CYGNUM_HAL_INTERRUPT_GPIO59 (64+27)
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#define CYGNUM_HAL_INTERRUPT_GPIO60 (64+28)
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#define CYGNUM_HAL_INTERRUPT_GPIO61 (64+29)
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#define CYGNUM_HAL_INTERRUPT_GPIO62 (64+30)
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#define CYGNUM_HAL_INTERRUPT_GPIO63 (64+31)
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#define CYGNUM_HAL_INTERRUPT_GPIO64 (96+0)
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#define CYGNUM_HAL_INTERRUPT_GPIO65 (96+1)
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#define CYGNUM_HAL_INTERRUPT_GPIO66 (96+2)
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#define CYGNUM_HAL_INTERRUPT_GPIO67 (96+3)
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#define CYGNUM_HAL_INTERRUPT_GPIO68 (96+4)
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#define CYGNUM_HAL_INTERRUPT_GPIO69 (96+5)
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#define CYGNUM_HAL_INTERRUPT_GPIO70 (96+6)
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#define CYGNUM_HAL_INTERRUPT_GPIO71 (96+7)
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#define CYGNUM_HAL_INTERRUPT_GPIO72 (96+8)
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#define CYGNUM_HAL_INTERRUPT_GPIO73 (96+9)
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#define CYGNUM_HAL_INTERRUPT_GPIO74 (96+10)
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#define CYGNUM_HAL_INTERRUPT_GPIO75 (96+11)
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#define CYGNUM_HAL_INTERRUPT_GPIO76 (96+12)
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#define CYGNUM_HAL_INTERRUPT_GPIO77 (96+13)
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#define CYGNUM_HAL_INTERRUPT_GPIO78 (96+14)
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#define CYGNUM_HAL_INTERRUPT_GPIO79 (96+15)
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#define CYGNUM_HAL_INTERRUPT_GPIO80 (96+16)
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#define CYGNUM_HAL_INTERRUPT_NONE -1
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
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#define CYGNUM_HAL_ISR_MIN 8
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#define CYGNUM_HAL_ISR_MAX (96+16)
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
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#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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externC void hal_clock_latency(cyg_uint32 *);
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# define HAL_CLOCK_LATENCY( _pvalue_ ) hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
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#endif
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// Reset
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#define HAL_PLATFORM_RESET() \
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CYG_MACRO_START \
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cyg_uint32 ctrl; \
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HAL_DISABLE_INTERRUPTS(ctrl); \
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*PXA2X0_OWER = PXA2X0_OWER_WME; \
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*PXA2X0_OSMR3 = *PXA2X0_OSCR + 1000; \
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for(;;); \
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CYG_MACRO_END
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#define HAL_PLATFORM_RESET_ENTRY 0x00000000
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#endif // CYGONCE_HAL_VAR_INTS_H
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