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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [i386/] [pcmb/] [v2_0/] [include/] [pcmb_io.h] - Blame information for rev 229

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#ifndef CYGONCE_PCMB_IO_H
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#define CYGONCE_PCMB_IO_H
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//=============================================================================
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//
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//      pcmb_io.h
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//
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//      PC Motherboard specific IO support
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    proven
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// Contributors: proven, jskov, pjo
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// Date:         1999-10-15
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// Purpose:      PC Motherboard IO support
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// Description:  The macros defined here provide the HAL APIs for handling
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//               basic IO - specifically PCI config access.
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//              
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/system.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include <cyg/hal/pcmb_io.h>
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//----------------------------------------------------------------------------
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// The PCI resources required by the STPC 
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// PCI Config registers in IO space
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#define STPC_PCI_ADDR_REG  (0xCF8)
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#define STPC_PCI_DATA_REG  (0xCFC)
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//----------------------------------------------------------------------------
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// Initialize the PCI bus.
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#define HAL_PCI_INIT() \
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CYG_MACRO_START    \
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CYG_MACRO_END
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//----------------------------------------------------------------------------
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset )               \
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        ((1<<31) | ((__bus) << 16) | ((__devfn) << 8) | ((__offset) & ~3))
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//----------------------------------------------------------------------------
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// Read a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )                              \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_READ_UINT32(STPC_PCI_DATA_REG,(__val));                                                 \
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CYG_MACRO_END
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )                               \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_READ_UINT8(STPC_PCI_DATA_REG + ((__offset)&3),(__val));                                 \
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CYG_MACRO_END
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val )                              \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_READ_UINT16(STPC_PCI_DATA_REG + ((__offset)&2),(__val));                                \
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CYG_MACRO_END
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//----------------------------------------------------------------------------
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// Write a value to the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val )                             \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_WRITE_UINT32(STPC_PCI_DATA_REG,(__val));                                                \
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CYG_MACRO_END
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )                              \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_WRITE_UINT8(STPC_PCI_DATA_REG+(__offset & 3),(__val));                                  \
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CYG_MACRO_END
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val )                             \
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CYG_MACRO_START                                                                                 \
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    HAL_WRITE_UINT32(STPC_PCI_ADDR_REG,HAL_PCI_CONFIG_ADDRESS((__bus),(__devfn),(__offset)));   \
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    HAL_WRITE_UINT16(STPC_PCI_DATA_REG+(__offset & 2),(__val));                                 \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Resources
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#ifdef CYGSEM_HAL_I386_PC_LARGE_PCI_SPACE
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// Use unrestricted PCI space
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#define CYG_PCI_MAX_BUS                     256
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#define CYG_PCI_MIN_DEV                       0
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#define CYG_PCI_MAX_DEV                      32
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#define CYG_PCI_MAX_FN                        8
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#endif
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// This is where the PCI spaces are mapped in the CPU's address space.
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// In the PC the PCI address space is mapped 1-1 into the CPU physical
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// address space, so these values are both zero.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE    0x00000000
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#define HAL_PCI_PHYSICAL_IO_BASE        0x0000
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// Map PCI device resources starting from these addresses in PCI space.
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// These are the addresses in PCI space where we should map device
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// memory.  Since there is RAM and other devices in low memory and IO
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// space, we allocate from high addresses. In most PC platforms, the
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// BIOS will have actually allocated the PCI devices before we start,
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// so these values are actually academic.
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#define HAL_PCI_ALLOC_BASE_MEMORY  0xf0000000
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#define HAL_PCI_ALLOC_BASE_IO      0xDF00
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//----------------------------------------------------------------------------
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid)            \
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CYG_MACRO_START                                                                 \
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        HAL_PCI_CFG_READ_UINT8((__bus),(__devfn),CYG_PCI_CFG_INT_LINE,(__vec)); \
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        if(__vec<=15) __valid=1;                                                \
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        else __valid=0;                                                         \
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        __vec += 0x20;                                                          \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// CMOS RAM access
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#define HAL_CMOS_ADDRESS        0x70    // CMOS address register
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#define HAL_CMOS_DATA           0x71    // CMOS data register
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#define HAL_READ_CMOS( __addr, __val )                  \
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CYG_MACRO_START                                         \
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{                                                       \
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    HAL_WRITE_UINT8( HAL_CMOS_ADDRESS, __addr );        \
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    HAL_READ_UINT8( HAL_CMOS_DATA, (__val) );           \
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}                                                       \
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CYG_MACRO_END
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#define HAL_WRITE_CMOS( __addr, __val )                 \
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CYG_MACRO_START                                         \
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{                                                       \
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    HAL_WRITE_UINT8( HAL_CMOS_ADDRESS, __addr );        \
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    HAL_WRITE_UINT8( HAL_CMOS_DATA, (__val) );          \
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}                                                       \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Debug macros
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// Some simple macros for writing useful info to a PC ASCII display
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#define PC_WRITE_SCREEN( __pos, __ch ) \
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                       (*((short *)(0xB8000)+((__pos)%(80*25))) = (0x0700+(__ch)))
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#define PC_SCREEN_LINE( __line ) ((__line)*80)
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#define PC_WRITE_SCREEN_8( __pos, __val )                       \
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{                                                               \
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    char __hex[] = "0123456789ABCDEF";                          \
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    PC_WRITE_SCREEN( (__pos), __hex[((int)(__val)>>4)&0xF] );        \
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    PC_WRITE_SCREEN( ((__pos)+1), __hex[(int)(__val)&0xF] );         \
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}
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#define PC_WRITE_SCREEN_16( __pos, __val )      \
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    PC_WRITE_SCREEN_8( __pos, (int)(__val)>>8 );     \
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    PC_WRITE_SCREEN_8( (__pos)+2, (int)(__val) );
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#define PC_WRITE_SCREEN_32( __pos, __val )      \
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    PC_WRITE_SCREEN_16( __pos, (int)(__val)>>16 );   \
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    PC_WRITE_SCREEN_16( (__pos)+4, (int)(__val) );
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//-----------------------------------------------------------------------------
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// IDE interface macros
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//
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#define HAL_IDE_NUM_CONTROLLERS 2
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// Initialize the IDE controller(s).
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#define HAL_IDE_INIT()
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#define __PCMB_IDE_PRI_CMD   0x1f0
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#define __PCMB_IDE_PRI_CTL   0x3f4
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#define __PCMB_IDE_SEC_CMD   0x170
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#define __PCMB_IDE_SEC_CTL   0x374
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#define __CMD_ADDR(__n) ((__n) ? __PCMB_IDE_SEC_CMD : __PCMB_IDE_PRI_CMD)
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#define __CTL_ADDR(__n) ((__n) ? __PCMB_IDE_SEC_CTL : __PCMB_IDE_PRI_CTL)
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#define HAL_IDE_READ_UINT8( __ctlr, __regno, __val )  \
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    HAL_READ_UINT8(__CMD_ADDR(__ctlr) + (__regno), (__val))
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#define HAL_IDE_READ_UINT16( __ctlr, __regno, __val )  \
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    HAL_READ_UINT16(__CMD_ADDR(__ctlr) + (__regno), (__val))
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#define HAL_IDE_READ_ALTSTATUS( __ctlr, __val )  \
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    HAL_READ_UINT16(__CTL_ADDR(__ctlr) + 2, (__val))
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#define HAL_IDE_WRITE_UINT8( __ctlr, __regno, __val )  \
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    HAL_WRITE_UINT8(__CMD_ADDR(__ctlr) + (__regno), (__val))
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#define HAL_IDE_WRITE_UINT16( __ctlr, __regno, __val )  \
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    HAL_WRITE_UINT16(__CMD_ADDR(__ctlr) + (__regno), (__val))
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#define HAL_IDE_WRITE_CONTROL( __ctlr, __val )  \
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    HAL_WRITE_UINT16(__CTL_ADDR(__ctlr) + 2, (__val))
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//-----------------------------------------------------------------------------
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// end of pcmb_io.h
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#endif // CYGONCE_PCMB_IO_H

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