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#ifndef CYGONCE_VAR_INTR_H
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#define CYGONCE_VAR_INTR_H
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//=============================================================================
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//
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// var_intr.h
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//
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// Variant HAL interrupt and clock support
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2002 Gary Thomas
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): mtek, pfine
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// Contributors:nickg, jskov, jlarmour, hmt
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// Date: 2001-12-12
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// Purpose: Variant interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock on the MPC8260 PowerQUICCII CPU.
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// Usage: Is included via the architecture interrupt header:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/hal/plf_intr.h>
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#include <cyg/hal/mpc8260.h> // Memory map
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#include <cyg/infra/cyg_type.h> // types
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#include <cyg/hal/hal_io.h> // io macros
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#include <cyg/infra/cyg_ass.h> // CYG_FAIL
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#define CYGARC_IMM_BASE 0x04700000
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// Interrupts
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// The first level of external interrupts
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#define CYGNUM_HAL_INTERRUPT_I2C 1
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#define CYGNUM_HAL_INTERRUPT_SPI 2
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#define CYGNUM_HAL_INTERRUPT_RISC_TIMERS 3
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#define CYGNUM_HAL_INTERRUPT_SMC1 4
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#define CYGNUM_HAL_INTERRUPT_SMC2 5
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#define CYGNUM_HAL_INTERRUPT_IDMA1 6
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#define CYGNUM_HAL_INTERRUPT_IDMA2 7
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#define CYGNUM_HAL_INTERRUPT_IDMA3 8
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#define CYGNUM_HAL_INTERRUPT_IDMA4 9
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#define CYGNUM_HAL_INTERRUPT_SDMA 10
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#define CYGNUM_HAL_INTERRUPT_TIMER1 12
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#define CYGNUM_HAL_INTERRUPT_TIMER2 13
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#define CYGNUM_HAL_INTERRUPT_TIMER3 14
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#define CYGNUM_HAL_INTERRUPT_TIMER4 15
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#define CYGNUM_HAL_INTERRUPT_TMCNT 16
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#define CYGNUM_HAL_INTERRUPT_PIT 17
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#define CYGNUM_HAL_INTERRUPT_IRQ1 19
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#define CYGNUM_HAL_INTERRUPT_IRQ2 20
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#define CYGNUM_HAL_INTERRUPT_IRQ3 21
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#define CYGNUM_HAL_INTERRUPT_IRQ4 22
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#define CYGNUM_HAL_INTERRUPT_IRQ5 23
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#define CYGNUM_HAL_INTERRUPT_IRQ6 24
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#define CYGNUM_HAL_INTERRUPT_IRQ7 25
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#define CYGNUM_HAL_INTERRUPT_FCC1 32
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#define CYGNUM_HAL_INTERRUPT_FCC2 33
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#define CYGNUM_HAL_INTERRUPT_FCC3 34
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#define CYGNUM_HAL_INTERRUPT_MCC1 36
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#define CYGNUM_HAL_INTERRUPT_MCC2 37
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#define CYGNUM_HAL_INTERRUPT_SCC1 40
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#define CYGNUM_HAL_INTERRUPT_SCC2 41
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#define CYGNUM_HAL_INTERRUPT_SCC3 42
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#define CYGNUM_HAL_INTERRUPT_SCC4 43
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#define CYGNUM_HAL_INTERRUPT_PC15 48
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#define CYGNUM_HAL_INTERRUPT_PC14 49
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#define CYGNUM_HAL_INTERRUPT_PC13 50
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#define CYGNUM_HAL_INTERRUPT_PC12 51
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#define CYGNUM_HAL_INTERRUPT_PC11 52
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#define CYGNUM_HAL_INTERRUPT_PC10 53
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#define CYGNUM_HAL_INTERRUPT_PC9 54
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#define CYGNUM_HAL_INTERRUPT_PC8 55
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#define CYGNUM_HAL_INTERRUPT_PC7 56
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#define CYGNUM_HAL_INTERRUPT_PC6 57
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#define CYGNUM_HAL_INTERRUPT_PC5 58
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#define CYGNUM_HAL_INTERRUPT_PC4 59
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#define CYGNUM_HAL_INTERRUPT_PC3 60
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#define CYGNUM_HAL_INTERRUPT_PC2 61
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#define CYGNUM_HAL_INTERRUPT_PC1 62
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#define CYGNUM_HAL_INTERRUPT_PC0 63
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#define CYGNUM_HAL_INTERRUPT_ERROR 0
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PC0
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//--------------------------------------------------------------------------
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// Interrupt controller access
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#ifdef CYGPKG_HAL_POWERPC_MPC8260
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static __inline__ void
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cyg_hal_interrupt_mask ( cyg_uint32 vector )
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{
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volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
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cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
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cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
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*reg_simr_h &= ~( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
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*reg_simr_h &= ~( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
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break;
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case CYGNUM_HAL_INTERRUPT_TMCNT:
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*reg_simr_h &= ~(0x00000004);
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break;
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case CYGNUM_HAL_INTERRUPT_PIT:
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*reg_simr_h &= ~(0x00000002);
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break;
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case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
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*reg_simr_l &= ~( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
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break;
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case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
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*reg_simr_l &= ~( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
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break;
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case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
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*reg_simr_l &= ~( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
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break;
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case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
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*reg_simr_l &= ~( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
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break;
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case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
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*reg_simr_l &= ~( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
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break;
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default:
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CYG_FAIL("Unknown Interrupt in mask !!!");
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break;
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}
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}
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static __inline__ void
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cyg_hal_interrupt_unmask ( cyg_uint32 vector )
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{
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volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
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cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
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cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
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*reg_simr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
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*reg_simr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
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break;
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case CYGNUM_HAL_INTERRUPT_TMCNT:
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*reg_simr_h |= (0x00000004);
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break;
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case CYGNUM_HAL_INTERRUPT_PIT:
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*reg_simr_h |= (0x00000002);
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break;
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case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
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*reg_simr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
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break;
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case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
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*reg_simr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
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break;
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case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
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*reg_simr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
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break;
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| 227 |
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| 228 |
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case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
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*reg_simr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
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break;
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| 231 |
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| 232 |
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case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
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*reg_simr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
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| 234 |
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break;
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| 235 |
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| 236 |
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default:
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| 237 |
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CYG_FAIL("Unknown Interrupt in unmask !!!");
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| 238 |
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break;
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| 239 |
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}
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| 240 |
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| 241 |
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}
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| 242 |
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| 243 |
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static __inline__ void
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cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
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| 245 |
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{
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| 246 |
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| 247 |
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volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
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| 248 |
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cyg_uint32 *reg_sipnr_h = (cyg_uint32 *) &(IMM->ic_sipnr_h);
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| 249 |
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cyg_uint32 *reg_sipnr_l = (cyg_uint32 *) &(IMM->ic_sipnr_l);
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| 250 |
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| 251 |
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switch (vector) {
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| 252 |
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| 253 |
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case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
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| 254 |
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*reg_sipnr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
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| 255 |
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break;
|
| 256 |
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|
| 257 |
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case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
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| 258 |
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*reg_sipnr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
|
| 259 |
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break;
|
| 260 |
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| 261 |
|
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case CYGNUM_HAL_INTERRUPT_TMCNT:
|
| 262 |
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*reg_sipnr_h |= (0x00000004);
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| 263 |
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break;
|
| 264 |
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| 265 |
|
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case CYGNUM_HAL_INTERRUPT_PIT:
|
| 266 |
|
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*reg_sipnr_h |= (0x00000002);
|
| 267 |
|
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break;
|
| 268 |
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|
|
| 269 |
|
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case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
|
| 270 |
|
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*reg_sipnr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
|
| 271 |
|
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break;
|
| 272 |
|
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|
| 273 |
|
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case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
|
| 274 |
|
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*reg_sipnr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
|
| 275 |
|
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break;
|
| 276 |
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|
|
| 277 |
|
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case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
|
| 278 |
|
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*reg_sipnr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
|
| 279 |
|
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break;
|
| 280 |
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|
| 281 |
|
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case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
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| 282 |
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*reg_sipnr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
|
| 283 |
|
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break;
|
| 284 |
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|
| 285 |
|
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case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
|
| 286 |
|
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*reg_sipnr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
|
| 287 |
|
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break;
|
| 288 |
|
|
|
| 289 |
|
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default:
|
| 290 |
|
|
CYG_FAIL("Unknown Interrupt in unmask !!!");
|
| 291 |
|
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break;
|
| 292 |
|
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}
|
| 293 |
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|
|
| 294 |
|
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}
|
| 295 |
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|
|
| 296 |
|
|
static __inline__ void
|
| 297 |
|
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cyg_hal_interrupt_configure ( cyg_uint32 vector,
|
| 298 |
|
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cyg_bool level,
|
| 299 |
|
|
cyg_bool up )
|
| 300 |
|
|
{
|
| 301 |
|
|
// NOT IMPLEMENTED ...
|
| 302 |
|
|
}
|
| 303 |
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|
|
| 304 |
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|
|
| 305 |
|
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static __inline__ void
|
| 306 |
|
|
cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
|
| 307 |
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{
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| 308 |
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| 309 |
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// NOT IMPLEMENTED ....
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// FACT : USER should not program the same interrupt to more than
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// one priority position.
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// FACT : Every interrupt has an assigned default priority.
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// PROBLEM : One has to find the previous priority of the given vector
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// and swap(?) it with the requested priority owner (Not nice because
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// it changes another interrupt's priority inadvertently)
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}
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// The decrementer interrupt cannnot be masked, configured or acknowledged.
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| 322 |
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
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cyg_hal_interrupt_mask ( (_vector_) ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
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cyg_hal_interrupt_unmask ( (_vector_) ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
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cyg_hal_interrupt_acknowledge ( (_vector_) ); \
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CYG_MACRO_END
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| 340 |
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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| 341 |
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CYG_MACRO_START \
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| 342 |
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if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
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cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \
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| 344 |
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CYG_MACRO_END
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| 345 |
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| 346 |
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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| 347 |
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CYG_MACRO_START \
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| 348 |
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if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
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| 349 |
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cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
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| 350 |
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CYG_MACRO_END
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| 351 |
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| 352 |
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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| 353 |
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| 354 |
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#endif
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| 355 |
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#endif
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| 356 |
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| 357 |
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| 358 |
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|
| 359 |
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//-----------------------------------------------------------------------------
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| 360 |
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#endif // ifndef CYGONCE_VAR_INTR_H
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| 361 |
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// End of var_intr.h
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