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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [mpc8xx/] [v2_0/] [include/] [var_intr.h] - Blame information for rev 174

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#ifndef CYGONCE_VAR_INTR_H
2
#define CYGONCE_VAR_INTR_H
3
//=============================================================================
4
//
5
//      var_intr.h
6
//
7
//      Variant HAL interrupt and clock support
8
//
9
//=============================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later version.
18
//
19
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22
// for more details.
23
//
24
// You should have received a copy of the GNU General Public License along
25
// with eCos; if not, write to the Free Software Foundation, Inc.,
26
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27
//
28
// As a special exception, if other files instantiate templates or use macros
29
// or inline functions from this file, or you compile this file and link it
30
// with other works to produce a work based on this file, this file does not
31
// by itself cause the resulting work to be covered by the GNU General Public
32
// License. However the source code for this file must still be made available
33
// in accordance with section (3) of the GNU General Public License.
34
//
35
// This exception does not invalidate any other reasons why a work based on
36
// this file might be covered by the GNU General Public License.
37
//
38
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39
// at http://sources.redhat.com/ecos/ecos-license/
40
// -------------------------------------------
41
//####ECOSGPLCOPYRIGHTEND####
42
//=============================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):   nickg
46
// Contributors:nickg, jskov, jlarmour, hmt
47
// Date:        2000-04-02
48
// Purpose:     Variant interrupt support
49
// Description: The macros defined here provide the HAL APIs for handling
50
//              interrupts and the clock on the MPC8xx variant CPUs.
51
// Usage:       Is included via the architecture interrupt header:
52
//              #include <cyg/hal/hal_intr.h>
53
//              ...
54
//
55
//####DESCRIPTIONEND####
56
//
57
//=============================================================================
58
 
59
#include <pkgconf/hal.h>
60
 
61
#include <cyg/hal/plf_intr.h>
62
 
63
#include <cyg/infra/cyg_type.h>         // types
64
 
65
#include <cyg/hal/ppc_regs.h>           // register definitions
66
 
67
#include <cyg/hal/hal_io.h>             // io macros
68
#include <cyg/infra/cyg_ass.h>          // CYG_FAIL
69
 
70
//-----------------------------------------------------------------------------
71
// Exception vectors.
72
 
73
// Additional exceptions on the MPC8xx CPUs
74
#define CYGNUM_HAL_VECTOR_RESERVED_F         15
75
#define CYGNUM_HAL_VECTOR_SW_EMUL            16
76
#define CYGNUM_HAL_VECTOR_ITLB_MISS          17
77
#define CYGNUM_HAL_VECTOR_DTLB_MISS          18
78
#define CYGNUM_HAL_VECTOR_ITLB_ERROR         19
79
#define CYGNUM_HAL_VECTOR_DTLB_ERROR         20
80
#define CYGNUM_HAL_VECTOR_RESERVED_15        21
81
#define CYGNUM_HAL_VECTOR_RESERVED_16        22
82
#define CYGNUM_HAL_VECTOR_RESERVED_17        23
83
#define CYGNUM_HAL_VECTOR_RESERVED_18        24
84
#define CYGNUM_HAL_VECTOR_RESERVED_19        25
85
#define CYGNUM_HAL_VECTOR_RESERVED_1A        26
86
#define CYGNUM_HAL_VECTOR_RESERVED_1B        27
87
#define CYGNUM_HAL_VECTOR_DATA_BP            28
88
#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP     29
89
#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP      30
90
#define CYGNUM_HAL_VECTOR_NMI                31
91
 
92
#define CYGNUM_HAL_VSR_MAX                   CYGNUM_HAL_VECTOR_NMI
93
 
94
// These are the values used when passed out to an
95
// external exception handler using cyg_hal_deliver_exception()
96
 
97
#define CYGNUM_HAL_EXCEPTION_RESERVED_0      CYGNUM_HAL_VECTOR_RESERVED_0
98
#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK   CYGNUM_HAL_VECTOR_MACHINE_CHECK
99
#ifdef CYGPKG_HAL_POWERPC_MPC860
100
// The MPC860 does not generate DSI and ISI: instead it goes to machine
101
// check, so that a software VM system can then call into vectors 0x300 or
102
// 0x400 if the address is truly invalid rather than merely not in the TLB
103
// right now.  Shades of IBM wanting to port OS/MVS here!
104
// See pp 7-9/10 in "PowerQUICC - MPC860 User's Manual"
105
# undef CYGNUM_HAL_EXCEPTION_DATA_ACCESS
106
# define CYGNUM_HAL_EXCEPTION_DATA_ACCESS    CYGNUM_HAL_VECTOR_MACHINE_CHECK
107
// do not define catchers for DSI and ISI - should never happen.
108
# undef CYGNUM_HAL_EXCEPTION_MACHINE_CHECK
109
# undef CYGNUM_HAL_EXCEPTION_CODE_ACCESS
110
#else
111
# define CYGNUM_HAL_EXCEPTION_DATA_ACCESS    CYGNUM_HAL_VECTOR_DSI
112
# define CYGNUM_HAL_EXCEPTION_CODE_ACCESS    CYGNUM_HAL_VECTOR_ISI
113
#endif
114
#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS  \
115
           CYGNUM_HAL_VECTOR_ALIGNMENT
116
#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL   CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
117
#define CYGNUM_HAL_EXCEPTION_RESERVED_A      CYGNUM_HAL_VECTOR_RESERVED_A
118
#define CYGNUM_HAL_EXCEPTION_RESERVED_B      CYGNUM_HAL_VECTOR_RESERVED_B
119
#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL     CYGNUM_HAL_VECTOR_SYSTEM_CALL
120
#define CYGNUM_HAL_EXCEPTION_TRACE           CYGNUM_HAL_VECTOR_TRACE
121
#define CYGNUM_HAL_EXCEPTION_FP_ASSIST       CYGNUM_HAL_VECTOR_FP_ASSIST
122
#define CYGNUM_HAL_EXCEPTION_RESERVED_F      CYGNUM_HAL_VECTOR_RESERVED_F
123
#define CYGNUM_HAL_EXCEPTION_SW_EMUL         CYGNUM_HAL_VECTOR_SW_EMUL
124
#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS  CYGNUM_HAL_VECTOR_ITLB_MISS
125
#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS  CYGNUM_HAL_VECTOR_DTLB_MISS
126
#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \
127
               CYGNUM_HAL_VECTOR_ITLB_ERROR
128
#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \
129
           CYGNUM_HAL_VECTOR_DTLB_ERROR
130
#define CYGNUM_HAL_EXCEPTION_RESERVED_15     CYGNUM_HAL_VECTOR_RESERVED_15
131
#define CYGNUM_HAL_EXCEPTION_RESERVED_16     CYGNUM_HAL_VECTOR_RESERVED_16
132
#define CYGNUM_HAL_EXCEPTION_RESERVED_17     CYGNUM_HAL_VECTOR_RESERVED_17
133
#define CYGNUM_HAL_EXCEPTION_RESERVED_18     CYGNUM_HAL_VECTOR_RESERVED_18
134
#define CYGNUM_HAL_EXCEPTION_RESERVED_19     CYGNUM_HAL_VECTOR_RESERVED_19
135
#define CYGNUM_HAL_EXCEPTION_RESERVED_1A     CYGNUM_HAL_VECTOR_RESERVED_1A
136
#define CYGNUM_HAL_EXCEPTION_RESERVED_1B     CYGNUM_HAL_VECTOR_RESERVED_1B
137
#define CYGNUM_HAL_EXCEPTION_DATA_BP         CYGNUM_HAL_VECTOR_DATA_BP
138
#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP  CYGNUM_HAL_VECTOR_INSTRUCTION_BP
139
#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP   CYGNUM_HAL_VECTOR_PERIPHERAL_BP
140
#define CYGNUM_HAL_EXCEPTION_NMI             CYGNUM_HAL_VECTOR_NMI
141
 
142
#define CYGNUM_HAL_EXCEPTION_MIN             CYGNUM_HAL_EXCEPTION_RESERVED_0
143
#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_EXCEPTION_NMI
144
 
145
#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
146
 
147
//-----------------------------------------------------------------------------
148
// Interrupts
149
 
150
// The first level of external interrupts
151
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0            1
152
#define CYGNUM_HAL_INTERRUPT_SIU_LVL0            2
153
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1            3
154
#define CYGNUM_HAL_INTERRUPT_SIU_LVL1            4
155
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2            5
156
#define CYGNUM_HAL_INTERRUPT_SIU_LVL2            6
157
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3            7
158
#define CYGNUM_HAL_INTERRUPT_SIU_LVL3            8
159
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4            9
160
#define CYGNUM_HAL_INTERRUPT_SIU_LVL4           10
161
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5           11
162
#define CYGNUM_HAL_INTERRUPT_SIU_LVL5           12
163
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6           13
164
#define CYGNUM_HAL_INTERRUPT_SIU_LVL6           14
165
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7           15
166
#define CYGNUM_HAL_INTERRUPT_SIU_LVL7           16
167
 
168
// Further decoded interrups
169
#define CYGNUM_HAL_INTERRUPT_SIU_TB_A           17
170
#define CYGNUM_HAL_INTERRUPT_SIU_TB_B           18
171
#define CYGNUM_HAL_INTERRUPT_SIU_PIT            19
172
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC        20
173
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR        21
174
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ   22
175
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23
176
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ   24
177
#define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25
178
#define CYGNUM_HAL_INTERRUPT_SIU_CPM            26
179
 
180
// Even further...
181
#define CYGNUM_HAL_INTERRUPT_CPM_PC15           27
182
#define CYGNUM_HAL_INTERRUPT_CPM_SCC1           28
183
#define CYGNUM_HAL_INTERRUPT_CPM_SCC2           29
184
#define CYGNUM_HAL_INTERRUPT_CPM_SCC3           30
185
#define CYGNUM_HAL_INTERRUPT_CPM_SCC4           31
186
#define CYGNUM_HAL_INTERRUPT_CPM_PC14           32
187
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER1         33
188
#define CYGNUM_HAL_INTERRUPT_CPM_PC13           34
189
#define CYGNUM_HAL_INTERRUPT_CPM_PC12           35
190
#define CYGNUM_HAL_INTERRUPT_CPM_SDMA           36
191
#define CYGNUM_HAL_INTERRUPT_CPM_IDMA1          37
192
#define CYGNUM_HAL_INTERRUPT_CPM_IDMA2          38
193
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13    39
194
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER2         40
195
#define CYGNUM_HAL_INTERRUPT_CPM_RISCTT         41
196
#define CYGNUM_HAL_INTERRUPT_CPM_I2C            42
197
#define CYGNUM_HAL_INTERRUPT_CPM_PC11           43
198
#define CYGNUM_HAL_INTERRUPT_CPM_PC10           44
199
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D    45
200
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER3         46
201
#define CYGNUM_HAL_INTERRUPT_CPM_PC9            47
202
#define CYGNUM_HAL_INTERRUPT_CPM_PC8            48
203
#define CYGNUM_HAL_INTERRUPT_CPM_PC7            49
204
#define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08    50
205
#define CYGNUM_HAL_INTERRUPT_CPM_TIMER4         51
206
#define CYGNUM_HAL_INTERRUPT_CPM_PC6            52
207
#define CYGNUM_HAL_INTERRUPT_CPM_SPI            53
208
#define CYGNUM_HAL_INTERRUPT_CPM_SMC1           54
209
#define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP       55
210
#define CYGNUM_HAL_INTERRUPT_CPM_PC5            56
211
#define CYGNUM_HAL_INTERRUPT_CPM_PC4            57
212
#define CYGNUM_HAL_INTERRUPT_CPM_ERROR          58
213
 
214
#define CYGNUM_HAL_INTERRUPT_CPM_FIRST       CYGNUM_HAL_INTERRUPT_CPM_PC15
215
#define CYGNUM_HAL_INTERRUPT_CPM_LAST        CYGNUM_HAL_INTERRUPT_CPM_ERROR
216
 
217
#define CYGNUM_HAL_ISR_MAX                   CYGNUM_HAL_INTERRUPT_CPM_LAST
218
#endif
219
 
220
 
221
//--------------------------------------------------------------------------
222
// Interrupt controller access
223
 
224
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
225
 
226
#ifdef CYGPKG_HAL_POWERPC_MPC860
227
 
228
static __inline__ void
229
cyg_hal_interrupt_mask ( cyg_uint32 vector )
230
{
231
    switch (vector) {
232
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
233
    {
234
        // SIU interrupt vectors
235
        cyg_uint32 simask;
236
 
237
        HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
238
        simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0)
239
                    >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
240
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
241
        break;
242
    }
243
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
244
    {
245
        // TimeBase A interrupt
246
        cyg_uint16 tbscr;
247
 
248
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
249
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE);
250
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
251
        break;
252
    }
253
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
254
    {
255
        // TimeBase B interrupt
256
        cyg_uint16 tbscr;
257
 
258
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
259
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE);
260
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
261
        break;
262
    }
263
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
264
    {
265
        // Periodic Interrupt
266
        cyg_uint16 piscr;
267
 
268
        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
269
        piscr &= ~(CYGARC_REG_IMM_PISCR_PIE);
270
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
271
        break;
272
    }
273
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
274
    {
275
        // Real Time Clock Second
276
        cyg_uint16 rtcsc;
277
 
278
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
279
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE);
280
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
281
        break;
282
    }
283
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
284
    {
285
        // Real Time Clock Alarm
286
        cyg_uint16 rtcsc;
287
 
288
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
289
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE);
290
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
291
        break;
292
    }
293
    // PCMCIA_A_IRQ
294
    // PCMCIA_A_CHLVL
295
    // PCMCIA_B_IRQ
296
    // PCMCIA_B_CHLVL
297
    case CYGNUM_HAL_INTERRUPT_SIU_CPM:
298
    {
299
        // Communications Processor Module
300
        cyg_uint32 cicr;
301
 
302
        HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
303
        cicr &= ~(CYGARC_REG_IMM_CICR_IEN);
304
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
305
        break;
306
    }
307
    case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
308
    {
309
        // CPM interrupts
310
        cyg_uint32 cimr;
311
 
312
        HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
313
        cimr &= ~(((cyg_uint32) 0x80000000)
314
                  >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
315
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
316
        break;
317
    }
318
    default:
319
        CYG_FAIL("Unknown Interrupt!!!");
320
        break;
321
    }
322
}
323
 
324
static __inline__ void
325
cyg_hal_interrupt_unmask ( cyg_uint32 vector )
326
{
327
    switch (vector) {
328
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
329
    {
330
        // SIU interrupt vectors
331
        cyg_uint32 simask;
332
 
333
        HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
334
        simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0)
335
                   >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
336
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
337
        break;
338
    }
339
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
340
    {
341
        // TimeBase A interrupt
342
        cyg_uint16 tbscr;
343
 
344
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
345
        tbscr |= CYGARC_REG_IMM_TBSCR_REFAE;
346
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
347
        break;
348
    }
349
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
350
    {
351
        // TimeBase B interrupt
352
        cyg_uint16 tbscr;
353
 
354
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
355
        tbscr |= CYGARC_REG_IMM_TBSCR_REFBE;
356
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
357
        break;
358
    }
359
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
360
    {
361
        // Periodic Interrupt
362
        cyg_uint16 piscr;
363
 
364
        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
365
        piscr |= CYGARC_REG_IMM_PISCR_PIE;
366
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
367
        break;
368
    }
369
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
370
    {
371
        // Real Time Clock Second
372
        cyg_uint16 rtcsc;
373
 
374
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
375
        rtcsc |= CYGARC_REG_IMM_RTCSC_SIE;
376
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
377
        break;
378
    }
379
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
380
    {
381
        // Real Time Clock Alarm
382
        cyg_uint16 rtcsc;
383
 
384
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
385
        rtcsc |= CYGARC_REG_IMM_RTCSC_ALE;
386
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
387
        break;
388
    }
389
    // PCMCIA_A_IRQ
390
    // PCMCIA_A_CHLVL
391
    // PCMCIA_B_IRQ
392
    // PCMCIA_B_CHLVL
393
    case CYGNUM_HAL_INTERRUPT_SIU_CPM:
394
    {
395
        // Communications Processor Module
396
        cyg_uint32 cicr;
397
 
398
        HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
399
        cicr |= CYGARC_REG_IMM_CICR_IEN;
400
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
401
        break;
402
    }
403
    case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
404
    {
405
        // CPM interrupts
406
        cyg_uint32 cimr;
407
 
408
        HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
409
        cimr |= (((cyg_uint32) 0x80000000)
410
                 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
411
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
412
        break;
413
    }
414
    default:
415
        CYG_FAIL("Unknown Interrupt!!!");
416
        break;
417
    }
418
}
419
 
420
static __inline__ void
421
cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
422
{
423
    switch (vector) {
424
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
425
    {
426
        // SIU interrupt vectors
427
        cyg_uint32 sipend;
428
 
429
        // When IRQx is configured as an edge interrupt it needs to be
430
        // cleared. Write to INTx and IRQ/level bits are ignore so
431
        // it's safe to do always.
432
        HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
433
        sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0)
434
                   >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
435
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
436
        break;
437
    }
438
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
439
    {
440
        // TimeBase A interrupt
441
        cyg_uint16 tbscr;
442
 
443
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
444
        tbscr |= CYGARC_REG_IMM_TBSCR_REFA;
445
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
446
        break;
447
    }
448
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
449
    {
450
        // TimeBase B interrupt
451
        cyg_uint16 tbscr;
452
 
453
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
454
        tbscr |= CYGARC_REG_IMM_TBSCR_REFB;
455
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
456
        break;
457
    }
458
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
459
    {
460
        // Periodic Interrupt
461
        cyg_uint16 piscr;
462
 
463
        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
464
        piscr |= CYGARC_REG_IMM_PISCR_PS;
465
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
466
        break;
467
    }
468
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
469
    {
470
        // Real Time Clock Second
471
        cyg_uint16 rtcsc;
472
 
473
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
474
        rtcsc |= CYGARC_REG_IMM_RTCSC_SEC;
475
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
476
        break;
477
    }
478
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
479
    {
480
        // Real Time Clock Alarm
481
        cyg_uint16 rtcsc;
482
 
483
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
484
        rtcsc |= CYGARC_REG_IMM_RTCSC_ALR;
485
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
486
        break;
487
    }
488
    // PCMCIA_A_IRQ
489
    // PCMCIA_A_CHLVL
490
    // PCMCIA_B_IRQ
491
    // PCMCIA_B_CHLVL
492
    case CYGNUM_HAL_INTERRUPT_SIU_CPM:
493
        // Communications Processor Module
494
        // The CPM interrupts must be acknowledged individually.
495
        break;
496
    case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
497
    {
498
        // CPM interrupts
499
        cyg_uint32 cisr;
500
 
501
        HAL_READ_UINT32 (CYGARC_REG_IMM_CISR, cisr);
502
        cisr |= (((cyg_uint32) 0x80000000)
503
                 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
504
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CISR, cisr);
505
        break;
506
    }
507
    default:
508
        CYG_FAIL("Unknown Interrupt!!!");
509
        break;
510
    }
511
}
512
 
513
static __inline__ void
514
cyg_hal_interrupt_configure ( cyg_uint32 vector,
515
                              cyg_bool level,
516
                              cyg_bool up )
517
{
518
    switch (vector) {
519
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0:
520
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ1:
521
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ2:
522
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ3:
523
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ4:
524
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ5:
525
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ6:
526
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ7:
527
    {
528
        // External interrupts
529
        cyg_uint32 siel, bit;
530
 
531
        CYG_ASSERT( level || !up, "Only falling edge is supported");
532
 
533
        bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_IRQ0)
534
               >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
535
 
536
        HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel);
537
        siel &= ~bit;
538
        if (!level) {
539
            // Set edge detect bit.
540
            siel |= bit;
541
        }
542
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel);
543
        break;
544
    }
545
    case CYGNUM_HAL_INTERRUPT_SIU_LVL0:
546
    case CYGNUM_HAL_INTERRUPT_SIU_LVL1:
547
    case CYGNUM_HAL_INTERRUPT_SIU_LVL2:
548
    case CYGNUM_HAL_INTERRUPT_SIU_LVL3:
549
    case CYGNUM_HAL_INTERRUPT_SIU_LVL4:
550
    case CYGNUM_HAL_INTERRUPT_SIU_LVL5:
551
    case CYGNUM_HAL_INTERRUPT_SIU_LVL6:
552
    case CYGNUM_HAL_INTERRUPT_SIU_LVL7:
553
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
554
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
555
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
556
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
557
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
558
    // PCMCIA_A_IRQ
559
    // PCMCIA_A_CHLVL
560
    // PCMCIA_B_IRQ
561
    // PCMCIA_B_CHLVL
562
    case CYGNUM_HAL_INTERRUPT_SIU_CPM:
563
    case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
564
        // These cannot be configured.
565
        break;
566
 
567
    default:
568
        CYG_FAIL("Unknown Interrupt!!!");
569
        break;
570
    }
571
}
572
 
573
static __inline__ void
574
cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
575
{
576
    // Note: highest priority has the lowest numerical value.
577
    CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
578
    CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
579
 
580
    switch (vector) {
581
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
582
        // These cannot be configured.
583
        break;
584
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
585
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
586
    {
587
        // TimeBase A+B interrupt
588
        cyg_uint16 tbscr;
589
 
590
        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
591
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK);
592
        tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level;
593
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
594
        break;
595
    }
596
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
597
    {
598
        // Periodic Interrupt
599
        cyg_uint16 piscr;
600
 
601
        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
602
        piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK);
603
        piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level;
604
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
605
        break;
606
    }
607
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
608
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
609
    {
610
        // Real Time Clock Second & Real Time Clock Alarm
611
        cyg_uint16 rtcsc;
612
 
613
        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
614
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK);
615
        rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level;
616
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
617
        break;
618
    }
619
    // PCMCIA_A_IRQ
620
    // PCMCIA_A_CHLVL
621
    // PCMCIA_B_IRQ
622
    // PCMCIA_B_CHLVL
623
    case CYGNUM_HAL_INTERRUPT_SIU_CPM:
624
    {
625
        // Communications Processor Module
626
        cyg_uint32 cicr;
627
 
628
        HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
629
        cicr &= ~(CYGARC_REG_IMM_CICR_IRQMASK);
630
        cicr |= level << CYGARC_REG_IMM_CICR_IRQ_SHIFT;
631
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
632
        break;
633
    }
634
    case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
635
        // CPM interrupt levels are for internal priority. All interrupts
636
        // fed to the CPU use the CPM level set above.
637
        // FIXME: Control of SCdP ordering.
638
        break;
639
    default:
640
        CYG_FAIL("Unknown Interrupt!!!");
641
        break;
642
    }
643
}
644
 
645
// The decrementer interrupt cannnot be masked, configured or acknowledged.
646
 
647
#define HAL_INTERRUPT_MASK( _vector_ )                    \
648
    CYG_MACRO_START                                       \
649
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
650
        cyg_hal_interrupt_mask ( (_vector_) );            \
651
    CYG_MACRO_END
652
 
653
#define HAL_INTERRUPT_UNMASK( _vector_ )                  \
654
    CYG_MACRO_START                                       \
655
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
656
        cyg_hal_interrupt_unmask ( (_vector_) );          \
657
    CYG_MACRO_END
658
 
659
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )             \
660
    CYG_MACRO_START                                       \
661
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
662
        cyg_hal_interrupt_acknowledge ( (_vector_) );     \
663
    CYG_MACRO_END
664
 
665
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )              \
666
    CYG_MACRO_START                                                     \
667
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))                 \
668
        cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) );  \
669
    CYG_MACRO_END
670
 
671
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
672
    CYG_MACRO_START                                             \
673
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))         \
674
        cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
675
    CYG_MACRO_END
676
 
677
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
678
 
679
#endif
680
 
681
//--------------------------------------------------------------------------
682
// Interrupt arbiters
683
 
684
#ifdef CYGPKG_HAL_POWERPC_MPC860
685
 
686
externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector,
687
                                           CYG_ADDRWORD data);
688
externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
689
                                            CYG_ADDRWORD data);
690
externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
691
                                            CYG_ADDRWORD data);
692
externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector,
693
                                            CYG_ADDRWORD data);
694
 
695
#endif // ifdef CYGPKG_HAL_POWERPC_MPC860
696
 
697
//-----------------------------------------------------------------------------
698
// Symbols used by assembly code
699
#define CYGARC_VARIANT_DEFS                                     \
700
    DEFINE(CYGNUM_HAL_VECTOR_NMI, CYGNUM_HAL_VECTOR_NMI);
701
 
702
//-----------------------------------------------------------------------------
703
#endif // ifndef CYGONCE_VAR_INTR_H
704
// End of var_intr.h

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