OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [calmrisc16/] [arch/] [current/] [include/] [hal_io.h] - Blame information for rev 834

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_HAL_HAL_IO_H
2
#define CYGONCE_HAL_HAL_IO_H
3
 
4
//=============================================================================
5
//
6
//      hal_io.h
7
//
8
//      HAL device IO register support.
9
//
10
//=============================================================================
11
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
12
// -------------------------------------------                              
13
// This file is part of eCos, the Embedded Configurable Operating System.   
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under    
17
// the terms of the GNU General Public License as published by the Free     
18
// Software Foundation; either version 2 or (at your option) any later      
19
// version.                                                                 
20
//
21
// eCos is distributed in the hope that it will be useful, but WITHOUT      
22
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
24
// for more details.                                                        
25
//
26
// You should have received a copy of the GNU General Public License        
27
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
28
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
29
//
30
// As a special exception, if other files instantiate templates or use      
31
// macros or inline functions from this file, or you compile this file      
32
// and link it with other works to produce a work based on this file,       
33
// this file does not by itself cause the resulting work to be covered by   
34
// the GNU General Public License. However the source code for this file    
35
// must still be made available in accordance with section (3) of the GNU   
36
// General Public License v2.                                               
37
//
38
// This exception does not invalidate any other reasons why a work based    
39
// on this file might be covered by the GNU General Public License.         
40
// -------------------------------------------                              
41
// ####ECOSGPLCOPYRIGHTEND####                                              
42
//=============================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):   nickg
46
// Contributors:        nickg
47
// Date:        1998-02-17
48
// Purpose:     Define IO register support
49
// Description: The macros defined here provide the HAL APIs for handling
50
//              device IO control registers.
51
//              
52
// Usage:
53
//              #include <cyg/hal/hal_io.h>
54
//              ...
55
//              
56
//
57
//####DESCRIPTIONEND####
58
//
59
//=============================================================================
60
 
61
#include <pkgconf/hal.h>
62
 
63
#include <cyg/infra/cyg_type.h>
64
 
65
#include <cyg/hal/plf_io.h>
66
 
67
//-----------------------------------------------------------------------------
68
// IO Register address.
69
// This type is for recording the address of an IO register.
70
 
71
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
72
 
73
//-----------------------------------------------------------------------------
74
// HAL IO macros.
75
#ifndef HAL_IO_MACROS_DEFINED
76
 
77
//-----------------------------------------------------------------------------
78
// BYTE Register access.
79
// Individual and vectorized access to 8 bit registers.
80
 
81
#define HAL_READ_UINT8( _register_, _value_ ) \
82
        ((_value_) = *((volatile CYG_BYTE *)(_register_)))
83
 
84
#define HAL_WRITE_UINT8( _register_, _value_ ) \
85
        (*((volatile CYG_BYTE *)(_register_)) = (_value_))
86
 
87
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
88
{                                                                       \
89
    cyg_count32 _i_,_j_;                                                \
90
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
91
        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
92
}
93
 
94
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
95
{                                                                       \
96
    cyg_count32 _i_,_j_;                                                \
97
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
98
        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
99
}
100
 
101
 
102
//-----------------------------------------------------------------------------
103
// 16 bit access.
104
// Individual and vectorized access to 16 bit registers.
105
 
106
#define HAL_READ_UINT16( _register_, _value_ ) \
107
        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
108
 
109
#define HAL_WRITE_UINT16( _register_, _value_ ) \
110
        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
111
 
112
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
113
{                                                                       \
114
    cyg_count32 _i_,_j_;                                                \
115
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
116
        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
117
}
118
 
119
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
120
{                                                                       \
121
    cyg_count32 _i_,_j_;                                                \
122
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
123
        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
124
}
125
 
126
//-----------------------------------------------------------------------------
127
// 32 bit access.
128
// Individual and vectorized access to 32 bit registers.
129
 
130
#define HAL_READ_UINT32( _register_, _value_ ) \
131
        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
132
 
133
#define HAL_WRITE_UINT32( _register_, _value_ ) \
134
        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
135
 
136
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
137
{                                                                       \
138
    cyg_count32 _i_,_j_;                                                \
139
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
140
        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
141
}
142
 
143
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
144
{                                                                       \
145
    cyg_count32 _i_,_j_;                                                \
146
    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
147
        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
148
}
149
 
150
#define HAL_IO_MACROS_DEFINED
151
 
152
#endif
153
 
154
 
155
//-----------------------------------------------------------------------------
156
#endif // ifndef CYGONCE_HAL_HAL_IO_H
157
// End of hal_io.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.