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#ifndef CYGONCE_HAL_INTR_H
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#define CYGONCE_HAL_INTR_H
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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg, gthomas
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// Contributors: nickg, gthomas,
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// jlarmour
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// Date: 1999-02-20
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage: #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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// This is to allow a variant to decide that there is no platform-specific
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// interrupts file; and that in turn can be overridden by a platform that
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// refines the variant's ideas.
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#ifdef CYGBLD_HAL_PLF_INTS_H
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# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
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#else
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# ifdef CYGBLD_HAL_VAR_INTS_H
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# include CYGBLD_HAL_VAR_INTS_H
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# else
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# include <cyg/hal/plf_ints.h> // default less-complex platforms
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# endif
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#endif
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// Spurious interrupt (no interrupt source could be found)
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#define CYGNUM_HAL_INTERRUPT_NONE -1
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//--------------------------------------------------------------------------
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// FUJITSU exception vectors.
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// The Fujitsu FR-V architecture supports up to 256 interrupt/exceptions.
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// Each vectors to a specific VSR which is 16 bytes (4 instructions) long.
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// These vectors correspond to VSRs. These values are the ones to use for
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// HAL_VSR_GET/SET
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#define CYGNUM_HAL_VECTOR_RESET 0x00
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#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_MMU_MISS 0x01
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#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR 0x02
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#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_EXCEPTION 0x03
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#define CYGNUM_HAL_VECTOR_PRIVELEDGED_INSTRUCTION 0x06
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#define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 0x07
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#define CYGNUM_HAL_VECTOR_REGISTER_EXCEPTION 0x08
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#define CYGNUM_HAL_VECTOR_FP_DISABLED 0x0A
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#define CYGNUM_HAL_VECTOR_MP_DISABLED 0x0B
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#define CYGNUM_HAL_VECTOR_FP_EXCEPTION 0x0D
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#define CYGNUM_HAL_VECTOR_MP_EXCEPTION 0x0E
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#define CYGNUM_HAL_VECTOR_MEMORY_ADDRESS_NOT_ALIGNED 0x10
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#define CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR 0x11
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#define CYGNUM_HAL_VECTOR_DATA_ACCESS_MMU_MISS 0x12
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#define CYGNUM_HAL_VECTOR_DATA_ACCESS_EXCEPTION 0x13
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#define CYGNUM_HAL_VECTOR_DATA_STORE_ERROR 0x14
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#define CYGNUM_HAL_VECTOR_DIVISION_EXCEPTION 0x17
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#define CYGNUM_HAL_VECTOR_COMMIT_EXCEPTION 0x19
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#define CYGNUM_HAL_VECTOR_COMPOUND_EXCEPTION 0x20
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1 0x21
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_2 0x22
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_3 0x23
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_4 0x24
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_5 0x25
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_6 0x26
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_7 0x27
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_8 0x28
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_9 0x29
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_10 0x2A
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_11 0x2B
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_12 0x2C
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_13 0x2D
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_14 0x2E
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#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15 0x2F
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#define CYGNUM_HAL_VECTOR_SYSCALL 0x80 // tira gr0,#0
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#define CYGNUM_HAL_VECTOR_BREAKPOINT_TRAP 0x81 // tira gr0,#1
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#define CYGNUM_HAL_VECTOR_BREAKPOINT 0xFF // break
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#define CYGNUM_HAL_VSR_MIN 0
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#define CYGNUM_HAL_VSR_MAX 255
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#define CYGNUM_HAL_VSR_COUNT 256
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#define CYGNUM_HAL_ISR_COUNT 256 // 1-1 mapping
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// Exception vectors. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
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CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
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#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_DATA_ACCESS
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#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
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CYGNUM_HAL_EXCEPTION_MIN + 1)
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#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15
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//--------------------------------------------------------------------------
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// Static data used by HAL
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// ISR tables
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externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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// VSR table
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externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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// Platform setup memory size (0 if unknown by hardware)
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externC CYG_ADDRWORD hal_dram_size;
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// what, if anything, this means, is platform dependent:
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externC CYG_ADDRWORD hal_dram_type;
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#if CYGINT_HAL_FRV_MEM_REAL_REGION_TOP
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externC cyg_uint8 *hal_frv_mem_real_region_top( cyg_uint8 *_regionend_ );
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# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \
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hal_frv_mem_real_region_top( _regionend_ )
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#endif
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//--------------------------------------------------------------------------
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// Default ISR
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// The #define is used to test whether this routine exists, and to allow
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// code outside the HAL to call it.
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externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_DEFAULT_ISR hal_default_isr
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//--------------------------------------------------------------------------
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// Interrupt state storage
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typedef cyg_uint32 CYG_INTERRUPT_STATE;
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//--------------------------------------------------------------------------
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// Interrupt control macros
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externC cyg_uint32 hal_disable_interrupts(void);
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externC void hal_enable_interrupts(void);
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externC void hal_restore_interrupts(cyg_uint32);
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externC cyg_uint32 hal_query_interrupts(void);
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// On this processor, interrupts are controlled by level. Since eCos
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// only has the notion of "off" and "on", this will be emulated by
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// NONE-level and ALL-level.
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ( \
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"movsg psr,%0\n" \
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"\tsetlos (0x0F<<3),gr5\n" \
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"\tor %0,gr5,gr5\n" \
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"\tmovgs gr5,psr\n" \
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: "=r" (reg) \
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: \
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: "gr5" /* Clobber list */ \
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); \
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(_old_) = (reg); \
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CYG_MACRO_END
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#define HAL_ENABLE_INTERRUPTS() \
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CYG_MACRO_START \
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asm volatile ( \
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"movsg psr,gr4\n" \
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"\tsetlos (0x0F<<3),gr5\n" \
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"\tnot gr5,gr5\n" \
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"\tand gr4,gr5,gr5\n" \
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"\tmovgs gr5,psr\n" \
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: \
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: \
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: "gr4","gr5" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// This should work, but breaks compiler
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#if 0
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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asm volatile ( \
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"movsg psr,gr4\n" \
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"\tsetlos 1,gr5\n" \
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"\tand %0,gr5,gr5\n" \
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"\tor gr5,gr4,gr4\n" \
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"\tmovgs gr4,psr\n" \
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: \
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: "g" (_old_) \
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: "gr4","gr5" /* Clobber list */ \
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); \
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CYG_MACRO_END
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#else
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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hal_restore_interrupts(_old_)
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#endif
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#define HAL_QUERY_INTERRUPTS(_old_) \
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_old_ = hal_query_interrupts()
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//--------------------------------------------------------------------------
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// Routine to execute DSRs using separate interrupt stack
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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externC void hal_interrupt_stack_call_pending_DSRs(void);
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#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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hal_interrupt_stack_call_pending_DSRs()
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#if 0 // Interrupt stacks not implemented yet
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// these are offered solely for stack usage testing
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// if they are not defined, then there is no interrupt stack.
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#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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// use them to declare these extern however you want:
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// extern char HAL_INTERRUPT_STACK_BASE[];
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// extern char HAL_INTERRUPT_STACK_TOP[];
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// is recommended
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#endif // 0
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#endif
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//--------------------------------------------------------------------------
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// Vector translation.
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#ifndef HAL_TRANSLATE_VECTOR
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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(_index_) = (_vector_)
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#endif
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//--------------------------------------------------------------------------
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// Interrupt and VSR attachment macros
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#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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CYG_MACRO_START \
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cyg_uint32 _index_; \
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HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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\
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if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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(_state_) = 0; \
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else \
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(_state_) = 1; \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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CYG_MACRO_START \
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if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
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{ \
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hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
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hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
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hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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CYG_MACRO_START \
|
| 307 |
|
|
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
|
| 308 |
|
|
{ \
|
| 309 |
|
|
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
|
| 310 |
|
|
hal_interrupt_data[_vector_] = 0; \
|
| 311 |
|
|
hal_interrupt_objects[_vector_] = 0; \
|
| 312 |
|
|
} \
|
| 313 |
|
|
CYG_MACRO_END
|
| 314 |
|
|
|
| 315 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 316 |
|
|
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
|
| 320 |
|
|
CYG_MACRO_START \
|
| 321 |
|
|
if( _poldvsr_ != NULL ) \
|
| 322 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 323 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 324 |
|
|
CYG_MACRO_END
|
| 325 |
|
|
|
| 326 |
|
|
//--------------------------------------------------------------------------
|
| 327 |
|
|
// Interrupt controller access
|
| 328 |
|
|
|
| 329 |
|
|
externC void hal_interrupt_mask(int);
|
| 330 |
|
|
externC void hal_interrupt_unmask(int);
|
| 331 |
|
|
externC void hal_interrupt_acknowledge(int);
|
| 332 |
|
|
externC void hal_interrupt_configure(int, int, int);
|
| 333 |
|
|
externC void hal_interrupt_set_level(int, int);
|
| 334 |
|
|
|
| 335 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 336 |
|
|
hal_interrupt_mask( _vector_ )
|
| 337 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 338 |
|
|
hal_interrupt_unmask( _vector_ )
|
| 339 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 340 |
|
|
hal_interrupt_acknowledge( _vector_ )
|
| 341 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
|
| 342 |
|
|
hal_interrupt_configure( _vector_, _level_, _up_ )
|
| 343 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
|
| 344 |
|
|
hal_interrupt_set_level( _vector_, _level_ )
|
| 345 |
|
|
|
| 346 |
|
|
//--------------------------------------------------------------------------
|
| 347 |
|
|
// Clock control
|
| 348 |
|
|
|
| 349 |
|
|
externC void hal_clock_initialize(cyg_uint32);
|
| 350 |
|
|
externC void hal_clock_read(cyg_uint32 *);
|
| 351 |
|
|
externC void hal_clock_reset(cyg_uint32, cyg_uint32);
|
| 352 |
|
|
|
| 353 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
|
| 354 |
|
|
#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
|
| 355 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
|
| 356 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
| 357 |
|
|
# ifndef HAL_CLOCK_LATENCY
|
| 358 |
|
|
# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
|
| 359 |
|
|
# endif
|
| 360 |
|
|
#endif
|
| 361 |
|
|
|
| 362 |
|
|
//--------------------------------------------------------------------------
|
| 363 |
|
|
#endif // ifndef CYGONCE_HAL_INTR_H
|
| 364 |
|
|
// End of hal_intr.h
|
