OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2106_GCC/] [readme.txt] - Blame information for rev 583

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
Use one of the following four batch files to build the demo application:
2
 
3
+ rom_arm.bat
4
 
5
Creates an ARM mode release build suitable for programming into flash.
6
 
7
+ ram_arm.bat
8
 
9
Creates an ARM mode debug build suitable for running from RAM.
10
 
11
+ rom_thumb.bat
12
 
13
Creates a THUMB mode release build suitable for programming into flash.
14
 
15
+ ram_thumb.bat
16
 
17
Creates a THUMB mode debug build suitable for running from RAM.
18
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.