OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [GCC/] [ARM7_AT91SAM7S/] [portmacro.h] - Blame information for rev 749

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 572 jeremybenn
/*
2
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
 
4
    ***************************************************************************
5
    *                                                                         *
6
    * If you are:                                                             *
7
    *                                                                         *
8
    *    + New to FreeRTOS,                                                   *
9
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
    *    + Looking for basic training,                                        *
11
    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
    *                                                                         *
13
    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
    *                                                                         *
15
    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
    *                  http://www.FreeRTOS.org/Documentation                  *
17
    *                                                                         *
18
    * A pdf reference manual is also available.  Both are usually delivered   *
19
    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
    * exceptional circumstances).  Thank you for your support!                *
22
    *                                                                         *
23
    ***************************************************************************
24
 
25
    This file is part of the FreeRTOS distribution.
26
 
27
    FreeRTOS is free software; you can redistribute it and/or modify it under
28
    the terms of the GNU General Public License (version 2) as published by the
29
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
30
    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
    a combined work that includes FreeRTOS without being obliged to provide the
32
    source code for proprietary components outside of the FreeRTOS kernel.
33
    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
    more details. You should have received a copy of the GNU General Public
37
    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
    by writing to Richard Barry, contact details for whom are available on the
40
    FreeRTOS WEB site.
41
 
42
    1 tab == 4 spaces!
43
 
44
    http://www.FreeRTOS.org - Documentation, latest information, license and
45
    contact details.
46
 
47
    http://www.SafeRTOS.com - A version that is certified for use in safety
48
    critical systems.
49
 
50
    http://www.OpenRTOS.com - Commercial support, development, porting,
51
    licensing and training services.
52
*/
53
 
54
/*
55
        Changes from V3.2.3
56
 
57
        + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
58
 
59
        Changes from V3.2.4
60
 
61
        + Removed the use of the %0 parameter within the assembler macros and
62
          replaced them with hard coded registers.  This will ensure the
63
          assembler does not select the link register as the temp register as
64
          was occasionally happening previously.
65
 
66
        + The assembler statements are now included in a single asm block rather
67
          than each line having its own asm block.
68
 
69
        Changes from V4.5.0
70
 
71
        + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
72
          and replaced them with portYIELD_FROM_ISR() macro.  Application code
73
          should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
74
          macros as per the V4.5.1 demo code.
75
*/
76
 
77
#ifndef PORTMACRO_H
78
#define PORTMACRO_H
79
 
80
#ifdef __cplusplus
81
extern "C" {
82
#endif
83
 
84
/*-----------------------------------------------------------
85
 * Port specific definitions.
86
 *
87
 * The settings in this file configure FreeRTOS correctly for the
88
 * given hardware and compiler.
89
 *
90
 * These settings should not be altered.
91
 *-----------------------------------------------------------
92
 */
93
 
94
/* Type definitions. */
95
#define portCHAR                char
96
#define portFLOAT               float
97
#define portDOUBLE              double
98
#define portLONG                long
99
#define portSHORT               short
100
#define portSTACK_TYPE  unsigned portLONG
101
#define portBASE_TYPE   portLONG
102
 
103
#if( configUSE_16_BIT_TICKS == 1 )
104
        typedef unsigned portSHORT portTickType;
105
        #define portMAX_DELAY ( portTickType ) 0xffff
106
#else
107
        typedef unsigned portLONG portTickType;
108
        #define portMAX_DELAY ( portTickType ) 0xffffffff
109
#endif
110
/*-----------------------------------------------------------*/
111
 
112
/* Architecture specifics. */
113
#define portSTACK_GROWTH                        ( -1 )
114
#define portTICK_RATE_MS                        ( ( portTickType ) 1000 / configTICK_RATE_HZ )          
115
#define portBYTE_ALIGNMENT                      8
116
#define portNOP()                                       asm volatile ( "NOP" );
117
/*-----------------------------------------------------------*/
118
 
119
 
120
/* Scheduler utilities. */
121
 
122
/*
123
 * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
124
 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
125
 * are included here for efficiency.  An attempt to call one from
126
 * THUMB mode code will result in a compile time error.
127
 */
128
 
129
#define portRESTORE_CONTEXT()                                                                                   \
130
{                                                                                                                                               \
131
extern volatile void * volatile pxCurrentTCB;                                                   \
132
extern volatile unsigned portLONG ulCriticalNesting;                                    \
133
                                                                                                                                                \
134
        /* Set the LR to the task stack. */                                                                     \
135
        asm volatile (                                                                                                          \
136
        "LDR            R0, =pxCurrentTCB                                                               \n\t"   \
137
        "LDR            R0, [R0]                                                                                \n\t"   \
138
        "LDR            LR, [R0]                                                                                \n\t"   \
139
                                                                                                                                                \
140
        /* The critical nesting depth is the first item on the stack. */        \
141
        /* Load it into the ulCriticalNesting variable. */                                      \
142
        "LDR            R0, =ulCriticalNesting                                                  \n\t"   \
143
        "LDMFD  LR!, {R1}                                                                                       \n\t"   \
144
        "STR            R1, [R0]                                                                                \n\t"   \
145
                                                                                                                                                \
146
        /* Get the SPSR from the stack. */                                                                      \
147
        "LDMFD  LR!, {R0}                                                                                       \n\t"   \
148
        "MSR            SPSR, R0                                                                                \n\t"   \
149
                                                                                                                                                \
150
        /* Restore all system mode registers for the task. */                           \
151
        "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \
152
        "NOP                                                                                                            \n\t"   \
153
                                                                                                                                                \
154
        /* Restore the return address. */                                                                       \
155
        "LDR            LR, [LR, #+60]                                                                  \n\t"   \
156
                                                                                                                                                \
157
        /* And return - correcting the offset in the LR to obtain the */        \
158
        /* correct address. */                                                                                          \
159
        "SUBS   PC, LR, #4                                                                                      \n\t"   \
160
        );                                                                                                                                      \
161
        ( void ) ulCriticalNesting;                                                                                     \
162
        ( void ) pxCurrentTCB;                                                                                          \
163
}
164
/*-----------------------------------------------------------*/
165
 
166
#define portSAVE_CONTEXT()                                                                                              \
167
{                                                                                                                                               \
168
extern volatile void * volatile pxCurrentTCB;                                                   \
169
extern volatile unsigned portLONG ulCriticalNesting;                                    \
170
                                                                                                                                                \
171
        /* Push R0 as we are going to use the register. */                                      \
172
        asm volatile (                                                                                                          \
173
        "STMDB  SP!, {R0}                                                                                       \n\t"   \
174
                                                                                                                                                \
175
        /* Set R0 to point to the task stack pointer. */                                        \
176
        "STMDB  SP,{SP}^                                                                                        \n\t"   \
177
        "NOP                                                                                                            \n\t"   \
178
        "SUB    SP, SP, #4                                                                                      \n\t"   \
179
        "LDMIA  SP!,{R0}                                                                                        \n\t"   \
180
                                                                                                                                                \
181
        /* Push the return address onto the stack. */                                           \
182
        "STMDB  R0!, {LR}                                                                                       \n\t"   \
183
                                                                                                                                                \
184
        /* Now we have saved LR we can use it instead of R0. */                         \
185
        "MOV    LR, R0                                                                                          \n\t"   \
186
                                                                                                                                                \
187
        /* Pop R0 so we can save it onto the system mode stack. */                      \
188
        "LDMIA  SP!, {R0}                                                                                       \n\t"   \
189
                                                                                                                                                \
190
        /* Push all the system mode registers onto the task stack. */           \
191
        "STMDB  LR,{R0-LR}^                                                                                     \n\t"   \
192
        "NOP                                                                                                            \n\t"   \
193
        "SUB    LR, LR, #60                                                                                     \n\t"   \
194
                                                                                                                                                \
195
        /* Push the SPSR onto the task stack. */                                                        \
196
        "MRS    R0, SPSR                                                                                        \n\t"   \
197
        "STMDB  LR!, {R0}                                                                                       \n\t"   \
198
                                                                                                                                                \
199
        "LDR    R0, =ulCriticalNesting                                                          \n\t"   \
200
        "LDR    R0, [R0]                                                                                        \n\t"   \
201
        "STMDB  LR!, {R0}                                                                                       \n\t"   \
202
                                                                                                                                                \
203
        /* Store the new top of stack for the task. */                                          \
204
        "LDR    R0, =pxCurrentTCB                                                                       \n\t"   \
205
        "LDR    R0, [R0]                                                                                        \n\t"   \
206
        "STR    LR, [R0]                                                                                        \n\t"   \
207
        );                                                                                                                                      \
208
        ( void ) ulCriticalNesting;                                                                                     \
209
        ( void ) pxCurrentTCB;                                                                                          \
210
}
211
 
212
 
213
#define portYIELD_FROM_ISR()            vTaskSwitchContext()
214
#define portYIELD()                                     asm volatile ( "SWI 0" )
215
/*-----------------------------------------------------------*/
216
 
217
 
218
/* Critical section management. */
219
 
220
/*
221
 * The interrupt management utilities can only be called from ARM mode.  When
222
 * THUMB_INTERWORK is defined the utilities are defined as functions in
223
 * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
224
 * defined then the utilities are defined as macros here - as per other ports.
225
 */
226
 
227
#ifdef THUMB_INTERWORK
228
 
229
        extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
230
        extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
231
 
232
        #define portDISABLE_INTERRUPTS()        vPortDisableInterruptsFromThumb()
233
        #define portENABLE_INTERRUPTS()         vPortEnableInterruptsFromThumb()
234
 
235
#else
236
 
237
        #define portDISABLE_INTERRUPTS()                                                                                        \
238
                asm volatile (                                                                                                                  \
239
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
240
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
241
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                    */      \
242
                        "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
243
                        "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
244
 
245
        #define portENABLE_INTERRUPTS()                                                                                         \
246
                asm volatile (                                                                                                                  \
247
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
248
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
249
                        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \
250
                        "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
251
                        "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
252
 
253
#endif /* THUMB_INTERWORK */
254
 
255
extern void vPortEnterCritical( void );
256
extern void vPortExitCritical( void );
257
 
258
#define portENTER_CRITICAL()            vPortEnterCritical();
259
#define portEXIT_CRITICAL()                     vPortExitCritical();
260
/*-----------------------------------------------------------*/
261
 
262
/* Task function macros as described on the FreeRTOS.org WEB site. */
263
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
264
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
265
 
266
#ifdef __cplusplus
267
}
268
#endif
269
 
270
#endif /* PORTMACRO_H */
271
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.