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/*
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*-------------------------------------------------------------------
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*
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* SIM -- System Integration Module
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*
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* The system integration module (SIM) is used on many Motorola 16-
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* and 32-bit MCUs for the following functions:
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*
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* () System configuration and protection. Bus and software watchdog
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* monitors are provided in addition to periodic interrupt generators.
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*
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* () Clock signal generation for other intermodule bus (IMB) members
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* and external devices.
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*
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* () The generation of chip-select signals that simplify external
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* circuitry interface.
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*
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* () Data ports that are available for general purpose input and
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* output.
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*
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* () A system test block that is intended only for factory tests.
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*
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* For more information, refer to Motorola's "Modular Microcontroller
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* Family System Integration Module Reference Manual" (Motorola document
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* SIMRM/AD).
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*
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* This file has been created by John S. Gwynne for support of
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* Motorola's 68332 MCU in the efi332 project.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the following conditions are met:
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* 1. Redistribution of source code and documentation must retain
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* the above authorship, this list of conditions and the
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* following disclaimer.
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* 2. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* This software is provided "AS IS" without warranty of any kind,
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* either expressed or implied, including, but not limited to, the
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* implied warranties of merchantability, title and fitness for a
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* particular purpose.
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*
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*------------------------------------------------------------------
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*
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* $Id: sim.h,v 1.2 2001-09-27 11:59:28 chris Exp $
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*/
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#ifndef _SIM_H_
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#define _SIM_H_
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/* SAM-- shift and mask */
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#undef SAM
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#define SAM(a,b,c) ((a << b) & c)
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/*
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* These macros make this file usable from assembly.
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*/
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#ifdef ASM
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#define SIM_VOLATILE_USHORT_POINTER
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#define SIM_VOLATILE_UCHAR_POINTER
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#else
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#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
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#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const)
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#endif
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/* SIM_CRB (SIM Control Register Block) base address of the SIM
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control registers */
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/* not included in ram_init.h */
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#if SIM_MM == 0
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#define SIM_CRB 0x7ffa00
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#else
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#undef SIM_MM
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#define SIM_MM 1
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#define SIM_CRB 0xfffa00
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#endif
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/* end not included in ram_init.h */
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#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB)
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/* Module Configuration Register */
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#define EXOFF 0x8000 /* External Clock Off */
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#define FRZSW 0x4000 /* Freeze Software Enable */
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#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */
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#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/
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#define SHEN 0x0300 /* Show Cycle Enable */
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#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */
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#define MM 0x0040 /* Module Mapping */
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#define IARB 0x000f /* Interrupt Arbitration Field */
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#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB)
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/* SIM Test Register */
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/* Used only for factor testing */
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#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB)
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/* Clock Synthesizer Control Register */
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#define VCO 0x8000 /* Frequency Control (VCO) */
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#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */
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#define COUNTER 0x3f00 /* Frequency Control Counter */
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#define EDIV 0x0080 /* ECLK Divide Rate */
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#define SLIMP 0x0010 /* Limp Mode Status */
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#define SLOCK 0x0008 /* Synthesizer Lock */
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#define RSTEN 0x0004 /* Reset Enable */
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#define STSIM 0x0002 /* Stop Mode SIM Clock */
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#define STEXT 0x0001 /* Stop Mode External Clock */
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#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB)
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/* Reset Status Register */
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#define EXT 0x0080 /* External Reset */
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#define POW 0x0040 /* Power-On Reset */
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#define SW 0x0020 /* Software Watchdog Reset */
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#define DBF 0x0010 /* Double Bus Fault Reset */
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#define LOC 0x0004 /* Loss of Clock Reset */
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#define SYS 0x0002 /* System Reset */
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#define TST 0x0001 /* Test Submodule Reset */
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#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB)
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/* System Integration Test Register */
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/* Used only for factor testing */
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#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB)
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#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB)
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/* Port E Data Register */
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#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB)
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/* Port E Data Direction Register */
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#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB)
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/* Port E Pin Assignment Register */
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/* Any bit cleared (zero) defines the corresponding pin to be an I/O
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pin. Any bit set defines the corresponding pin to be a bus control
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signal. */
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#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB)
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#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB)
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/* Port F Data Register */
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#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB)
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/* Port E Data Direction Register */
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#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB)
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/* Any bit cleared (zero) defines the corresponding pin to be an I/O
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pin. Any bit set defines the corresponding pin to be a bus control
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signal. */
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#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB)
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/* !!! can write to only once after reset !!! */
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/* System Protection Control Register */
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#define SWE 0x80 /* Software Watch Enable */
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#define SWP 0x40 /* Software Watchdog Prescale */
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#define SWT 0x30 /* Software Watchdog Timing */
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#define HME 0x08 /* Halt Monitor Enable */
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#define BME 0x04 /* Bus Monitor External Enable */
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#define BMT 0x03 /* Bus Monitor Timing */
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#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB)
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/* Periodic Interrupt Control Reg. */
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#define PIRQL 0x0700 /* Periodic Interrupt Request Level */
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#define PIV 0x00ff /* Periodic Interrupt Level */
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#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB)
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/* Periodic Interrupt Timer Register */
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#define PTP 0x0100 /* Periodic Timer Prescaler Control */
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#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */
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#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB)
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/* Software Service Register */
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/* write 0x55 then 0xaa to service the software watchdog */
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#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB)
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/* Test Module Master Shift A */
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#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB)
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/* Test Module Master Shift A */
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#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB)
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/* Test Module Shift Count */
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#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB)
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/* Test Module Repetition Counter */
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#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB)
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/* Test Module Control */
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#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB)
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/* Test Module Distributed */
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/* Used only for factor testing */
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#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB)
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/* Port C Data */
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#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB)
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/* Chip Select Pin Assignment
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Resgister 0 */
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/* CSPAR0 contains seven two-bit fields that determine the functions
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of corresponding chip-select pins. CSPAR0[15:14] are not
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used. These bits always read zero; write have no effect. CSPAR0 bit
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1 always reads one; writes to CSPAR0 bit 1 have no effect. */
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#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
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/* Chip Select Pin Assignment
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Register 1 */
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/* CSPAR1 contains five two-bit fields that determine the finctions of
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corresponding chip-select pins. CSPAR1[15:10] are not used. These
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bits always read zero; writes have no effect. */
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/*
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*
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* Bit Field | Description
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* ------------+---------------
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* 00 | Discrete Output
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* 01 | Alternate Function
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* 10 | Chip Select (8-bit port)
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* 11 | Chip Select (16-bit port)
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*/
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#define DisOut 0x0
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#define AltFun 0x1
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#define CS8bit 0x2
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#define CS16bit 0x3
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/*
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*
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* CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output
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*-----------------+--------------------+--------------------+---------------*/
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#define CS_5 12 /* !CS5 | FC2 | PC2 */
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#define CS_4 10 /* !CS4 | FC1 | PC1 */
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#define CS_3 8 /* !CS3 | FC0 | PC0 */
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#define CS_2 6 /* !CS2 | !BGACK | */
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#define CS_1 4 /* !CS1 | !BG | */
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#define CS_0 2 /* !CS0 | !BR | */
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#define CSBOOT 0 /* !CSBOOT | | */
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/* | | | */
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#define CS_10 8 /* !CS10 | ADDR23 | ECLK */
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#define CS_9 6 /* !CS9 | ADDR22 | PC6 */
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#define CS_8 4 /* !CS8 | ADDR21 | PC5 */
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#define CS_7 2 /* !CS7 | ADDR20 | PC4 */
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#define CS_6 0 /* !CS6 | ADDR19 | PC3 */
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| 256 |
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#define BS_2K 0x0
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#define BS_8K 0x1
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#define BS_16K 0x2
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#define BS_64K 0x3
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#define BS_128K 0x4
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#define BS_256K 0x5
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#define BS_512K 0x6
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#define BS_1M 0x7
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#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB)
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#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB)
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#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB)
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#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB)
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#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB)
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#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB)
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#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB)
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#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB)
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#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB)
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#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB)
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#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB)
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#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB)
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| 278 |
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#define MODE 0x8000
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#define Disable 0
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#define LowerByte 0x2000
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#define UpperByte 0x4000
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#define BothBytes 0x6000
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#define ReadOnly 0x0800
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#define WriteOnly 0x1000
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#define ReadWrite 0x1800
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| 286 |
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#define SyncAS 0x0
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| 287 |
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#define SyncDS 0x0400
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| 288 |
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| 289 |
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#define WaitStates_0 (0x0 << 6)
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#define WaitStates_1 (0x1 << 6)
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#define WaitStates_2 (0x2 << 6)
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#define WaitStates_3 (0x3 << 6)
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#define WaitStates_4 (0x4 << 6)
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#define WaitStates_5 (0x5 << 6)
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#define WaitStates_6 (0x6 << 6)
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#define WaitStates_7 (0x7 << 6)
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#define WaitStates_8 (0x8 << 6)
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#define WaitStates_9 (0x9 << 6)
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#define WaitStates_10 (0xa << 6)
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#define WaitStates_11 (0xb << 6)
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#define WaitStates_12 (0xc << 6)
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#define WaitStates_13 (0xd << 6)
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#define FastTerm (0xe << 6)
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#define External (0xf << 6)
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#define CPUSpace (0x0 << 4)
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#define UserSpace (0x1 << 4)
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#define SupSpace (0x2 << 4)
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#define UserSupSpace (0x3 << 4)
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#define IPLevel_any 0x0
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#define IPLevel_1 0x2
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#define IPLevel_2 0x4
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#define IPLevel_3 0x6
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#define IPLevel_4 0x8
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#define IPLevel_5 0xa
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#define IPLevel_6 0xc
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#define IPLevel_7 0xe
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| 319 |
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| 320 |
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#define AVEC 1
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| 321 |
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| 322 |
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#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB)
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| 323 |
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#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB)
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| 324 |
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#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB)
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| 325 |
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#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB)
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| 326 |
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#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB)
|
| 327 |
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#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB)
|
| 328 |
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#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB)
|
| 329 |
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#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB)
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| 330 |
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#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB)
|
| 331 |
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#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB)
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| 332 |
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#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB)
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| 333 |
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#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB)
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| 334 |
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| 335 |
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#endif /* _SIM_h_ */
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