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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [dmv152/] [timer/] [timerisr.S] - Blame information for rev 30

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1 30 unneback
/*  timer_isr()
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 *
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 *  This routine provides the ISR for the Z8536 timer on the DMV152
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 *  board.   The timer is set up to generate an interrupt at maximum
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 *  intervals.
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 *
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 *  Input parameters:  NONE
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 *
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 *  Output parameters:  NONE
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 *
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 *  COPYRIGHT (c) 1989-1999.
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 *  On-Line Applications Research Corporation (OAR).
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:01 chris Exp $
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 */
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#include "asm.h"
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BEGIN_CODE
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.set TIMER,           0x0c000007         | port A
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.set CT1_CMD_STATUS,  0x0a               | command status register
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.set RELOAD,          0x26               | clr IP & IUS,allow countdown
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        PUBLIC(timerisr)
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SYM (timerisr):
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        movb    #CT1_CMD_STATUS,TIMER    | set pointer to cmd status reg
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        movb    #RELOAD,TIMER            | reload countdown
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        addql   #1, SYM (Ttimer_val)     | increment timer value
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        rte
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END_CODE
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END

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