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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [libchip/] [network/] [sonic.h] - Blame information for rev 229

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/*
2
 *       RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC'
3
 *         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER
4
 *
5
 *                REUSABLE CHIP DRIVER CONFIGURATION
6
 *
7
 * References:
8
 *
9
 *  1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
10
 *     Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
11
 *     1995.
12
 *
13
 *  2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
14
 *     Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
15
 *     RRD-B30M75, National Semiconductor, March, 1991.
16
 *
17
 *  COPYRIGHT (c) 1989-1997.
18
 *  On-Line Applications Research Corporation (OAR).
19
 *  Copyright assigned to U.S. Government, 1994.
20
 *
21
 *  The license and distribution terms for this file may be
22
 *  found in the file LICENSE in this distribution or at
23
 *  http://www.OARcorp.com/rtems/license.html.
24
 *
25
 *  $Id: sonic.h,v 1.2 2001-09-27 12:01:41 chris Exp $
26
 */
27
 
28
#ifndef _SONIC_DP83932_
29
#define _SONIC_DP83932_
30
 
31
 
32
 /*
33
  * Debug levels
34
  *
35
  */
36
 
37
#define SONIC_DEBUG_NONE                0x0000
38
#define SONIC_DEBUG_ALL                 0xFFFF
39
#define SONIC_DEBUG_PRINT_REGISTERS     0x0001
40
#define SONIC_DEBUG_MEMORY              0x0002
41
#define SONIC_DEBUG_MEMORY_ALLOCATE     0x0004
42
#define SONIC_DEBUG_MEMORY_DESCRIPTORS  0x0008
43
#define SONIC_DEBUG_FRAGMENTS           0x0008
44
#define SONIC_DEBUG_CAM                 0x0010
45
#define SONIC_DEBUG_DESCRIPTORS         0x0020
46
#define SONIC_DEBUG_ERRORS              0x0040
47
#define SONIC_DEBUG_DUMP_TX_MBUFS       0x0080
48
#define SONIC_DEBUG_DUMP_RX_MBUFS       0x0100
49
 
50
#define SONIC_DEBUG_DUMP_MBUFS \
51
      (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS)
52
 
53
#define SONIC_DEBUG  (SONIC_DEBUG_NONE)
54
/*
55
#define SONIC_DEBUG  (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\
56
      SONIC_DEBUG_DESCRIPTORS)
57
*/
58
 
59
/*
60
  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS))
61
  ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS))
62
*/
63
 
64
#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
65
extern char SONIC_Reg_name[64][6];
66
#endif
67
 
68
 
69
/*
70
 *  Configuration Information
71
 */
72
 
73
typedef void (*sonic_write_register_t)(
74
  void       *base,
75
  unsigned32  regno,
76
  unsigned32  value
77
);
78
 
79
typedef unsigned32 (*sonic_read_register_t)(
80
  void       *base,
81
  unsigned32  regno
82
);
83
 
84
typedef struct {
85
  unsigned32              base_address;
86
  unsigned32              vector;
87
  unsigned32              dcr_value;
88
  unsigned32              dc2_value;
89
  unsigned32              tda_count;
90
  unsigned32              rda_count;
91
  sonic_write_register_t  write_register;
92
  sonic_read_register_t   read_register;
93
} sonic_configuration_t;
94
 
95
/*
96
 ******************************************************************
97
 *                                                                *
98
 *                        Device Registers                        *
99
 *                                                                *
100
 ******************************************************************
101
 */
102
#define SONIC_REG_CR      0x00 /* Command */
103
#define SONIC_REG_DCR     0x01 /* Data configuration */
104
#define SONIC_REG_RCR     0x02 /* Receive control */
105
#define SONIC_REG_TCR     0x03 /* Transmit control */
106
#define SONIC_REG_IMR     0x04 /* Interrupt mask */
107
#define SONIC_REG_ISR     0x05 /* Interrupt status */
108
#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
109
#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
110
#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
111
#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
112
#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
113
#define SONIC_REG_URRA    0x14 /* Upper receive resource */
114
#define SONIC_REG_RSA     0x15 /* Resource start address */
115
#define SONIC_REG_REA     0x16 /* Resource end address */
116
#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
117
#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
118
#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
119
#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
120
#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
121
#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
122
#define SONIC_REG_CE      0x25 /* CAM enable */
123
#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
124
#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
125
#define SONIC_REG_SR      0x28 /* Silicon revision */
126
#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
127
#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
128
#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
129
#define SONIC_REG_CRCT    0x2C /* CRC error tally */
130
#define SONIC_REG_FAET    0x2D /* FAE tally */
131
#define SONIC_REG_MPT     0x2E /* Missed packet tally */
132
#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
133
#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
134
 
135
/*
136
 * Command register
137
 */
138
#define CR_LCAM         0x0200
139
#define CR_RRRA         0x0100
140
#define CR_RST          0x0080
141
#define CR_ST           0x0020
142
#define CR_STP          0x0010
143
#define CR_RXEN         0x0008
144
#define CR_RXDIS        0x0004
145
#define CR_TXP          0x0002
146
#define CR_HTX          0x0001
147
 
148
/*
149
 * Data configuration register
150
 */
151
#define DCR_EXBUS       0x8000
152
#define DCR_LBR         0x2000
153
#define DCR_PO1         0x1000
154
#define DCR_PO0         0x0800
155
#define DCR_SBUS        0x0400
156
#define DCR_USR1        0x0200
157
#define DCR_USR0        0x0100
158
#define DCR_WC1         0x0080
159
#define DCR_WC0         0x0040
160
#define DCR_DW          0x0020
161
#define DCR_BMS         0x0010
162
#define DCR_RFT1        0x0008
163
#define DCR_RFT0        0x0004
164
#define DCR_TFT1        0x0002
165
#define DCR_TFT0        0x0001
166
 
167
/* data configuration register aliases */
168
#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
169
#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
170
 
171
#define DCR_WAIT0       0                 /* 0 wait states added */
172
#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
173
#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
174
#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
175
 
176
#define DCR_DW16        0       /* use 16-bit DMA accesses */
177
#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
178
 
179
#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
180
#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
181
 
182
#define DCR_RFT4        0               /* receive threshold 4 bytes */
183
#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
184
#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
185
#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
186
 
187
#define DCR_TFT8        0               /* transmit threshold 8 bytes */
188
#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
189
#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
190
#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
191
 
192
/*
193
 * Receive control register
194
 */
195
#define RCR_ERR         0x8000
196
#define RCR_RNT         0x4000
197
#define RCR_BRD         0x2000
198
#define RCR_PRO         0x1000
199
#define RCR_AMC         0x0800
200
#define RCR_LB1         0x0400
201
#define RCR_LB0         0x0200
202
#define RCR_MC          0x0100
203
#define RCR_BC          0x0080
204
#define RCR_LPKT        0x0040
205
#define RCR_CRS         0x0020
206
#define RCR_COL         0x0010
207
#define RCR_CRCR        0x0008
208
#define RCR_FAER        0x0004
209
#define RCR_LBK         0x0002
210
#define RCR_PRX         0x0001
211
 
212
/*
213
 * Transmit control register
214
 */
215
#define TCR_PINT        0x8000
216
#define TCR_POWC        0x4000
217
#define TCR_CRCI        0x2000
218
#define TCR_EXDIS       0x1000
219
#define TCR_EXD         0x0400
220
#define TCR_DEF         0x0200
221
#define TCR_NCRS        0x0100
222
#define TCR_CRSL        0x0080
223
#define TCR_EXC         0x0040
224
#define TCR_OWC         0x0020
225
#define TCR_PMB         0x0008
226
#define TCR_FU          0x0004
227
#define TCR_BCM         0x0002
228
#define TCR_PTX         0x0001
229
 
230
/*
231
 * Interrupt mask register
232
 */
233
#define IMR_BREN        0x4000
234
#define IMR_HBLEN       0x2000
235
#define IMR_LCDEN       0x1000
236
#define IMR_PINTEN      0x0800
237
#define IMR_PRXEN       0x0400
238
#define IMR_PTXEN       0x0200
239
#define IMR_TXEREN      0x0100
240
#define IMR_TCEN        0x0080
241
#define IMR_RDEEN       0x0040
242
#define IMR_RBEEN       0x0020
243
#define IMR_RBAEEN      0x0010
244
#define IMR_CRCEN       0x0008
245
#define IMR_FAEEN       0x0004
246
#define IMR_MPEN        0x0002
247
#define IMR_RFOEN       0x0001
248
 
249
/*
250
 * Interrupt status register
251
 */
252
#define ISR_BR          0x4000
253
#define ISR_HBL         0x2000
254
#define ISR_LCD         0x1000
255
#define ISR_PINT        0x0800
256
#define ISR_PKTRX       0x0400
257
#define ISR_TXDN        0x0200
258
#define ISR_TXER        0x0100
259
#define ISR_TC          0x0080
260
#define ISR_RDE         0x0040
261
#define ISR_RBE         0x0020
262
#define ISR_RBAE        0x0010
263
#define ISR_CRC         0x0008
264
#define ISR_FAE         0x0004
265
#define ISR_MP          0x0002
266
#define ISR_RFO         0x0001
267
 
268
/*
269
 * Data configuration register 2
270
 */
271
#define DCR2_EXPO3      0x8000
272
#define DCR2_EXPO2      0x4000
273
#define DCR2_EXPO1      0x2000
274
#define DCR2_EXPO0      0x1000
275
#define DCR2_HBDIS      0x0800
276
#define DCR2_PH         0x0010
277
#define DCR2_PCM        0x0004
278
#define DCR2_PCNM       0x0002
279
#define DCR2_RJCM       0x0001
280
 
281
/*
282
 *  Known values for the Silicon Revision Register.
283
 *  Note that DP83934 has revision 5 and seems to work.
284
 */
285
 
286
#define SONIC_REVISION_B   4
287
#define SONIC_REVISION_DP83934   5
288
#define SONIC_REVISION_C   6
289
 
290
/*
291
 ******************************************************************
292
 *                                                                *
293
 *                   Transmit Buffer Management                   *
294
 *                                                                *
295
 ******************************************************************
296
 */
297
 
298
/*
299
 * Transmit descriptor area entry.
300
 * There is one transmit descriptor for each packet to be transmitted.
301
 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
302
 * per descriptor.
303
 */
304
#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
305
struct TransmitDescriptor {
306
  rtems_unsigned32        status;
307
  rtems_unsigned32        pkt_config;
308
  rtems_unsigned32        pkt_size;
309
  rtems_unsigned32        frag_count;
310
 
311
  /*
312
   * Packet fragment pointers
313
   */
314
  struct TransmitDescriptorFragLink {
315
      rtems_unsigned32 frag_lsw;  /* LSW of fragment address */
316
#define                      frag_link frag_lsw
317
      rtems_unsigned32 frag_msw;  /* MSW of fragment address */
318
      rtems_unsigned32 frag_size;
319
  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
320
 
321
  /*
322
   * Space for link if all fragment pointers are used.
323
   */
324
  rtems_unsigned32        link_pad;
325
 
326
  /*
327
   * Extra RTEMS stuff
328
   */
329
  struct TransmitDescriptor       *next;  /* Circularly-linked list */
330
  struct mbuf                     *mbufp; /* First mbuf in packet */
331
  volatile rtems_unsigned32       *linkp; /* Pointer to un[xxx].link */
332
};
333
typedef struct TransmitDescriptor TransmitDescriptor_t;
334
typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
335
 
336
/*
337
 * Transmit Configuration.
338
 * For standard Ethernet transmission, all bits in the transmit
339
 * configuration field are set to 0.
340
 */
341
#define TDA_CONFIG_PINT 0x8000
342
#define TDA_CONFIG_POWC 0x4000
343
#define TDA_CONFIG_CRCI 0x2000
344
#define TDA_CONFIG_EXDIS        0x1000
345
 
346
/*
347
 * Transmit status
348
 */
349
#define TDA_STATUS_COLLISION_MASK       0xF800
350
#define TDA_STATUS_COLLISION_SHIFT      11
351
#define TDA_STATUS_EXD          0x0400
352
#define TDA_STATUS_DEF          0x0200
353
#define TDA_STATUS_NCRS         0x0100
354
#define TDA_STATUS_CRSL         0x0080
355
#define TDA_STATUS_EXC          0x0040
356
#define TDA_STATUS_OWC          0x0020
357
#define TDA_STATUS_PMB          0x0008
358
#define TDA_STATUS_FU           0x0004
359
#define TDA_STATUS_BCM          0x0002
360
#define TDA_STATUS_PTX          0x0001
361
 
362
#define TDA_LINK_EOL      0x0001
363
#define TDA_LINK_EOL_MASK 0xFFFE
364
 
365
 
366
 
367
/*
368
 ******************************************************************
369
 *                                                                *
370
 *                    Receive Buffer Management                   *
371
 *                                                                *
372
 ******************************************************************
373
 */
374
 
375
/*
376
 * Receive resource area entry.
377
 * There is one receive resource entry for each receive buffer area (RBA).
378
 * This driver allows only one packet per receive buffer area, so one
379
 * receive resource entry corresponds to one correctly-received packet.
380
 */
381
struct ReceiveResource {
382
  rtems_unsigned32        buff_ptr_lsw;   /* LSW of RBA address */
383
  rtems_unsigned32        buff_ptr_msw;   /* MSW of RBA address */
384
  rtems_unsigned32        buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
385
  rtems_unsigned32        buff_wc_msw;    /* MSW of RBA size (16-bit words) */
386
};
387
typedef struct ReceiveResource ReceiveResource_t;
388
typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
389
 
390
/*
391
 * Receive descriptor area entry.
392
 * There is one receive descriptor for each packet received.
393
 */
394
struct ReceiveDescriptor {
395
  rtems_unsigned32        status;
396
  rtems_unsigned32        byte_count;
397
  rtems_unsigned32        pkt_lsw;        /* LSW of packet address */
398
  rtems_unsigned32        pkt_msw;        /* MSW of packet address */
399
  rtems_unsigned32        seq_no;
400
  rtems_unsigned32        link;
401
  rtems_unsigned32        in_use;
402
 
403
  /*
404
   * Extra RTEMS stuff
405
   */
406
  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
407
  struct mbuf                        *mbufp; /* First mbuf in packet */
408
};
409
typedef struct ReceiveDescriptor ReceiveDescriptor_t;
410
typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
411
 
412
typedef struct {
413
  rtems_unsigned32  cep;  /* CAM Entry Pointer */
414
  rtems_unsigned32  cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
415
  rtems_unsigned32  cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
416
  rtems_unsigned32  cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
417
  rtems_unsigned32  ce;
418
} CamDescriptor_t;
419
 
420
typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
421
 
422
/*
423
 * Receive status
424
 */
425
#define RDA_STATUS_ERR          0x8800
426
#define RDA_STATUS_RNT          0x4000
427
#define RDA_STATUS_BRD          0x2000
428
#define RDA_STATUS_PRO          0x1000
429
#define RDA_STATUS_AMC          0x0800
430
#define RDA_STATUS_LB1          0x0400
431
#define RDA_STATUS_LB0          0x0200
432
#define RDA_STATUS_MC           0x0100
433
#define RDA_STATUS_BC           0x0080
434
#define RDA_STATUS_LPKT         0x0040
435
#define RDA_STATUS_CRS          0x0020
436
#define RDA_STATUS_COL          0x0010
437
#define RDA_STATUS_CRCR         0x0008
438
#define RDA_STATUS_FAER         0x0004
439
#define RDA_STATUS_LBK          0x0002
440
#define RDA_STATUS_PRX          0x0001
441
 
442
#define RDA_LINK_EOL        0x0001
443
#define RDA_LINK_EOL_MASK   0xFFFE
444
#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
445
                                    /*   and the driver can process it */
446
#define RDA_FREE            0xFFFF  /* SONIC can use it */
447
 
448
/*
449
 *  Attatch routine
450
 */
451
 
452
int rtems_sonic_driver_attach (
453
  struct rtems_bsdnet_ifconfig *config,
454
  sonic_configuration_t *chip
455
);
456
 
457
#ifdef CPU_U32_FIX
458
void ipalign(struct mbuf *m);
459
#endif
460
 
461
#endif /* _SONIC_DP83932_ */

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