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748 |
lampret |
#define ETH_REG_BASE ETH_BASE
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#define ETH_BD_BASE ETH_BASE + 0x400
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#define ETH_TOTAL_BD 128
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#define ETH_MAXBUF_LEN 0x600
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/* Tx BD */
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#define ETH_TX_BD_READY 0x8000 /* Tx BD Ready */
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#define ETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */
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#define ETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */
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#define ETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */
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#define ETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */
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#define ETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
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#define ETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */
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#define ETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */
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#define ETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */
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#define ETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
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#define ETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
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/* Rx BD */
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#define ETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
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#define ETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */
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#define ETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */
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#define ETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */
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#define ETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */
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#define ETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */
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#define ETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */
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#define ETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */
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#define ETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */
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#define ETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
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#define ETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
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/* Register space */
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#define ETH_MODER 0x00 /* Mode Register */
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#define ETH_INT 0x04 /* Interrupt Source Register */
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#define ETH_INT_MASK 0x08 /* Interrupt Mask Register */
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#define ETH_IPGT 0x0C /* Back to Bak Inter Packet Gap Register */
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#define ETH_IPGR1 0x10 /* Non Back to Back Inter Packet Gap Register 1 */
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#define ETH_IPGR2 0x14 /* Non Back to Back Inter Packet Gap Register 2 */
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#define ETH_PACKETLEN 0x18 /* Packet Length Register (min. and max.) */
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#define ETH_COLLCONF 0x1C /* Collision and Retry Configuration Register */
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#define ETH_RX_BD_NUM 0x20 /* Receive Buffer Descriptor Number Register */
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#define ETH_CTRLMODER 0x24 /* Control Module Mode Register */
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#define ETH_MIIMODER 0x28 /* MII Mode Register */
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#define ETH_MIICOMMAND 0x2C /* MII Command Register */
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#define ETH_MIIADDRESS 0x30 /* MII Address Register */
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#define ETH_MIITX_DATA 0x34 /* MII Transmit Data Register */
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#define ETH_MIIRX_DATA 0x38 /* MII Receive Data Register */
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#define ETH_MIISTATUS 0x3C /* MII Status Register */
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#define ETH_MAC_ADDR0 0x40 /* MAC Individual Address Register 0 */
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#define ETH_MAC_ADDR1 0x44 /* MAC Individual Address Register 1 */
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#define ETH_HASH_ADDR0 0x48 /* Hash Register 0 */
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#define ETH_HASH_ADDR1 0x4C /* Hash Register 1 */
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/* MODER Register */
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#define ETH_MODER_RXEN 0x00000001 /* Receive Enable */
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#define ETH_MODER_TXEN 0x00000002 /* Transmit Enable */
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#define ETH_MODER_NOPRE 0x00000004 /* No Preamble */
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#define ETH_MODER_BRO 0x00000008 /* Reject Broadcast */
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#define ETH_MODER_IAM 0x00000010 /* Use Individual Hash */
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#define ETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */
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#define ETH_MODER_IFG 0x00000040 /* Min. IFG not required */
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#define ETH_MODER_LOOPBCK 0x00000080 /* Loop Back */
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#define ETH_MODER_NOBCKOF 0x00000100 /* No Backoff */
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#define ETH_MODER_EXDFREN 0x00000200 /* Excess Defer */
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#define ETH_MODER_FULLD 0x00000400 /* Full Duplex */
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#define ETH_MODER_RST 0x00000800 /* Reset MAC */
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#define ETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
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#define ETH_MODER_CRCEN 0x00002000 /* CRC Enable */
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#define ETH_MODER_HUGEN 0x00004000 /* Huge Enable */
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#define ETH_MODER_PAD 0x00008000 /* Pad Enable */
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#define ETH_MODER_RECSMALL 0x00010000 /* Receive Small */
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/* Interrupt Source Register */
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#define ETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */
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#define ETH_INT_TXE 0x00000002 /* Transmit Error IRQ */
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#define ETH_INT_RXF 0x00000004 /* Receive Frame IRQ */
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#define ETH_INT_RXE 0x00000008 /* Receive Error IRQ */
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#define ETH_INT_BUSY 0x00000010 /* Busy IRQ */
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#define ETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */
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#define ETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */
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/* Interrupt Mask Register */
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#define ETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */
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#define ETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */
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#define ETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */
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#define ETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */
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#define ETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */
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#define ETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */
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#define ETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */
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/* Control Module Mode Register */
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#define ETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
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#define ETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */
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#define ETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */
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| 100 |
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/* MII Mode Register */
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| 101 |
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#define ETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */
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#define ETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */
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#define ETH_MIIMODER_RST 0x00000200 /* MIIM Reset */
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| 104 |
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| 105 |
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/* MII Command Register */
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| 106 |
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#define ETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */
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| 107 |
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#define ETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */
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#define ETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
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| 109 |
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| 110 |
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/* MII Address Register */
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| 111 |
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#define ETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
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| 112 |
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#define ETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
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| 113 |
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| 114 |
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/* MII Status Register */
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| 115 |
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#define ETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
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| 116 |
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#define ETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */
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| 117 |
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#define ETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */
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| 118 |
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