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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [except_test.c] - Blame information for rev 516

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1 516 markom 
/* This is exception test for OpenRISC 1200 */
2 
 
3 
#include "spr_defs.h"
4 
#include "support.h"
5 
#include "int.h"
6 
 
7 
/* Define RAM physical location and size
8 
   Bottom half will be used for this program, the rest
9 
   will be used for testing */
10 
#define FLASH_START 0x00000000
11 
#define FLASH_SIZE  0x00200000
12 
#define RAM_START   0x40000000
13 
#define RAM_SIZE    0x00200000
14 
 
15 
/* MMU page size */
16 
#define PAGE_SIZE 8192
17 
 
18 
/* Number of DTLB sets used (power of 2, max is 256) */
19 
#define DTLB_SETS 32
20 
 
21 
/* Number of DTLB ways (2, 2, 3 etc., max is 4). */
22 
#define DTLB_WAYS 1
23 
 
24 
/* Number of ITLB sets used (power of 2, max is 256) */
25 
#define ITLB_SETS 32
26 
 
27 
/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
28 
#define ITLB_WAYS 1
29 
 
30 
/* TLB mode codes */
31 
#define TLB_CODE_ONE_TO_ONE     0x00000000
32 
#define TLB_CODE_PLUS_ONE_PAGE  0x10000000
33 
#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
34 
 
35 
#define TLB_TEXT_SET_NB 6
36 
#define TLB_DATA_SET_NB 2
37 
 
38 
#define TLB_CODE_MASK   0xfffff000
39 
#define TLB_PR_MASK     0x00000fff
40 
#define DTLB_PR_NOLIMIT  ( SPR_DTLBTR_CI   | \
41 
                          SPR_DTLBTR_URE  | \
42 
                          SPR_DTLBTR_UWE  | \
43 
                          SPR_DTLBTR_SRE  | \
44 
                          SPR_DTLBTR_SWE  )
45 
 
46 
#define ITLB_PR_NOLIMIT  ( SPR_ITLBTR_CI   | \
47 
                          SPR_ITLBTR_SXE  | \
48 
                          SPR_ITLBTR_UXE  )
49 
 
50 
/* fails if x is false */
51 
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
52 
 
53 
/* Exception vectors */
54 
#define V_RESET       1
55 
#define V_BERR        2
56 
#define V_DPF         3
57 
#define V_IPF         4
58 
#define V_LPINT       5
59 
#define V_ALIGN       6
60 
#define V_ILLINSN     7
61 
#define V_HPINT       8
62 
#define V_DTLB_MISS   9
63 
#define V_ITLB_MISS   10
64 
#define V_RANGE       11
65 
#define V_SYS         12
66 
#define V_TRAP        14
67 
 
68 
#if 1
69 
#define debug printf
70 
#else
71 
#define debug
72 
#endif
73 
 
74 
/* Extern functions */
75 
extern void lo_dmmu_en (void);
76 
extern void lo_immu_en (void);
77 
extern unsigned long call (unsigned long add, unsigned long val);
78 
extern unsigned long call_with_int (unsigned long add, unsigned long val);
79 
extern void trap (void);
80 
extern void b_trap (void);
81 
extern void range (void);
82 
extern void b_range (void);
83 
extern int except_basic (void);
84 
extern void (*test)(void);
85 
extern int load_acc_32 (unsigned long add);
86 
extern int load_acc_16 (unsigned long add);
87 
extern int store_acc_32 (unsigned long add);
88 
extern int store_acc_16 (unsigned long add);
89 
extern int load_b_acc_32 (unsigned long add);
90 
extern int int_trigger (void);
91 
extern int int_loop (void);
92 
extern int jump_back (void);
93 
 
94 
/* Local functions prototypes */
95 
void dmmu_disable (void);
96 
void immu_disable (void);
97 
 
98 
/* DTLB mode status */
99 
volatile unsigned long dtlb_val;
100 
 
101 
/* ITLB mode status */
102 
volatile unsigned long itlb_val;
103 
 
104 
/* Exception counter */
105 
volatile int except_count;
106 
 
107 
/* Exception mask */
108 
volatile unsigned long except_mask;
109 
 
110 
/* Exception efective address */
111 
volatile unsigned long except_ea;
112 
 
113 
/* Eception PC */
114 
volatile unsigned long except_pc;
115 
 
116 
void fail (char *func, int line)
117 
{
118 
#ifndef __FUNCTION__
119 
#define __FUNCTION__ "?"
120 
#endif
121 
 
122 
  immu_disable ();
123 
  dmmu_disable ();
124 
 
125 
  debug("Test failed in %s:%i\n", func, line);
126 
  report (0xeeeeeeee);
127 
  exit (1);
128 
}
129 
 
130 
void test_dummy (void)
131 
{
132 
        asm("_test:");
133 
        asm("l.addi\t\tr3,r3,1") ;
134 
        asm("l.nop" : :);
135 
}
136 
 
137 
void copy_test (unsigned long phy_add)
138 
{
139 
        memcpy((void *)phy_add, (void *)&test, 8);
140 
}
141 
 
142 
/* Bus error handler */
143 
void bus_err_handler (void)
144 
{
145 
 
146 
  except_mask |= 1 << V_BERR;
147 
  except_count++;
148 
}
149 
 
150 
/* Illegal insn handler */
151 
void ill_insn_handler (void)
152 
{
153 
 
154 
  except_mask |= 1 << V_ILLINSN;
155 
  except_count++;
156 
}
157 
 
158 
/* Low priority interrupt handler */
159 
void lp_int_handler (void)
160 
{
161 
 
162 
  /* Disable interrupt recognition */
163 
  mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_EIR);
164 
 
165 
  except_mask |= 1 << V_LPINT;
166 
  except_count++;
167 
}
168 
 
169 
/* High priority interrupt handler */
170 
void hp_int_handler (void)
171 
{
172 
 
173 
  /* Disable interrupt recognition */
174 
  mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_EIR);
175 
 
176 
  except_mask |= 1 << V_HPINT;
177 
  except_count++;
178 
}
179 
 
180 
/* Trap handler */
181 
void trap_handler (void)
182 
{
183 
 
184 
  except_mask |= 1 << V_TRAP;
185 
  except_count++;
186 
}
187 
 
188 
/* Align handler */
189 
void align_handler (void)
190 
{
191 
 
192 
  except_mask |= 1 << V_ALIGN;
193 
  except_count++;
194 
}
195 
 
196 
/* Range handler */
197 
void range_handler (void)
198 
{
199 
  /* Disable range exception */
200 
  mtspr (SPR_ESR_BASE, mfspr (SPR_ESR_BASE) & ~SPR_SR_OVE);
201 
 
202 
  except_mask |= 1 << V_RANGE;
203 
  except_count++;
204 
}
205 
 
206 
/* DTLB miss exception handler */
207 
void dtlb_miss_handler (void)
208 
{
209 
  unsigned long ea;
210 
  int set, way = 0;
211 
  int i;
212 
 
213 
  /* Get EA that cause the exception */
214 
  ea = mfspr (SPR_EEAR_BASE);
215 
 
216 
  /* Find TLB set and LRU way */
217 
  set = (ea / PAGE_SIZE) % DTLB_SETS;
218 
  for (i = 0; i < DTLB_WAYS; i++) {
219 
    if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
220 
      way = i;
221 
      break;
222 
    }
223 
  }
224 
 
225 
  mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
226 
  mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | dtlb_val);
227 
 
228 
  except_mask |= 1 << V_DTLB_MISS;
229 
  except_count++;
230 
}
231 
 
232 
/* ITLB miss exception handler */
233 
void itlb_miss_handler (void)
234 
{
235 
  unsigned long ea;
236 
  int set, way = 0;
237 
  int i;
238 
 
239 
  /* Get EA that cause the exception */
240 
  ea = mfspr (SPR_EEAR_BASE);
241 
 
242 
  /* Find TLB set and LRU way */
243 
  set = (ea / PAGE_SIZE) % ITLB_SETS;
244 
  for (i = 0; i < ITLB_WAYS; i++) {
245 
    if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {
246 
      way = i;
247 
      break;
248 
    }
249 
  }
250 
 
251 
  mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
252 
  mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | itlb_val);
253 
  except_mask |= 1 << V_ITLB_MISS;
254 
  except_count++;
255 
}
256 
 
257 
/* Data page fault exception handler */
258 
void dpage_fault_handler (void)
259 
{
260 
  unsigned long ea;
261 
  int set, way = 0;
262 
  int i;
263 
 
264 
  /* Get EA that cause the exception */
265 
  ea = mfspr (SPR_EEAR_BASE);
266 
 
267 
  /* Find TLB set and way */
268 
  set = (ea / PAGE_SIZE) % DTLB_SETS;
269 
  for (i = 0; i < DTLB_WAYS; i++) {
270 
    if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) == (ea & SPR_DTLBMR_VPN)) {
271 
      way = i;
272 
      break;
273 
    }
274 
  }
275 
 
276 
  /* Give permission */
277 
  mtspr (SPR_DTLBTR_BASE(way) + set, (mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);
278 
 
279 
  except_mask |= 1 << V_DPF;
280 
  except_count++;
281 
}
282 
 
283 
/* Intstruction page fault exception handler */
284 
void ipage_fault_handler (void)
285 
{
286 
  unsigned long ea;
287 
  int set, way = 0;
288 
  int i;
289 
 
290 
  /* Get EA that cause the exception */
291 
  ea = mfspr (SPR_EEAR_BASE);
292 
 
293 
  /* Find TLB set and way */
294 
  set = (ea / PAGE_SIZE) % ITLB_SETS;
295 
  for (i = 0; i < ITLB_WAYS; i++) {
296 
    if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_VPN) == (ea & SPR_ITLBMR_VPN)) {
297 
      way = i;
298 
      break;
299 
    }
300 
  }
301 
 
302 
  /* Give permission */
303 
  mtspr (SPR_ITLBTR_BASE(way) + set, (mfspr (SPR_ITLBTR_BASE(way) + set) & ~ITLB_PR_NOLIMIT) | itlb_val);
304 
 
305 
  except_mask |= 1 << V_IPF;
306 
  except_count++;
307 
}
308 
 
309 
/*Enable DMMU */
310 
void dmmu_enable (void)
311 
{
312 
  /* Enable DMMU */
313 
  lo_dmmu_en ();
314 
}
315 
 
316 
/* Disable DMMU */
317 
void dmmu_disable (void)
318 
{
319 
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);
320 
}
321 
 
322 
/* Enable IMMU */
323 
void immu_enable (void)
324 
{
325 
  /* Enable IMMU */
326 
  lo_immu_en ();
327 
}
328 
 
329 
/* Disable IMMU */
330 
void immu_disable (void)
331 
{
332 
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);
333 
}
334 
 
335 
/* Tick timer init */
336 
void tick_init (int period, int hp_int)
337 
{
338 
  /* Disable interrupt recognition */
339 
  mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);
340 
 
341 
  /* Set period of one cycle, restartable mode */
342 
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
343 
 
344 
  /* Set tick priority */
345 
  if (hp_int)
346 
    mtspr(SPR_PICPR, mfspr(SPR_PICPR) | (0x00000001L << V_TICK));
347 
  else
348 
    mtspr(SPR_PICPR, mfspr(SPR_PICPR) & ~(0x00000001L << V_TICK));
349 
 
350 
  /* Reset counter */
351 
  mtspr(SPR_TTCR, 0);
352 
 
353 
  /* Unmask tick interrupt in PIC */
354 
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << V_TICK));
355 
}
356 
 
357 
/* Interrupt test */
358 
int interrupt_test (void)
359 
{
360 
  unsigned long ret;
361 
  int i;
362 
 
363 
  /* Init tick timer */
364 
  tick_init (1, 1);
365 
 
366 
  /* Reset except counter */
367 
  except_count = 0;
368 
  except_mask = 0;
369 
  except_pc = 0;
370 
  except_ea = 0;
371 
 
372 
  /* Test normal high priority interrupt trigger */
373 
  ret = call ((unsigned long)&int_trigger, 0);
374 
  ASSERT(except_count == 1);
375 
  ASSERT(except_mask == (1 << V_HPINT));
376 
  ASSERT(ret == 0);
377 
  ASSERT(except_pc == (unsigned long)int_trigger + 16);
378 
  ASSERT(except_ea == 0);
379 
 
380 
  /* Reset except counter */
381 
  except_count = 0;
382 
  except_mask = 0;
383 
  except_pc = 0;
384 
  except_ea = 0;
385 
 
386 
  /* Init tick timer */
387 
  tick_init (1, 0);
388 
 
389 
  /* Test normal low priority interrupt trigger */
390 
  ret = call ((unsigned long)&int_trigger, 0);
391 
  ASSERT(except_count == 1);
392 
  ASSERT(except_mask == (1 << V_LPINT));
393 
  ASSERT(ret == 0);
394 
  ASSERT(except_pc == (unsigned long)int_trigger + 16);
395 
  ASSERT(except_ea == 0);
396 
 
397 
  /* Reset except counter */
398 
  except_count = 0;
399 
  except_mask = 0;
400 
  except_pc = 0;
401 
  except_ea = 0;
402 
 
403 
  /* Test inetrrupt in delay slot */
404 
  tick_init (10, 1);
405 
 
406 
  /* Hopefully we will have interrupt recognition between branch insn and delay slot */
407 
  except_pc = (unsigned long)&int_loop;
408 
  for (i = 0; i < 10; i++) {
409 
    call_with_int (except_pc, RAM_START);
410 
    ASSERT(except_pc == (unsigned long)&int_loop);
411 
  }
412 
 
413 
  return 0;
414 
}
415 
 
416 
/* ITLB miss test */
417 
int itlb_test (void)
418 
{
419 
  int i, j, ret;
420 
  unsigned long ea, ta;
421 
 
422 
  /* Invalidate all entries in ITLB */
423 
  for (i = 0; i < ITLB_WAYS; i++) {
424 
    for (j = 0; j < ITLB_SETS; j++) {
425 
      mtspr (SPR_ITLBMR_BASE(i) + j, 0);
426 
      mtspr (SPR_ITLBTR_BASE(i) + j, 0);
427 
    }
428 
  }
429 
 
430 
  /* Set one to one translation for the use of this program */
431 
  for (i = 0; i < TLB_TEXT_SET_NB; i++) {
432 
    ea = FLASH_START + (i*PAGE_SIZE);
433 
    ta = FLASH_START + (i*PAGE_SIZE);
434 
    mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
435 
    mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
436 
  }
437 
 
438 
  /* Set dtlb no permisions */
439 
  itlb_val = SPR_ITLBTR_CI;
440 
 
441 
  /* Reset except counter */
442 
  except_count = 0;
443 
  except_mask = 0;
444 
  except_pc = 0;
445 
  except_ea = 0;
446 
 
447 
  /* Enable IMMU */
448 
  immu_enable ();
449 
 
450 
  /* Copy jump instruction to last location of a page */
451 
  ea = RAM_START + (RAM_SIZE/2) + ((TLB_TEXT_SET_NB + 1)*PAGE_SIZE) - 8;
452 
  memcpy((void *)ea, (void *)&jump_back, 12);
453 
 
454 
  /* Check if there was ITLB miss exception */
455 
  ret = call (ea, 0);
456 
  ASSERT(except_count == 1);
457 
  ASSERT(except_mask == (1 << V_ITLB_MISS));
458 
  ASSERT(except_pc == ea);
459 
  ASSERT(except_ea == ea);
460 
  ASSERT(ret == 0);
461 
 
462 
  /* Set dtlb no permisions */
463 
  itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
464 
 
465 
  /* Reset except counter */
466 
  except_count = 0;
467 
  except_mask = 0;
468 
  except_pc = 0;
469 
  except_ea = 0;
470 
 
471 
  /* Check if there was IPF miss exception */
472 
  ret = call (ea, 0);
473 
  ASSERT(except_count == 1);
474 
  ASSERT(except_mask == (1 << V_IPF));
475 
  ASSERT(except_pc == ea);
476 
  ASSERT(except_ea == ea);
477 
  ASSERT(ret == 0);
478 
 
479 
  /* Set dtlb no permisions */
480 
  itlb_val = SPR_ITLBTR_CI;
481 
 
482 
  /* Reset except counter */
483 
  except_count = 0;
484 
  except_mask = 0;
485 
  except_pc = 0;
486 
  except_ea = 0;
487 
 
488 
  /* Check if there was ITLB miss exception */
489 
  ret = call (ea, 0);
490 
  ASSERT(except_count == 1);
491 
  ASSERT(except_mask == (1 << V_ITLB_MISS));
492 
  ASSERT(except_pc == ea + 4);
493 
  ASSERT(except_ea == ea + 8);
494 
  ASSERT(ret == 0);
495 
 
496 
  /* Set dtlb no permisions */
497 
  itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
498 
 
499 
  /* Reset except counter */
500 
  except_count = 0;
501 
  except_mask = 0;
502 
  except_pc = 0;
503 
  except_ea = 0;
504 
 
505 
  /* Check if there was IPF exception */
506 
  ret = call (ea, 0);
507 
  ASSERT(except_count == 1);
508 
  ASSERT(except_mask == (1 << V_IPF));
509 
  ASSERT(except_pc == ea + 4);
510 
  ASSERT(except_ea == ea + 8);
511 
  ASSERT(ret == 0);
512 
 
513 
  /* Reset except counter */
514 
  except_count = 0;
515 
  except_mask = 0;
516 
  except_pc = 0;
517 
  except_ea = 0;
518 
 
519 
  ret = call (ea, 0);
520 
  ASSERT(except_count == 0);
521 
  ASSERT(ret == 1);
522 
 
523 
  /* Disable IMMU */
524 
  immu_disable ();
525 
 
526 
  return 0;
527 
}
528 
 
529 
/* DTLB miss test */
530 
int dtlb_test (void)
531 
{
532 
  int i, j, ret;
533 
  unsigned long ea, ta;
534 
 
535 
  /* Invalidate all entries in DTLB */
536 
  for (i = 0; i < DTLB_WAYS; i++) {
537 
    for (j = 0; j < DTLB_SETS; j++) {
538 
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
539 
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
540 
    }
541 
  }
542 
 
543 
  /* Set one to one translation for the use of this program */
544 
  for (i = 0; i < TLB_DATA_SET_NB; i++) {
545 
    ea = RAM_START + (i*PAGE_SIZE);
546 
    ta = RAM_START + (i*PAGE_SIZE);
547 
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
548 
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
549 
  }
550 
 
551 
  /* Set dtlb no permisions */
552 
  dtlb_val = SPR_DTLBTR_CI;
553 
 
554 
  /* Reset except counter */
555 
  except_count = 0;
556 
  except_mask = 0;
557 
  except_pc = 0;
558 
  except_ea = 0;
559 
 
560 
  /* Set pattern */
561 
  ea = RAM_START + (RAM_SIZE/2) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
562 
  REG32(ea) = 0x87654321;
563 
 
564 
  /* Enable DMMU */
565 
  dmmu_enable ();
566 
 
567 
  /* Check if there was DTLB miss exception */
568 
  ret = call ((unsigned long)&load_b_acc_32, ea);
569 
  ASSERT(except_count == 1);
570 
  ASSERT(except_mask == (1 << V_DTLB_MISS));
571 
  ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
572 
  ASSERT(except_ea == ea);
573 
  ASSERT(ret == 0x12345678);
574 
 
575 
  /* Set dtlb no permisions */
576 
  dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
577 
 
578 
  /* Reset except counter */
579 
  except_count = 0;
580 
  except_mask = 0;
581 
  except_pc = 0;
582 
  except_ea = 0;
583 
 
584 
  /* Check if there was DPF miss exception */
585 
  ret = call ((unsigned long)&load_b_acc_32, ea);
586 
  ASSERT(except_count == 1);
587 
  ASSERT(except_mask == (1 << V_DPF));
588 
  ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
589 
  ASSERT(except_ea == ea);
590 
  ASSERT(ret == 0x12345678);
591 
 
592 
  /* Reset except counter */
593 
  except_count = 0;
594 
  except_mask = 0;
595 
  except_pc = 0;
596 
  except_ea = 0;
597 
 
598 
  ret = call ((unsigned long)&load_b_acc_32, ea);
599 
  ASSERT(except_count == 0);
600 
  ASSERT(ret == 0x87654321);
601 
 
602 
  /* Disable DMMU */
603 
  dmmu_disable ();
604 
 
605 
  return 0;
606 
}
607 
 
608 
/* Bus error test */
609 
int buserr_test (void)
610 
{
611 
  int i, j, ret;
612 
  unsigned long ea, ta;
613 
 
614 
  /* Invalidate all entries in ITLB */
615 
  for (i = 0; i < ITLB_WAYS; i++) {
616 
    for (j = 0; j < ITLB_SETS; j++) {
617 
      mtspr (SPR_ITLBMR_BASE(i) + j, 0);
618 
      mtspr (SPR_ITLBTR_BASE(i) + j, 0);
619 
    }
620 
  }
621 
 
622 
  /* Set one to one translation for the use of this program */
623 
  for (i = 0; i < TLB_TEXT_SET_NB; i++) {
624 
    ea = FLASH_START + (i*PAGE_SIZE);
625 
    ta = FLASH_START + (i*PAGE_SIZE);
626 
    mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
627 
    mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
628 
  }
629 
 
630 
  /* Invalidate all entries in DTLB */
631 
  for (i = 0; i < DTLB_WAYS; i++) {
632 
    for (j = 0; j < DTLB_SETS; j++) {
633 
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
634 
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
635 
    }
636 
  }
637 
 
638 
  /* Set one to one translation for the use of this program */
639 
  for (i = 0; i < TLB_DATA_SET_NB; i++) {
640 
    ea = RAM_START + (i*PAGE_SIZE);
641 
    ta = RAM_START + (i*PAGE_SIZE);
642 
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
643 
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
644 
  }
645 
 
646 
  /* Reset except counter */
647 
  except_count = 0;
648 
  except_mask = 0;
649 
  except_pc = 0;
650 
  except_ea = 0;
651 
 
652 
  /* Set IMMU translation */
653 
  ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
654 
  itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
655 
  mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
656 
  mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val);
657 
 
658 
  /* Enable IMMU */
659 
  immu_enable ();
660 
 
661 
  /* Check if there was bus error exception */
662 
  ret = call (ea, 0);
663 
  ASSERT(except_count == 1);
664 
  ASSERT(except_mask == (1 << V_BERR));
665 
printf("except_pc = %.8lx except_ea = %.8lx\n", except_pc, except_ea);
666 
  ASSERT(except_pc == ea);
667 
  ASSERT(except_ea == ea + PAGE_SIZE);
668 
 
669 
  /* Disable IMMU */
670 
  immu_disable ();
671 
 
672 
  /* Reset except counter */
673 
  except_count = 0;
674 
  except_mask = 0;
675 
  except_pc = 0;
676 
  except_ea = 0;
677 
 
678 
  /* Copy jump instruction to last location of RAM */
679 
  ea = RAM_START + RAM_SIZE - 8;
680 
  memcpy((void *)ea, (void *)&jump_back, 8);
681 
 
682 
  /* Check if there was bus error exception */
683 
  ret = call (ea, 0);
684 
  ASSERT(except_count == 1);
685 
  ASSERT(except_mask == (1 << V_BERR));
686 
  ASSERT(except_pc == ea + 4);
687 
  ASSERT(except_ea == ea + 8);
688 
 
689 
  /* Reset except counter */
690 
  except_count = 0;
691 
  except_mask = 0;
692 
  except_pc = 0;
693 
  except_ea = 0;
694 
 
695 
  /* Set DMMU translation */
696 
  ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
697 
  dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
698 
  mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
699 
  mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val);
700 
 
701 
  /* Enable DMMU */
702 
  dmmu_enable ();
703 
 
704 
  /* Check if there was bus error exception */
705 
  ret = call ((unsigned long)&load_acc_32, ea );
706 
  ASSERT(except_count == 1);
707 
  ASSERT(except_mask == (1 << V_BERR));
708 
  ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
709 
  ASSERT(except_ea == ea + PAGE_SIZE);
710 
  ASSERT(ret == 0x12345678);
711 
 
712 
  /* Disable DMMU */
713 
  dmmu_disable ();
714 
 
715 
  /* Reset except counter */
716 
  except_count = 0;
717 
  except_mask = 0;
718 
  except_pc = 0;
719 
  except_ea = 0;
720 
 
721 
  /* Check if there was bus error exception */
722 
  ret = call ((unsigned long)&load_b_acc_32, ea );
723 
  ASSERT(except_count == 1);
724 
  ASSERT(except_mask == (1 << V_BERR));
725 
  ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
726 
  ASSERT(except_ea == ea);
727 
  ASSERT(ret == 0x12345678);
728 
 
729 
  return 0;
730 
}
731 
 
732 
/* Illegal instruction test */
733 
int illegal_insn_test (void)
734 
{
735 
  int ret;
736 
 
737 
  /* Reset except counter */
738 
  except_count = 0;
739 
  except_mask = 0;
740 
  except_pc = 0;
741 
  except_ea = 0;
742 
 
743 
  /* Set illegal insn */
744 
  REG32(RAM_START + 0) = REG32((unsigned long)jump_back + 4);
745 
  REG32(RAM_START + 4) = 0xffffffff;
746 
 
747 
  /* Check if there was illegal insn exception */
748 
  ret = call (RAM_START + 4, 0 );
749 
  ASSERT(except_count == 1);
750 
  ASSERT(except_mask == (1 << V_ILLINSN));
751 
  ASSERT(except_pc == RAM_START + 4);
752 
  ASSERT(except_ea == RAM_START + 4);
753 
 
754 
  /* Reset except counter */
755 
  except_count = 0;
756 
  except_mask = 0;
757 
  except_pc = 0;
758 
  except_ea = 0;
759 
 
760 
  /* Check if there was illegal insn exception */
761 
  ret = call (RAM_START, 0 );
762 
  ASSERT(except_count == 1);
763 
  ASSERT(except_mask == (1 << V_ILLINSN));
764 
  ASSERT(except_pc == RAM_START);
765 
  ASSERT(except_ea == RAM_START + 4);
766 
 
767 
  return 0;
768 
}
769 
 
770 
/* Align test */
771 
int align_test (void)
772 
{
773 
  int ret;
774 
 
775 
  /* Reset except counter */
776 
  except_count = 0;
777 
  except_mask = 0;
778 
  except_pc = 0;
779 
  except_ea = 0;
780 
 
781 
  /* Check if there was alignment exception on read insn */
782 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
783 
  ASSERT(except_count == 1);
784 
  ASSERT(except_mask == (1 << V_ALIGN));
785 
  ASSERT(ret == 0x12345678);
786 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
787 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
788 
 
789 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
790 
  ASSERT(except_count == 2);
791 
  ASSERT(except_mask == (1 << V_ALIGN));
792 
  ASSERT(ret == 0x12345678);
793 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
794 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
795 
 
796 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
797 
  ASSERT(except_count == 3);
798 
  ASSERT(except_mask == (1 << V_ALIGN));
799 
  ASSERT(ret == 0x12345678);
800 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
801 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
802 
 
803 
  ret = call ((unsigned long)&load_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
804 
  ASSERT(except_count == 4);
805 
  ASSERT(except_mask == (1 << V_ALIGN));
806 
  ASSERT(ret == 0x12345678);
807 
  ASSERT(except_pc == ((unsigned long)(load_acc_16) + 8));
808 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
809 
 
810 
  /* Check alignment exception on write  insn */
811 
  call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
812 
  ASSERT(except_count == 5);
813 
  ASSERT(except_mask == (1 << V_ALIGN));
814 
  ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
815 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
816 
 
817 
  call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
818 
  ASSERT(except_count == 6);
819 
  ASSERT(except_mask == (1 << V_ALIGN));
820 
  ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
821 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
822 
 
823 
  call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
824 
  ASSERT(except_count == 7);
825 
  ASSERT(except_mask == (1 << V_ALIGN));
826 
  ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
827 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
828 
 
829 
  call ((unsigned long)&store_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
830 
  ASSERT(except_count == 8);
831 
  ASSERT(except_mask == (1 << V_ALIGN));
832 
  ASSERT(except_pc == ((unsigned long)(store_acc_16) + 8));
833 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
834 
 
835 
 
836 
  ret = call ((unsigned long)&load_b_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
837 
  ASSERT(except_count == 9);
838 
  ASSERT(except_mask == (1 << V_ALIGN));
839 
  ASSERT(ret == 0x12345678);
840 
  ASSERT(except_pc == ((unsigned long)(load_b_acc_32) + 8));
841 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
842 
 
843 
 
844 
  return 0;
845 
}
846 
 
847 
/* Trap test */
848 
int trap_test (void)
849 
{
850 
  /* Reset except counter */
851 
  except_count = 0;
852 
  except_mask = 0;
853 
  except_pc = 0;
854 
  except_ea = 0;
855 
 
856 
  /* Check if there was trap exception */
857 
  call ((unsigned long)&trap, 0);
858 
  ASSERT(except_count == 1);
859 
  ASSERT(except_mask == (1 << V_TRAP));
860 
  ASSERT(except_pc == (unsigned long)(trap));
861 
  ASSERT(except_ea == 0);
862 
 
863 
  /* Check if there was trap exception */
864 
  call ((unsigned long)&b_trap, 0);
865 
  ASSERT(except_count == 2);
866 
  ASSERT(except_mask == (1 << V_TRAP));
867 
  ASSERT(except_pc == (unsigned long)(b_trap));
868 
  ASSERT(except_ea == 0);
869 
 
870 
  return 0;
871 
}
872 
 
873 
/* Range test */
874 
int range_test (void)
875 
{
876 
  /* Reset except counter */
877 
  except_count = 0;
878 
  except_mask = 0;
879 
  except_pc = 0;
880 
  except_ea = 0;
881 
 
882 
  /* Check if there was range exception */
883 
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
884 
  call ((unsigned long)&range, 0);
885 
  ASSERT(except_count == 1);
886 
  ASSERT(except_mask == (1 << V_RANGE));
887 
  ASSERT(except_pc == (unsigned long)(range));
888 
  ASSERT(except_ea == 0);
889 
 
890 
  /* Check if there was range exception */
891 
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
892 
  call ((unsigned long)&b_range, 0);
893 
  ASSERT(except_count == 2);
894 
  ASSERT(except_mask == (1 << V_RANGE));
895 
  ASSERT(except_pc == (unsigned long)(b_range));
896 
  ASSERT(except_ea == 0);
897 
 
898 
  return 0;
899 
}
900 
 
901 
/* Exception priority test */
902 
void except_priority_test (void)
903 
{
904 
  int i, j;
905 
  unsigned long ea, ta, ret;
906 
 
907 
  /* Invalidate all entries in ITLB */
908 
  for (i = 0; i < ITLB_WAYS; i++) {
909 
    for (j = 0; j < ITLB_SETS; j++) {
910 
      mtspr (SPR_ITLBMR_BASE(i) + j, 0);
911 
      mtspr (SPR_ITLBTR_BASE(i) + j, 0);
912 
    }
913 
  }
914 
 
915 
  /* Set one to one translation for the use of this program */
916 
  for (i = 0; i < TLB_TEXT_SET_NB; i++) {
917 
    ea = FLASH_START + (i*PAGE_SIZE);
918 
    ta = FLASH_START + (i*PAGE_SIZE);
919 
    mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
920 
    mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
921 
  }
922 
 
923 
  /* Set dtlb no permisions */
924 
  itlb_val = SPR_ITLBTR_CI;
925 
 
926 
  /* Invalidate all entries in DTLB */
927 
  for (i = 0; i < DTLB_WAYS; i++) {
928 
    for (j = 0; j < DTLB_SETS; j++) {
929 
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
930 
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
931 
    }
932 
  }
933 
 
934 
  /* Set one to one translation for the use of this program */
935 
  for (i = 0; i < TLB_DATA_SET_NB; i++) {
936 
    ea = RAM_START + (i*PAGE_SIZE);
937 
    ta = RAM_START + (i*PAGE_SIZE);
938 
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
939 
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
940 
  }
941 
 
942 
  /* Init tick timer */
943 
  tick_init (1, 1);
944 
 
945 
  /* Set dtlb no permisions */
946 
  dtlb_val = SPR_DTLBTR_CI;
947 
 
948 
  /* Reset except counter */
949 
  except_count = 0;
950 
  except_mask = 0;
951 
  except_pc = 0;
952 
  except_ea = 0;
953 
 
954 
  /* Enable IMMU */
955 
  immu_enable ();
956 
 
957 
  /* Check if there was INT exception */
958 
  call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
959 
  ASSERT(except_count == 1);
960 
  ASSERT(except_mask == (1 << V_HPINT));
961 
  ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
962 
  ASSERT(except_ea == 0);
963 
 
964 
  /* Reset except counter */
965 
  except_count = 0;
966 
  except_mask = 0;
967 
  except_pc = 0;
968 
  except_ea = 0;
969 
 
970 
  /* Check if there was ITLB exception */
971 
  call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
972 
  ASSERT(except_count == 1);
973 
  ASSERT(except_mask == (1 << V_ITLB_MISS));
974 
  ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
975 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
976 
 
977 
  /* Set dtlb permisions */
978 
  itlb_val |= SPR_ITLBTR_SXE;
979 
 
980 
  /* Reset except counter */
981 
  except_count = 0;
982 
  except_mask = 0;
983 
  except_pc = 0;
984 
  except_ea = 0;
985 
 
986 
  /* Check if there was IPF exception */
987 
  call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
988 
  ASSERT(except_count == 1);
989 
  ASSERT(except_mask == (1 << V_IPF));
990 
  ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
991 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
992 
 
993 
  /* Reset except counter */
994 
  except_count = 0;
995 
  except_mask = 0;
996 
  except_pc = 0;
997 
  except_ea = 0;
998 
 
999 
  /* Check if there was bus error exception */
1000 
  call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
1001 
  ASSERT(except_count == 1);
1002 
  ASSERT(except_mask == (1 << V_BERR));
1003 
  ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
1004 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
1005 
 
1006 
  /* Reset except counter */
1007 
  except_count = 0;
1008 
  except_mask = 0;
1009 
  except_pc = 0;
1010 
  except_ea = 0;
1011 
 
1012 
  /* Disable MMU */
1013 
  immu_disable ();
1014 
 
1015 
  /* Set illegal instruction */
1016 
  REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
1017 
  REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xffffffff;
1018 
  REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
1019 
 
1020 
  /* Check if there was illegal insn exception */
1021 
  call (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4, 0);
1022 
  ASSERT(except_count == 1);
1023 
  ASSERT(except_mask == (1 << V_ILLINSN));
1024 
  ASSERT(except_pc == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4));
1025 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4 ));
1026 
 
1027 
  /* Reset except counter */
1028 
  except_count = 0;
1029 
  except_mask = 0;
1030 
  except_pc = 0;
1031 
  except_ea = 0;
1032 
 
1033 
  /* Enable DMMU */
1034 
  dmmu_enable ();
1035 
 
1036 
  /* Check if there was alignment exception on read insn */
1037 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
1038 
  ASSERT(except_count == 1);
1039 
  ASSERT(except_mask == (1 << V_ALIGN));
1040 
  ASSERT(ret == 0x12345678);
1041 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
1042 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
1043 
 
1044 
  /* Reset except counter */
1045 
  except_count = 0;
1046 
  except_mask = 0;
1047 
  except_pc = 0;
1048 
  except_ea = 0;
1049 
 
1050 
  /* Check if there was DTLB exception */
1051 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
1052 
  ASSERT(except_count == 1);
1053 
  ASSERT(except_mask == (1 << V_DTLB_MISS));
1054 
  ASSERT(ret == 0x12345678);
1055 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
1056 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
1057 
 
1058 
  /* Reset except counter */
1059 
  except_count = 0;
1060 
  except_mask = 0;
1061 
  except_pc = 0;
1062 
  except_ea = 0;
1063 
 
1064 
  /* Set dtlb permisions */
1065 
  dtlb_val |= SPR_DTLBTR_SRE;
1066 
 
1067 
  /* Check if there was DPF exception */
1068 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
1069 
  ASSERT(except_count == 1);
1070 
  ASSERT(except_mask == (1 << V_DPF));
1071 
  ASSERT(ret == 0x12345678);
1072 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
1073 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
1074 
 
1075 
  /* Reset except counter */
1076 
  except_count = 0;
1077 
  except_mask = 0;
1078 
  except_pc = 0;
1079 
  except_ea = 0;
1080 
 
1081 
  /* Check if there was bus error exception */
1082 
  ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
1083 
  ASSERT(except_count == 1);
1084 
  ASSERT(except_mask == (1 << V_BERR));
1085 
  ASSERT(ret == 0x12345678);
1086 
  ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
1087 
  ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
1088 
 
1089 
  /* Reset except counter */
1090 
  except_count = 0;
1091 
  except_mask = 0;
1092 
  except_pc = 0;
1093 
  except_ea = 0;
1094 
 
1095 
  /* Check if there was trap exception */
1096 
  call ((unsigned long)&trap, 0);
1097 
  ASSERT(except_count == 1);
1098 
  ASSERT(except_mask == (1 << V_TRAP));
1099 
  ASSERT(except_pc == (unsigned long)(trap));
1100 
  ASSERT(except_ea == 0);
1101 
 
1102 
  /* Reset except counter */
1103 
  except_count = 0;
1104 
  except_mask = 0;
1105 
  except_pc = 0;
1106 
  except_ea = 0;
1107 
 
1108 
  /* Check if there was range exception */
1109 
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
1110 
  call ((unsigned long)&range, 0);
1111 
  ASSERT(except_count == 1);
1112 
  ASSERT(except_mask == (1 << V_RANGE));
1113 
  ASSERT(except_pc == (unsigned long)(range));
1114 
  ASSERT(except_ea == 0);
1115 
}
1116 
 
1117 
int main (void)
1118 
{
1119 
  int ret;
1120 
 
1121 
  /* Register bus error handler */
1122 
  excpt_buserr = (unsigned long)bus_err_handler;
1123 
 
1124 
  /* Register illegal insn handler */
1125 
  excpt_illinsn = (unsigned long)ill_insn_handler;
1126 
 
1127 
  /* Register low priority interrupt handler */
1128 
  excpt_lpint = (unsigned long)lp_int_handler;
1129 
 
1130 
  /* Register high priority interrupt handler */
1131 
  excpt_hpint = (unsigned long)hp_int_handler;
1132 
 
1133 
  /* Register ITLB miss handler */
1134 
  excpt_itlbmiss = (unsigned long)itlb_miss_handler;
1135 
 
1136 
  /* Register instruction page fault handler */
1137 
  excpt_ipfault = (unsigned long)ipage_fault_handler;
1138 
 
1139 
  /* Register DTLB miss handler */
1140 
  excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
1141 
 
1142 
  /* Register data page fault handler */
1143 
  excpt_dpfault = (unsigned long)dpage_fault_handler;
1144 
 
1145 
  /* Register trap handler */
1146 
  excpt_trap = (unsigned long)trap_handler;
1147 
 
1148 
  /* Register align handler */
1149 
  excpt_align = (unsigned long)align_handler;
1150 
 
1151 
  /* Register range handler */
1152 
  excpt_range = (unsigned long)range_handler;
1153 
 
1154 
  /* Exception basic test */
1155 
  ret = except_basic ();
1156 
  ASSERT(ret == 0);
1157 
 
1158 
  /* Interrupt exception test */
1159 
  interrupt_test ();
1160 
 
1161 
  /* ITLB exception test */
1162 
  itlb_test ();
1163 
 
1164 
  /* DTLB exception test */
1165 
  dtlb_test ();
1166 
 
1167 
  /* Bus error exception test */
1168 
  buserr_test ();
1169 
 
1170 
  /* Illegal insn test */
1171 
  illegal_insn_test ();
1172 
 
1173 
  /* Alignment test */
1174 
  align_test ();
1175 
 
1176 
  /* Trap test */
1177 
  trap_test ();
1178 
 
1179 
  /* Range test */
1180 
  range_test ();
1181 
 
1182 
  /* Exception priority test */
1183 
  except_priority_test ();
1184 
 
1185 
  report (0xdeaddead);
1186 
  exit (0);
1187 
 
1188 
  return 0;
1189 
}
1190 
 

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