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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [arm/] [lib/] [io-writesb.S] - Blame information for rev 1765

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1 1275 phoenix
/*
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 *  linux/arch/arm/lib/io-writesb.S
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 *
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 *  Copyright (C) 1995-2000 Russell King
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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 */
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#include 
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#include 
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#include 
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.outsb_align:   rsb     ip, ip, #4
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                cmp     ip, r2
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                movgt   ip, r2
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                cmp     ip, #2
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                ldrb    r3, [r1], #1
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                strb    r3, [r0]
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                ldrgeb  r3, [r1], #1
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                strgeb  r3, [r0]
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                ldrgtb  r3, [r1], #1
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                strgtb  r3, [r0]
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                subs    r2, r2, ip
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                bne     .outsb_aligned
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ENTRY(__raw_writesb)
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                teq     r2, #0          @ do we have to check for the zero len?
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                moveq   pc, lr
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                ands    ip, r1, #3
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                bne     .outsb_align
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.outsb_aligned: stmfd   sp!, {r4 - r6, lr}
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                subs    r2, r2, #16
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                bmi     .outsb_no_16
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.outsb_16_lp:   ldmia   r1!, {r3 - r6}
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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                strb    r5, [r0]
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                mov     r5, r5, lsr #8
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                strb    r5, [r0]
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                mov     r5, r5, lsr #8
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                strb    r5, [r0]
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                mov     r5, r5, lsr #8
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                strb    r5, [r0]
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                strb    r6, [r0]
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                mov     r6, r6, lsr #8
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                strb    r6, [r0]
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                mov     r6, r6, lsr #8
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                strb    r6, [r0]
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                mov     r6, r6, lsr #8
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                strb    r6, [r0]
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                subs    r2, r2, #16
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                bpl     .outsb_16_lp
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                tst     r2, #15
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                LOADREGS(eqfd, sp!, {r4 - r6, pc})
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.outsb_no_16:   tst     r2, #8
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                beq     .outsb_no_8
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                ldmia   r1!, {r3, r4}
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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                mov     r4, r4, lsr #8
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                strb    r4, [r0]
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.outsb_no_8:    tst     r2, #4
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                beq     .outsb_no_4
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                ldr     r3, [r1], #4
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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                mov     r3, r3, lsr #8
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                strb    r3, [r0]
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.outsb_no_4:    ands    r2, r2, #3
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                LOADREGS(eqfd, sp!, {r4 - r6, pc})
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                cmp     r2, #2
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                ldrb    r3, [r1], #1
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                strb    r3, [r0]
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                ldrgeb  r3, [r1], #1
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                strgeb  r3, [r0]
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                ldrgtb  r3, [r1]
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                strgtb  r3, [r0]
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                LOADREGS(fd, sp!, {r4 - r6, pc})

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