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/* ppc-opc.c -- PowerPC opcode list

   Copyright 1994 Free Software Foundation, Inc.

   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute

them and/or modify them under the terms of the GNU General Public

License as published by the Free Software Foundation; either version

2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they

will be useful, but WITHOUT ANY WARRANTY; without even the implied

warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

the GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this file; see the file COPYING.  If not, write to the Free

Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <linux/posix_types.h>

#include "ansidecl.h"

#include "ppc.h"

/* This file holds the PowerPC opcode table.  The opcode table

   includes almost all of the extended instruction mnemonics.  This

   permits the disassembler to use them, and simplifies the assembler

   logic, at the cost of increasing the table size.  The table is

   strictly constant data, so the compiler should be able to put it in

   the .text section.

   This file also holds the operand table.  All knowledge about

   inserting operands into instructions and vice-versa is kept in this

   file.  */

/* Local insertion and extraction functions.  */

static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));

static long extract_bat PARAMS ((unsigned long, int *));

static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));

static long extract_bba PARAMS ((unsigned long, int *));

static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));

static long extract_bd PARAMS ((unsigned long, int *));

static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));

static long extract_bdm PARAMS ((unsigned long, int *));

static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));

static long extract_bdp PARAMS ((unsigned long, int *));

static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));

static long extract_bo PARAMS ((unsigned long, int *));

static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));

static long extract_boe PARAMS ((unsigned long, int *));

static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));

static long extract_ds PARAMS ((unsigned long, int *));

static unsigned long insert_li PARAMS ((unsigned long, long, const char **));

static long extract_li PARAMS ((unsigned long, int *));

static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));

static long extract_mbe PARAMS ((unsigned long, int *));

static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));

static long extract_mb6 PARAMS ((unsigned long, int *));

static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));

static long extract_nb PARAMS ((unsigned long, int *));

static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));

static long extract_nsi PARAMS ((unsigned long, int *));

static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));

static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));

static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));

static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));

static long extract_rbs PARAMS ((unsigned long, int *));

static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));

static long extract_sh6 PARAMS ((unsigned long, int *));

static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));

static long extract_spr PARAMS ((unsigned long, int *));

static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));

static long extract_tbr PARAMS ((unsigned long, int *));

/* The operands table.

   The fields are bits, shift, signed, insert, extract, flags.  */

const struct powerpc_operand powerpc_operands[] =

{

  /* The zero index is used to indicate the end of the list of

     operands.  */

#define UNUSED (0)

  { 0, 0, 0, 0, 0 },

  /* The BA field in an XL form instruction.  */

#define BA (1)

#define BA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_CR },

  /* The BA field in an XL form instruction when it must be the same

     as the BT field in the same instruction.  */

#define BAT (2)

  { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

  /* The BB field in an XL form instruction.  */

#define BB (3)

#define BB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_CR },

  /* The BB field in an XL form instruction when it must be the same

     as the BA field in the same instruction.  */

#define BBA (4)

  { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

  /* The BD field in a B form instruction.  The lower two bits are

     forced to zero.  */

#define BD (5)

  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when absolute addressing is

     used.  */

#define BDA (6)

  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDM (7)

  { 16, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used

     and absolute address is used.  */

#define BDMA (8)

  { 16, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDP (9)

  { 16, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used

     and absolute addressing is used.  */

#define BDPA (10)

  { 16, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BF field in an X or XL form instruction.  */

#define BF (11)

  { 3, 23, 0, 0, PPC_OPERAND_CR },

  /* An optional BF field.  This is used for comparison instructions,

     in which an omitted BF field is taken as zero.  */

#define OBF (12)

  { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The BFA field in an X or XL form instruction.  */

#define BFA (13)

  { 3, 18, 0, 0, PPC_OPERAND_CR },

  /* The BI field in a B form or XL form instruction.  */

#define BI (14)

#define BI_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_CR },

  /* The BO field in a B form instruction.  Certain values are

     illegal.  */

#define BO (15)

#define BO_MASK (0x1f << 21)

  { 5, 21, insert_bo, extract_bo, 0 },

  /* The BO field in a B form instruction when the + or - modifier is

     used.  This is like the BO field, but it must be even.  */

#define BOE (16)

  { 5, 21, insert_boe, extract_boe, 0 },

  /* The BT field in an X or XL form instruction.  */

#define BT (17)

  { 5, 21, 0, 0, PPC_OPERAND_CR },

  /* The condition register number portion of the BI field in a B form

     or XL form instruction.  This is used for the extended

     conditional branch mnemonics, which set the lower two bits of the

     BI field.  This field is optional.  */

#define CR (18)

  { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The D field in a D form instruction.  This is a displacement off

     a register, and implies that the next operand is a register in

     parentheses.  */

#define D (19)

  { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DS field in a DS form instruction.  This is like D, but the

     lower two bits are forced to zero.  */

#define DS (20)

  { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The FL1 field in a POWER SC form instruction.  */

#define FL1 (21)

  { 4, 12, 0, 0, 0 },

  /* The FL2 field in a POWER SC form instruction.  */

#define FL2 (22)

  { 3, 2, 0, 0, 0 },

  /* The FLM field in an XFL form instruction.  */

#define FLM (23)

  { 8, 17, 0, 0, 0 },

  /* The FRA field in an X or A form instruction.  */

#define FRA (24)

#define FRA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_FPR },

  /* The FRB field in an X or A form instruction.  */

#define FRB (25)

#define FRB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_FPR },

  /* The FRC field in an A form instruction.  */

#define FRC (26)

#define FRC_MASK (0x1f << 6)

  { 5, 6, 0, 0, PPC_OPERAND_FPR },

  /* The FRS field in an X form instruction or the FRT field in a D, X

     or A form instruction.  */

#define FRS (27)

#define FRT (FRS)

  { 5, 21, 0, 0, PPC_OPERAND_FPR },

  /* The FXM field in an XFX instruction.  */

#define FXM (28)

#define FXM_MASK (0xff << 12)

  { 8, 12, 0, 0, 0 },

  /* The L field in a D or X form instruction.  */

#define L (29)

  { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },

  /* The LEV field in a POWER SC form instruction.  */

#define LEV (30)

  { 7, 5, 0, 0, 0 },

  /* The LI field in an I form instruction.  The lower two bits are

     forced to zero.  */

#define LI (31)

  { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The LI field in an I form instruction when used as an absolute

     address.  */

#define LIA (32)

  { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The MB field in an M form instruction.  */

#define MB (33)

#define MB_MASK (0x1f << 6)

  { 5, 6, 0, 0, 0 },

  /* The ME field in an M form instruction.  */

#define ME (34)

#define ME_MASK (0x1f << 1)

  { 5, 1, 0, 0, 0 },

  /* The MB and ME fields in an M form instruction expressed a single

     operand which is a bitmask indicating which bits to select.  This

     is a two operand form using PPC_OPERAND_NEXT.  See the

     description in opcode/ppc.h for what this means.  */

#define MBE (35)

  { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },

  { 32, 0, insert_mbe, extract_mbe, 0 },

  /* The MB or ME field in an MD or MDS form instruction.  The high

     bit is wrapped to the low end.  */

#define MB6 (37)

#define ME6 (MB6)

#define MB6_MASK (0x3f << 5)

  { 6, 5, insert_mb6, extract_mb6, 0 },

  /* The NB field in an X form instruction.  The value 32 is stored as

     0.  */

#define NB (38)

  { 6, 11, insert_nb, extract_nb, 0 },

  /* The NSI field in a D form instruction.  This is the same as the

     SI field, only negated.  */

#define NSI (39)

  { 16, 0, insert_nsi, extract_nsi,

      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */

#define RA (40)

#define RA_MASK (0x1f << 16)

  { 5, 16, 0, 0, PPC_OPERAND_GPR },

  /* The RA field in a D or X form instruction which is an updating

     load, which means that the RA field may not be zero and may not

     equal the RT field.  */

#define RAL (41)

  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },

  /* The RA field in an lmw instruction, which has special value

     restrictions.  */

#define RAM (42)

  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },

  /* The RA field in a D or X form instruction which is an updating

     store or an updating floating point load, which means that the RA

     field may not be zero.  */

#define RAS (43)

  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },

  /* The RB field in an X, XO, M, or MDS form instruction.  */

#define RB (44)

#define RB_MASK (0x1f << 11)

  { 5, 11, 0, 0, PPC_OPERAND_GPR },

  /* The RB field in an X form instruction when it must be the same as

     the RS field in the instruction.  This is used for extended

     mnemonics like mr.  */

#define RBS (45)

  { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form

     instruction or the RT field in a D, DS, X, XFX or XO form

     instruction.  */

#define RS (46)

#define RT (RS)

#define RT_MASK (0x1f << 21)

  { 5, 21, 0, 0, PPC_OPERAND_GPR },

  /* The SH field in an X or M form instruction.  */

#define SH (47)

#define SH_MASK (0x1f << 11)

  { 5, 11, 0, 0, 0 },

  /* The SH field in an MD form instruction.  This is split.  */

#define SH6 (48)

#define SH6_MASK ((0x1f << 11) | (1 << 1))

  { 6, 1, insert_sh6, extract_sh6, 0 },

  /* The SI field in a D form instruction.  */

#define SI (49)

  { 16, 0, 0, 0, PPC_OPERAND_SIGNED },

  /* The SI field in a D form instruction when we accept a wide range

     of positive values.  */

#define SISIGNOPT (50)

  { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The SPR field in an XFX form instruction.  This is flipped--the

     lower 5 bits are stored in the upper 5 and vice- versa.  */

#define SPR (51)

#define SPR_MASK (0x3ff << 11)

  { 10, 11, insert_spr, extract_spr, 0 },

  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */

#define SPRBAT (52)

#define SPRBAT_MASK (0x3 << 17)

  { 2, 17, 0, 0, 0 },

  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */

#define SPRG (53)

#define SPRG_MASK (0x3 << 16)

  { 2, 16, 0, 0, 0 },

  /* The SR field in an X form instruction.  */

#define SR (54)

  { 4, 16, 0, 0, 0 },

  /* The SV field in a POWER SC form instruction.  */

#define SV (55)

  { 14, 2, 0, 0, 0 },

  /* The TBR field in an XFX form instruction.  This is like the SPR

     field, but it is optional.  */

#define TBR (56)

  { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },

  /* The TO field in a D or X form instruction.  */

#define TO (57)

#define TO_MASK (0x1f << 21)

  { 5, 21, 0, 0, 0 },

  /* The U field in an X form instruction.  */

#define U (58)

  { 4, 12, 0, 0, 0 },

  /* The UI field in a D form instruction.  */

#define UI (59)

  { 16, 0, 0, 0, 0 },

};

/* The functions used to insert and extract complicated operands.  */

/* The BA field in an XL form instruction when it must be the same as

   the BT field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BT field into the BA field,

   and the extraction function just checks that the fields are the

   same.  */

/*ARGSUSED*/

static unsigned long

insert_bat (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  return insn | (((insn >> 21) & 0x1f) << 16);

}

static long

extract_bat (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BB field in an XL form instruction when it must be the same as

   the BA field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BA field into the BB field,

   and the extraction function just checks that the fields are the

   same.  */

/*ARGSUSED*/

static unsigned long

insert_bba (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  return insn | (((insn >> 16) & 0x1f) << 11);

}

static long

extract_bba (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BD field in a B form instruction.  The lower two bits are

   forced to zero.  */

/*ARGSUSED*/

static unsigned long

insert_bd (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  return insn | (value & 0xfffc);

}

/*ARGSUSED*/

static long

extract_bd (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if ((insn & 0x8000) != 0)

    return (insn & 0xfffc) - 0x10000;

  else

    return insn & 0xfffc;

}

/* The BD field in a B form instruction when the - modifier is used.

   This modifier means that the branch is not expected to be taken.

   We must set the y bit of the BO field to 1 if the offset is

   negative.  When extracting, we require that the y bit be 1 and that

   the offset be positive, since if the y bit is 0 we just want to

   print the normal form of the instruction.  */

/*ARGSUSED*/

static unsigned long

insert_bdm (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  if ((value & 0x8000) != 0)

    insn |= 1 << 21;

  return insn | (value & 0xfffc);

}

static long

extract_bdm (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn & (1 << 21)) == 0

          || (insn & (1 << 15)) == 0))

    *invalid = 1;

  if ((insn & 0x8000) != 0)

    return (insn & 0xfffc) - 0x10000;

  else

    return insn & 0xfffc;

}

/* The BD field in a B form instruction when the + modifier is used.

   This is like BDM, above, except that the branch is expected to be

   taken.  */

/*ARGSUSED*/

static unsigned long

insert_bdp (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  if ((value & 0x8000) == 0)

    insn |= 1 << 21;

  return insn | (value & 0xfffc);

}

static long

extract_bdp (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if (invalid != (int *) NULL

      && ((insn & (1 << 21)) == 0

          || (insn & (1 << 15)) != 0))

    *invalid = 1;

  if ((insn & 0x8000) != 0)

    return (insn & 0xfffc) - 0x10000;

  else

    return insn & 0xfffc;

}

/* Check for legal values of a BO field.  */

static int

valid_bo (long value)

{

  /* Certain encodings have bits that are required to be zero.  These

     are (z must be zero, y may be anything):

         001zy

         011zy

         1z00y

         1z01y

         1z1zz

     */

  switch (value & 0x14)

    {

    default:

    case 0:

      return 1;

    case 0x4:

      return (value & 0x2) == 0;

    case 0x10:

      return (value & 0x8) == 0;

    case 0x14:

      return value == 0x14;

    }

}

/* The BO field in a B form instruction.  Warn about attempts to set

   the field to an illegal value.  */

static unsigned long

insert_bo (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  if (errmsg != (const char **) NULL

      && ! valid_bo (value))

    *errmsg = "invalid conditional option";

  return insn | ((value & 0x1f) << 21);

}

static long

extract_bo (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  long value;

  value = (insn >> 21) & 0x1f;

  if (invalid != (int *) NULL

      && ! valid_bo (value))

    *invalid = 1;

  return value;

}

/* The BO field in a B form instruction when the + or - modifier is

   used.  This is like the BO field, but it must be even.  When

   extracting it, we force it to be even.  */

static unsigned long

insert_boe (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  if (errmsg != (const char **) NULL)

    {

      if (! valid_bo (value))

        *errmsg = "invalid conditional option";

      else if ((value & 1) != 0)

        *errmsg = "attempt to set y bit when using + or - modifier";

    }

  return insn | ((value & 0x1f) << 21);

}

static long

extract_boe (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  long value;

  value = (insn >> 21) & 0x1f;

  if (invalid != (int *) NULL

      && ! valid_bo (value))

    *invalid = 1;

  return value & 0x1e;

}

/* The DS field in a DS form instruction.  This is like D, but the

   lower two bits are forced to zero.  */

/*ARGSUSED*/

static unsigned long

insert_ds (insn, value, errmsg)

     unsigned long insn;

     long value;

     const char **errmsg;

{

  return insn | (value & 0xfffc);

}

/*ARGSUSED*/

static long

extract_ds (insn, invalid)

     unsigned long insn;

     int *invalid;

{

  if ((insn & 0x8000) != 0)