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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [ariadne.h] - Blame information for rev 1626

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Line No. Rev Author Line
1 1626 jcastillo
/*
2
 *  Amiga Linux/m68k Ariadne Ethernet Driver
3
 *
4
 *  © Copyright 1995 by Geert Uytterhoeven
5
 *                     (Geert.Uytterhoeven@cs.kuleuven.ac.be)
6
 *                      Peter De Schrijver
7
 *                     (Peter.DeSchrijver@linux.cc.kuleuven.ac.be)
8
 *
9
 *  ----------------------------------------------------------------------------------
10
 *
11
 *  This program is based on
12
 *
13
 *      lance.c:        An AMD LANCE ethernet driver for linux.
14
 *                      Written 1993-94 by Donald Becker.
15
 *
16
 *      Am79C960:       PCnet(tm)-ISA Single-Chip Ethernet Controller
17
 *                      Advanced Micro Devices
18
 *                      Publication #16907, Rev. B, Amendment/0, May 1994
19
 *
20
 *      MC68230:        Parallel Interface/Timer (PI/T)
21
 *                      Motorola Semiconductors, December, 1983
22
 *
23
 *  ----------------------------------------------------------------------------------
24
 *
25
 *  This file is subject to the terms and conditions of the GNU General Public
26
 *  License.  See the file COPYING in the main directory of the Linux
27
 *  distribution for more details.
28
 *
29
 *  ----------------------------------------------------------------------------------
30
 *
31
 *  The Ariadne is a Zorro-II board made by Village Tronic. It contains:
32
 *
33
 *      - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
34
 *        10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
35
 *
36
 *      - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
37
 */
38
 
39
 
40
    /*
41
     *  Am79C960 PCnet-ISA
42
     */
43
 
44
struct Am79C960 {
45
    volatile u_short AddressPROM[8];
46
                                /* IEEE Address PROM (Unused in the Ariadne) */
47
    volatile u_short RDP;       /* Register Data Port */
48
    volatile u_short RAP;       /* Register Address Port */
49
    volatile u_short Reset;     /* Reset Chip on Read Access */
50
    volatile u_short IDP;       /* ISACSR Data Port */
51
};
52
 
53
 
54
    /*
55
     *  Am79C960 Control and Status Registers
56
     *
57
     *  These values are already swap()ed!!
58
     *
59
     *  Only registers marked with a `-' are intended for network software
60
     *  access
61
     */
62
 
63
#define CSR0            0x0000  /* - PCnet-ISA Controller Status */
64
#define CSR1            0x0100  /* - IADR[15:0] */
65
#define CSR2            0x0200  /* - IADR[23:16] */
66
#define CSR3            0x0300  /* - Interrupt Masks and Deferral Control */
67
#define CSR4            0x0400  /* - Test and Features Control */
68
#define CSR6            0x0600  /*   RCV/XMT Descriptor Table Length */
69
#define CSR8            0x0800  /* - Logical Address Filter, LADRF[15:0] */
70
#define CSR9            0x0900  /* - Logical Address Filter, LADRF[31:16] */
71
#define CSR10           0x0a00  /* - Logical Address Filter, LADRF[47:32] */
72
#define CSR11           0x0b00  /* - Logical Address Filter, LADRF[63:48] */
73
#define CSR12           0x0c00  /* - Physical Address Register, PADR[15:0] */
74
#define CSR13           0x0d00  /* - Physical Address Register, PADR[31:16] */
75
#define CSR14           0x0e00  /* - Physical Address Register, PADR[47:32] */
76
#define CSR15           0x0f00  /* - Mode Register */
77
#define CSR16           0x1000  /*   Initialization Block Address Lower */
78
#define CSR17           0x1100  /*   Initialization Block Address Upper */
79
#define CSR18           0x1200  /*   Current Receive Buffer Address */
80
#define CSR19           0x1300  /*   Current Receive Buffer Address */
81
#define CSR20           0x1400  /*   Current Transmit Buffer Address */
82
#define CSR21           0x1500  /*   Current Transmit Buffer Address */
83
#define CSR22           0x1600  /*   Next Receive Buffer Address */
84
#define CSR23           0x1700  /*   Next Receive Buffer Address */
85
#define CSR24           0x1800  /* - Base Address of Receive Ring */
86
#define CSR25           0x1900  /* - Base Address of Receive Ring */
87
#define CSR26           0x1a00  /*   Next Receive Descriptor Address */
88
#define CSR27           0x1b00  /*   Next Receive Descriptor Address */
89
#define CSR28           0x1c00  /*   Current Receive Descriptor Address */
90
#define CSR29           0x1d00  /*   Current Receive Descriptor Address */
91
#define CSR30           0x1e00  /* - Base Address of Transmit Ring */
92
#define CSR31           0x1f00  /* - Base Address of transmit Ring */
93
#define CSR32           0x2000  /*   Next Transmit Descriptor Address */
94
#define CSR33           0x2100  /*   Next Transmit Descriptor Address */
95
#define CSR34           0x2200  /*   Current Transmit Descriptor Address */
96
#define CSR35           0x2300  /*   Current Transmit Descriptor Address */
97
#define CSR36           0x2400  /*   Next Next Receive Descriptor Address */
98
#define CSR37           0x2500  /*   Next Next Receive Descriptor Address */
99
#define CSR38           0x2600  /*   Next Next Transmit Descriptor Address */
100
#define CSR39           0x2700  /*   Next Next Transmit Descriptor Address */
101
#define CSR40           0x2800  /*   Current Receive Status and Byte Count */
102
#define CSR41           0x2900  /*   Current Receive Status and Byte Count */
103
#define CSR42           0x2a00  /*   Current Transmit Status and Byte Count */
104
#define CSR43           0x2b00  /*   Current Transmit Status and Byte Count */
105
#define CSR44           0x2c00  /*   Next Receive Status and Byte Count */
106
#define CSR45           0x2d00  /*   Next Receive Status and Byte Count */
107
#define CSR46           0x2e00  /*   Poll Time Counter */
108
#define CSR47           0x2f00  /*   Polling Interval */
109
#define CSR48           0x3000  /*   Temporary Storage */
110
#define CSR49           0x3100  /*   Temporary Storage */
111
#define CSR50           0x3200  /*   Temporary Storage */
112
#define CSR51           0x3300  /*   Temporary Storage */
113
#define CSR52           0x3400  /*   Temporary Storage */
114
#define CSR53           0x3500  /*   Temporary Storage */
115
#define CSR54           0x3600  /*   Temporary Storage */
116
#define CSR55           0x3700  /*   Temporary Storage */
117
#define CSR56           0x3800  /*   Temporary Storage */
118
#define CSR57           0x3900  /*   Temporary Storage */
119
#define CSR58           0x3a00  /*   Temporary Storage */
120
#define CSR59           0x3b00  /*   Temporary Storage */
121
#define CSR60           0x3c00  /*   Previous Transmit Descriptor Address */
122
#define CSR61           0x3d00  /*   Previous Transmit Descriptor Address */
123
#define CSR62           0x3e00  /*   Previous Transmit Status and Byte Count */
124
#define CSR63           0x3f00  /*   Previous Transmit Status and Byte Count */
125
#define CSR64           0x4000  /*   Next Transmit Buffer Address */
126
#define CSR65           0x4100  /*   Next Transmit Buffer Address */
127
#define CSR66           0x4200  /*   Next Transmit Status and Byte Count */
128
#define CSR67           0x4300  /*   Next Transmit Status and Byte Count */
129
#define CSR68           0x4400  /*   Transmit Status Temporary Storage */
130
#define CSR69           0x4500  /*   Transmit Status Temporary Storage */
131
#define CSR70           0x4600  /*   Temporary Storage */
132
#define CSR71           0x4700  /*   Temporary Storage */
133
#define CSR72           0x4800  /*   Receive Ring Counter */
134
#define CSR74           0x4a00  /*   Transmit Ring Counter */
135
#define CSR76           0x4c00  /* - Receive Ring Length */
136
#define CSR78           0x4e00  /* - Transmit Ring Length */
137
#define CSR80           0x5000  /* - Burst and FIFO Threshold Control */
138
#define CSR82           0x5200  /* - Bus Activity Timer */
139
#define CSR84           0x5400  /*   DMA Address */
140
#define CSR85           0x5500  /*   DMA Address */
141
#define CSR86           0x5600  /*   Buffer Byte Counter */
142
#define CSR88           0x5800  /* - Chip ID */
143
#define CSR89           0x5900  /* - Chip ID */
144
#define CSR92           0x5c00  /*   Ring Length Conversion */
145
#define CSR94           0x5e00  /*   Transmit Time Domain Reflectometry Count */
146
#define CSR96           0x6000  /*   Bus Interface Scratch Register 0 */
147
#define CSR97           0x6100  /*   Bus Interface Scratch Register 0 */
148
#define CSR98           0x6200  /*   Bus Interface Scratch Register 1 */
149
#define CSR99           0x6300  /*   Bus Interface Scratch Register 1 */
150
#define CSR104          0x6800  /*   SWAP */
151
#define CSR105          0x6900  /*   SWAP */
152
#define CSR108          0x6c00  /*   Buffer Management Scratch */
153
#define CSR109          0x6d00  /*   Buffer Management Scratch */
154
#define CSR112          0x7000  /* - Missed Frame Count */
155
#define CSR114          0x7200  /* - Receive Collision Count */
156
#define CSR124          0x7c00  /* - Buffer Management Unit Test */
157
 
158
 
159
    /*
160
     *  Am79C960 ISA Control and Status Registers
161
     *
162
     *  These values are already swap()ed!!
163
     */
164
 
165
#define ISACSR0         0x0000  /* Master Mode Read Active */
166
#define ISACSR1         0x0100  /* Master Mode Write Active */
167
#define ISACSR2         0x0200  /* Miscellaneous Configuration */
168
#define ISACSR4         0x0400  /* LED0 Status (Link Integrity) */
169
#define ISACSR5         0x0500  /* LED1 Status */
170
#define ISACSR6         0x0600  /* LED2 Status */
171
#define ISACSR7         0x0700  /* LED3 Status */
172
 
173
 
174
    /*
175
     *  Bit definitions for CSR0 (PCnet-ISA Controller Status)
176
     *
177
     *  These values are already swap()ed!!
178
     */
179
 
180
#define ERR             0x0080  /* Error */
181
#define BABL            0x0040  /* Babble: Transmitted too many bits */
182
#define CERR            0x0020  /* No Heartbeat (10BASE-T) */
183
#define MISS            0x0010  /* Missed Frame */
184
#define MERR            0x0008  /* Memory Error */
185
#define RINT            0x0004  /* Receive Interrupt */
186
#define TINT            0x0002  /* Transmit Interrupt */
187
#define IDON            0x0001  /* Initialization Done */
188
#define INTR            0x8000  /* Interrupt Flag */
189
#define INEA            0x4000  /* Interrupt Enable */
190
#define RXON            0x2000  /* Receive On */
191
#define TXON            0x1000  /* Transmit On */
192
#define TDMD            0x0800  /* Transmit Demand */
193
#define STOP            0x0400  /* Stop */
194
#define STRT            0x0200  /* Start */
195
#define INIT            0x0100  /* Initialize */
196
 
197
 
198
    /*
199
     *  Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
200
     *
201
     *  These values are already swap()ed!!
202
     */
203
 
204
#define BABLM           0x0040  /* Babble Mask */
205
#define MISSM           0x0010  /* Missed Frame Mask */
206
#define MERRM           0x0008  /* Memory Error Mask */
207
#define RINTM           0x0004  /* Receive Interrupt Mask */
208
#define TINTM           0x0002  /* Transmit Interrupt Mask */
209
#define IDONM           0x0001  /* Initialization Done Mask */
210
#define DXMT2PD         0x1000  /* Disable Transmit Two Part Deferral */
211
#define EMBA            0x0800  /* Enable Modified Back-off Algorithm */
212
 
213
 
214
    /*
215
     *  Bit definitions for CSR4 (Test and Features Control)
216
     *
217
     *  These values are already swap()ed!!
218
     */
219
 
220
#define ENTST           0x0080  /* Enable Test Mode */
221
#define DMAPLUS         0x0040  /* Disable Burst Transaction Counter */
222
#define TIMER           0x0020  /* Timer Enable Register */
223
#define DPOLL           0x0010  /* Disable Transmit Polling */
224
#define APAD_XMT        0x0008  /* Auto Pad Transmit */
225
#define ASTRP_RCV       0x0004  /* Auto Pad Stripping */
226
#define MFCO            0x0002  /* Missed Frame Counter Overflow Interrupt */
227
#define MFCOM           0x0001  /* Missed Frame Counter Overflow Mask */
228
#define RCVCCO          0x2000  /* Receive Collision Counter Overflow Interrupt */
229
#define RCVCCOM         0x1000  /* Receive Collision Counter Overflow Mask */
230
#define TXSTRT          0x0800  /* Transmit Start Status */
231
#define TXSTRTM         0x0400  /* Transmit Start Mask */
232
#define JAB             0x0200  /* Jabber Error */
233
#define JABM            0x0100  /* Jabber Error Mask */
234
 
235
 
236
    /*
237
     *  Bit definitions for CSR15 (Mode Register)
238
     *
239
     *  These values are already swap()ed!!
240
     */
241
 
242
#define PROM            0x0080  /* Promiscuous Mode */
243
#define DRCVBC          0x0040  /* Disable Receive Broadcast */
244
#define DRCVPA          0x0020  /* Disable Receive Physical Address */
245
#define DLNKTST         0x0010  /* Disable Link Status */
246
#define DAPC            0x0008  /* Disable Automatic Polarity Correction */
247
#define MENDECL         0x0004  /* MENDEC Loopback Mode */
248
#define LRTTSEL         0x0002  /* Low Receive Treshold/Transmit Mode Select */
249
#define PORTSEL1        0x0001  /* Port Select Bits */
250
#define PORTSEL2        0x8000  /* Port Select Bits */
251
#define INTL            0x4000  /* Internal Loopback */
252
#define DRTY            0x2000  /* Disable Retry */
253
#define FCOLL           0x1000  /* Force Collision */
254
#define DXMTFCS         0x0800  /* Disable Transmit CRC */
255
#define LOOP            0x0400  /* Loopback Enable */
256
#define DTX             0x0200  /* Disable Transmitter */
257
#define DRX             0x0100  /* Disable Receiver */
258
 
259
 
260
    /*
261
     *  Bit definitions for ISACSR2 (Miscellaneous Configuration)
262
     *
263
     *  These values are already swap()ed!!
264
     */
265
 
266
#define ASEL            0x0200  /* Media Interface Port Auto Select */
267
 
268
 
269
    /*
270
     *  Bit definitions for ISACSR5-7 (LED1-3 Status)
271
     *
272
     *  These values are already swap()ed!!
273
     */
274
 
275
#define LEDOUT          0x0080  /* Current LED Status */
276
#define PSE             0x8000  /* Pulse Stretcher Enable */
277
#define XMTE            0x1000  /* Enable Transmit Status Signal */
278
#define RVPOLE          0x0800  /* Enable Receive Polarity Signal */
279
#define RCVE            0x0400  /* Enable Receive Status Signal */
280
#define JABE            0x0200  /* Enable Jabber Signal */
281
#define COLE            0x0100  /* Enable Collision Signal */
282
 
283
 
284
    /*
285
     *  Receive Descriptor Ring Entry
286
     */
287
 
288
struct RDRE {
289
    volatile u_short RMD0;      /* LADR[15:0] */
290
    volatile u_short RMD1;      /* HADR[23:16] | Receive Flags */
291
    volatile u_short RMD2;      /* Buffer Byte Count (two's complement) */
292
    volatile u_short RMD3;      /* Message Byte Count */
293
};
294
 
295
 
296
    /*
297
     *  Transmit Descriptor Ring Entry
298
     */
299
 
300
struct TDRE {
301
    volatile u_short TMD0;      /* LADR[15:0] */
302
    volatile u_short TMD1;      /* HADR[23:16] | Transmit Flags */
303
    volatile u_short TMD2;      /* Buffer Byte Count (two's complement) */
304
    volatile u_short TMD3;      /* Error Flags */
305
};
306
 
307
 
308
    /*
309
     *  Receive Flags
310
     */
311
 
312
#define RF_OWN          0x0080  /* PCnet-ISA controller owns the descriptor */
313
#define RF_ERR          0x0040  /* Error */
314
#define RF_FRAM         0x0020  /* Framing Error */
315
#define RF_OFLO         0x0010  /* Overflow Error */
316
#define RF_CRC          0x0008  /* CRC Error */
317
#define RF_BUFF         0x0004  /* Buffer Error */
318
#define RF_STP          0x0002  /* Start of Packet */
319
#define RF_ENP          0x0001  /* End of Packet */
320
 
321
 
322
    /*
323
     *  Transmit Flags
324
     */
325
 
326
#define TF_OWN          0x0080  /* PCnet-ISA controller owns the descriptor */
327
#define TF_ERR          0x0040  /* Error */
328
#define TF_ADD_FCS      0x0020  /* Controls FCS Generation */
329
#define TF_MORE         0x0010  /* More than one retry needed */
330
#define TF_ONE          0x0008  /* One retry needed */
331
#define TF_DEF          0x0004  /* Deferred */
332
#define TF_STP          0x0002  /* Start of Packet */
333
#define TF_ENP          0x0001  /* End of Packet */
334
 
335
 
336
    /*
337
     *  Error Flags
338
     */
339
 
340
#define EF_BUFF         0x0080  /* Buffer Error */
341
#define EF_UFLO         0x0040  /* Underflow Error */
342
#define EF_LCOL         0x0010  /* Late Collision */
343
#define EF_LCAR         0x0008  /* Loss of Carrier */
344
#define EF_RTRY         0x0004  /* Retry Error */
345
#define EF_TDR          0xff03  /* Time Domain Reflectometry */
346
 
347
 
348
 
349
    /*
350
     *  MC68230 Parallel Interface/Timer
351
     */
352
 
353
struct MC68230 {
354
    volatile u_char PGCR;       /* Port General Control Register */
355
    u_char Pad1[1];
356
    volatile u_char PSRR;       /* Port Service Request Register */
357
    u_char Pad2[1];
358
    volatile u_char PADDR;      /* Port A Data Direction Register */
359
    u_char Pad3[1];
360
    volatile u_char PBDDR;      /* Port B Data Direction Register */
361
    u_char Pad4[1];
362
    volatile u_char PCDDR;      /* Port C Data Direction Register */
363
    u_char Pad5[1];
364
    volatile u_char PIVR;       /* Port Interrupt Vector Register */
365
    u_char Pad6[1];
366
    volatile u_char PACR;       /* Port A Control Register */
367
    u_char Pad7[1];
368
    volatile u_char PBCR;       /* Port B Control Register */
369
    u_char Pad8[1];
370
    volatile u_char PADR;       /* Port A Data Register */
371
    u_char Pad9[1];
372
    volatile u_char PBDR;       /* Port B Data Register */
373
    u_char Pad10[1];
374
    volatile u_char PAAR;       /* Port A Alternate Register */
375
    u_char Pad11[1];
376
    volatile u_char PBAR;       /* Port B Alternate Register */
377
    u_char Pad12[1];
378
    volatile u_char PCDR;       /* Port C Data Register */
379
    u_char Pad13[1];
380
    volatile u_char PSR;        /* Port Status Register */
381
    u_char Pad14[5];
382
    volatile u_char TCR;        /* Timer Control Register */
383
    u_char Pad15[1];
384
    volatile u_char TIVR;       /* Timer Interrupt Vector Register */
385
    u_char Pad16[3];
386
    volatile u_char CPRH;       /* Counter Preload Register (High) */
387
    u_char Pad17[1];
388
    volatile u_char CPRM;       /* Counter Preload Register (Mid) */
389
    u_char Pad18[1];
390
    volatile u_char CPRL;       /* Counter Preload Register (Low) */
391
    u_char Pad19[3];
392
    volatile u_char CNTRH;      /* Count Register (High) */
393
    u_char Pad20[1];
394
    volatile u_char CNTRM;      /* Count Register (Mid) */
395
    u_char Pad21[1];
396
    volatile u_char CNTRL;      /* Count Register (Low) */
397
    u_char Pad22[1];
398
    volatile u_char TSR;        /* Timer Status Register */
399
    u_char Pad23[11];
400
};
401
 
402
 
403
    /*
404
     *  Ariadne Expansion Board Structure
405
     */
406
 
407
struct AriadneBoard {
408
    u_char Pad1[0x360];
409
    struct Am79C960 Lance;
410
    u_char Pad2[0xc88];
411
    struct MC68230 PiT;
412
    u_char Pad3[0x2fc0];
413
    volatile u_short BootPROM[0x2000];  /* I guess it's here :-) */
414
    volatile u_short RAM[0x4000];       /* Always access WORDs!! */
415
};

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