| 1 |
158 |
chris |
/* m68k.h
|
| 2 |
|
|
*
|
| 3 |
|
|
* This include file contains information pertaining to the Motorola
|
| 4 |
|
|
* m68xxx processor family.
|
| 5 |
|
|
*
|
| 6 |
|
|
* COPYRIGHT (c) 1989-1999.
|
| 7 |
|
|
* On-Line Applications Research Corporation (OAR).
|
| 8 |
|
|
*
|
| 9 |
|
|
* The license and distribution terms for this file may be
|
| 10 |
|
|
* found in the file LICENSE in this distribution or at
|
| 11 |
|
|
* http://www.OARcorp.com/rtems/license.html.
|
| 12 |
|
|
*
|
| 13 |
208 |
chris |
* $Id: m68k.h,v 1.2 2001-09-27 11:59:28 chris Exp $
|
| 14 |
158 |
chris |
*/
|
| 15 |
|
|
|
| 16 |
|
|
#ifndef __M68k_h
|
| 17 |
|
|
#define __M68k_h
|
| 18 |
|
|
|
| 19 |
|
|
#ifdef __cplusplus
|
| 20 |
|
|
extern "C" {
|
| 21 |
|
|
#endif
|
| 22 |
|
|
|
| 23 |
|
|
/*
|
| 24 |
|
|
* This section contains the information required to build
|
| 25 |
|
|
* RTEMS for a particular member of the Motorola MC68xxx
|
| 26 |
|
|
* family. It does this by setting variables to indicate
|
| 27 |
|
|
* which implementation dependent features are present in
|
| 28 |
|
|
* a particular member of the family.
|
| 29 |
|
|
*
|
| 30 |
|
|
* Currently recognized:
|
| 31 |
|
|
* -m68000
|
| 32 |
|
|
* -m68000 -msoft-float
|
| 33 |
|
|
* -m68020
|
| 34 |
|
|
* -m68020 -msoft-float
|
| 35 |
|
|
* -m68030
|
| 36 |
|
|
* -m68040 -msoft-float
|
| 37 |
|
|
* -m68040
|
| 38 |
|
|
* -m68040 -msoft-float
|
| 39 |
|
|
* -m68060
|
| 40 |
|
|
* -m68060 -msoft-float
|
| 41 |
|
|
* -m68302 (no FP) (deprecated, use -m68000)
|
| 42 |
|
|
* -m68332 (no FP) (deprecated, use -mcpu32)
|
| 43 |
|
|
* -mcpu32 (no FP)
|
| 44 |
|
|
* -m5200 (no FP)
|
| 45 |
|
|
*
|
| 46 |
|
|
* As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
|
| 47 |
|
|
* the CPU32 and CPU32+. The option -mcpu32 generates code which can
|
| 48 |
|
|
* be run on either core. RTEMS distinguishes between these two cores
|
| 49 |
|
|
* because they have different alignment rules which impact performance.
|
| 50 |
|
|
* If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
|
| 51 |
|
|
* be defined in your custom file (see make/custom/gen68360.cfg for an
|
| 52 |
|
|
* example of how to do this. If gcc ever distinguishes between these
|
| 53 |
|
|
* two cores, then RTEMS__mcpu32p__ usage will be replaced with the
|
| 54 |
|
|
* appropriate compiler defined predefine.
|
| 55 |
|
|
*
|
| 56 |
|
|
* Here is some information on the 040 variants (courtesy of Doug McBride,
|
| 57 |
|
|
* mcbride@rodin.colorado.edu):
|
| 58 |
|
|
*
|
| 59 |
|
|
* "The 68040 is a superset of the 68EC040 and the 68LC040. The
|
| 60 |
|
|
* 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the
|
| 61 |
|
|
* 68EC040 have renamed the DLE pin as JS0 which must be tied to
|
| 62 |
|
|
* Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The
|
| 63 |
|
|
* 68EC040 has access control units instead of memory management units.
|
| 64 |
|
|
* The 68EC040 should not have the PFLUSH or PTEST instructions executed
|
| 65 |
|
|
* (cause an indeterminate result). The 68EC040 and 68LC040 do not
|
| 66 |
|
|
* implement the DLE or multiplexed bus modes. The 68EC040 does not
|
| 67 |
|
|
* implement the output buffer impedance selection mode of operation."
|
| 68 |
|
|
*
|
| 69 |
|
|
* M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
|
| 70 |
|
|
* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
|
| 71 |
|
|
* 68010, 68302, 68306, 68307). This instruction is available on the 68020
|
| 72 |
|
|
* up and the cpu32 based models.
|
| 73 |
|
|
*
|
| 74 |
|
|
* M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
|
| 75 |
|
|
* data access (68020, 68030, 68040, 68060, CPU32+).
|
| 76 |
|
|
*
|
| 77 |
|
|
* NOTE:
|
| 78 |
|
|
* Eventually it would be nice to evaluate doing a lot of this section
|
| 79 |
|
|
* by having each model specify which core it uses and then go from there.
|
| 80 |
|
|
*/
|
| 81 |
|
|
|
| 82 |
|
|
/*
|
| 83 |
|
|
* Figure out all CPU Model Feature Flags based upon compiler
|
| 84 |
|
|
* predefines. Notice the only exception to this is that
|
| 85 |
|
|
* gcc does not distinguish between CPU32 and CPU32+. This
|
| 86 |
|
|
* feature selection logic is setup such that if RTEMS__mcpu32p__
|
| 87 |
|
|
* is defined, then CPU32+ rules are used. Otherwise, the safe
|
| 88 |
|
|
* but less efficient CPU32 rules are used for the CPU32+.
|
| 89 |
|
|
*/
|
| 90 |
|
|
|
| 91 |
|
|
#if defined(__mc68020__)
|
| 92 |
|
|
|
| 93 |
|
|
#define CPU_MODEL_NAME "m68020"
|
| 94 |
|
|
#define M68K_HAS_VBR 1
|
| 95 |
|
|
#define M68K_HAS_SEPARATE_STACKS 1
|
| 96 |
|
|
#define M68K_HAS_BFFFO 1
|
| 97 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 98 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 99 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 100 |
|
|
# if defined (__HAVE_68881__)
|
| 101 |
|
|
# define M68K_HAS_FPU 1
|
| 102 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 103 |
|
|
# else
|
| 104 |
|
|
# define M68K_HAS_FPU 0
|
| 105 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 106 |
|
|
# endif
|
| 107 |
|
|
|
| 108 |
|
|
#elif defined(__mc68030__)
|
| 109 |
|
|
|
| 110 |
|
|
#define CPU_MODEL_NAME "m68030"
|
| 111 |
|
|
#define M68K_HAS_VBR 1
|
| 112 |
|
|
#define M68K_HAS_SEPARATE_STACKS 1
|
| 113 |
|
|
#define M68K_HAS_BFFFO 1
|
| 114 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 115 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 116 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 117 |
|
|
# if defined (__HAVE_68881__)
|
| 118 |
|
|
# define M68K_HAS_FPU 1
|
| 119 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 120 |
|
|
# else
|
| 121 |
|
|
# define M68K_HAS_FPU 0
|
| 122 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 123 |
|
|
# endif
|
| 124 |
|
|
|
| 125 |
|
|
#elif defined(__mc68040__)
|
| 126 |
|
|
|
| 127 |
|
|
#define CPU_MODEL_NAME "m68040"
|
| 128 |
|
|
#define M68K_HAS_VBR 1
|
| 129 |
|
|
#define M68K_HAS_SEPARATE_STACKS 1
|
| 130 |
|
|
#define M68K_HAS_BFFFO 1
|
| 131 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 132 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 133 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 134 |
|
|
# if defined (__HAVE_68881__)
|
| 135 |
|
|
# define M68K_HAS_FPU 1
|
| 136 |
|
|
# define M68K_HAS_FPSP_PACKAGE 1
|
| 137 |
|
|
# else
|
| 138 |
|
|
# define M68K_HAS_FPU 0
|
| 139 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 140 |
|
|
# endif
|
| 141 |
|
|
|
| 142 |
|
|
#elif defined(__mc68060__)
|
| 143 |
|
|
|
| 144 |
|
|
#define CPU_MODEL_NAME "m68060"
|
| 145 |
|
|
#define M68K_HAS_VBR 1
|
| 146 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 147 |
|
|
#define M68K_HAS_BFFFO 1
|
| 148 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 149 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 150 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 151 |
|
|
# if defined (__HAVE_68881__)
|
| 152 |
|
|
# define M68K_HAS_FPU 1
|
| 153 |
|
|
# define M68K_HAS_FPSP_PACKAGE 1
|
| 154 |
|
|
# else
|
| 155 |
|
|
# define M68K_HAS_FPU 0
|
| 156 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 157 |
|
|
# endif
|
| 158 |
|
|
|
| 159 |
|
|
#elif defined(__mc68302__)
|
| 160 |
|
|
#define CPU_MODEL_NAME "m68302"
|
| 161 |
|
|
#define M68K_HAS_VBR 0
|
| 162 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 163 |
|
|
#define M68K_HAS_BFFFO 0
|
| 164 |
|
|
#define M68K_HAS_PREINDEXING 0
|
| 165 |
|
|
#define M68K_HAS_EXTB_L 0
|
| 166 |
|
|
#define M68K_HAS_MISALIGNED 0
|
| 167 |
|
|
#define M68K_HAS_FPU 0
|
| 168 |
|
|
#define M68K_HAS_FPSP_PACKAGE 0
|
| 169 |
|
|
|
| 170 |
|
|
/* gcc and egcs do not distinguish between CPU32 and CPU32+ */
|
| 171 |
|
|
#elif defined(RTEMS__mcpu32p__)
|
| 172 |
|
|
|
| 173 |
|
|
#define CPU_MODEL_NAME "mcpu32+"
|
| 174 |
|
|
#define M68K_HAS_VBR 1
|
| 175 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 176 |
|
|
#define M68K_HAS_BFFFO 0
|
| 177 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 178 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 179 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 180 |
|
|
#define M68K_HAS_FPU 0
|
| 181 |
|
|
#define M68K_HAS_FPSP_PACKAGE 0
|
| 182 |
|
|
|
| 183 |
|
|
#elif defined(__mcpu32__)
|
| 184 |
|
|
|
| 185 |
|
|
#define CPU_MODEL_NAME "mcpu32"
|
| 186 |
|
|
#define M68K_HAS_VBR 1
|
| 187 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 188 |
|
|
#define M68K_HAS_BFFFO 0
|
| 189 |
|
|
#define M68K_HAS_PREINDEXING 1
|
| 190 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 191 |
|
|
#define M68K_HAS_MISALIGNED 0
|
| 192 |
|
|
#define M68K_HAS_FPU 0
|
| 193 |
|
|
#define M68K_HAS_FPSP_PACKAGE 0
|
| 194 |
|
|
|
| 195 |
|
|
#elif defined(__mcf5200__)
|
| 196 |
|
|
/* Motorola ColdFire V2 core - RISC/68020 hybrid */
|
| 197 |
|
|
#define CPU_MODEL_NAME "m5200"
|
| 198 |
|
|
#define M68K_HAS_VBR 1
|
| 199 |
|
|
#define M68K_HAS_BFFFO 0
|
| 200 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 201 |
|
|
#define M68K_HAS_PREINDEXING 0
|
| 202 |
|
|
#define M68K_HAS_EXTB_L 1
|
| 203 |
|
|
#define M68K_HAS_MISALIGNED 1
|
| 204 |
|
|
#define M68K_HAS_FPU 0
|
| 205 |
|
|
#define M68K_HAS_FPSP_PACKAGE 0
|
| 206 |
|
|
#define M68K_COLDFIRE_ARCH 1
|
| 207 |
|
|
|
| 208 |
|
|
#elif defined(__mc68000__)
|
| 209 |
|
|
|
| 210 |
|
|
#define CPU_MODEL_NAME "m68000"
|
| 211 |
|
|
#define M68K_HAS_VBR 0
|
| 212 |
|
|
#define M68K_HAS_SEPARATE_STACKS 0
|
| 213 |
|
|
#define M68K_HAS_BFFFO 0
|
| 214 |
|
|
#define M68K_HAS_PREINDEXING 0
|
| 215 |
|
|
#define M68K_HAS_EXTB_L 0
|
| 216 |
|
|
#define M68K_HAS_MISALIGNED 0
|
| 217 |
|
|
# if defined (__HAVE_68881__)
|
| 218 |
|
|
# define M68K_HAS_FPU 1
|
| 219 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 220 |
|
|
# else
|
| 221 |
|
|
# define M68K_HAS_FPU 0
|
| 222 |
|
|
# define M68K_HAS_FPSP_PACKAGE 0
|
| 223 |
|
|
# endif
|
| 224 |
|
|
|
| 225 |
|
|
#else
|
| 226 |
|
|
|
| 227 |
|
|
#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
|
| 228 |
|
|
|
| 229 |
|
|
#endif
|
| 230 |
|
|
|
| 231 |
|
|
/*
|
| 232 |
|
|
* If the above did not specify a ColdFire architecture, then set
|
| 233 |
|
|
* this flag to indicate that it is not a ColdFire CPU.
|
| 234 |
|
|
*/
|
| 235 |
|
|
|
| 236 |
|
|
#if !defined(M68K_COLDFIRE_ARCH)
|
| 237 |
|
|
#define M68K_COLDFIRE_ARCH 0
|
| 238 |
|
|
#endif
|
| 239 |
|
|
|
| 240 |
|
|
/*
|
| 241 |
|
|
* Define the name of the CPU family.
|
| 242 |
|
|
*/
|
| 243 |
|
|
|
| 244 |
|
|
#if ( M68K_COLDFIRE_ARCH == 1 )
|
| 245 |
|
|
#define CPU_NAME "Motorola ColdFire"
|
| 246 |
|
|
#else
|
| 247 |
|
|
#define CPU_NAME "Motorola MC68xxx"
|
| 248 |
|
|
#endif
|
| 249 |
|
|
|
| 250 |
|
|
#ifndef ASM
|
| 251 |
|
|
|
| 252 |
|
|
#if ( M68K_COLDFIRE_ARCH == 1 )
|
| 253 |
|
|
#define m68k_disable_interrupts( _level ) \
|
| 254 |
|
|
do { register unsigned32 _tmpsr = 0x0700; \
|
| 255 |
|
|
asm volatile ( "move.w %%sr,%0\n\t" \
|
| 256 |
|
|
"or.l %0,%1\n\t" \
|
| 257 |
|
|
"move.w %1,%%sr" \
|
| 258 |
|
|
: "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
|
| 259 |
|
|
} while( 0 )
|
| 260 |
|
|
#else
|
| 261 |
|
|
#define m68k_disable_interrupts( _level ) \
|
| 262 |
|
|
asm volatile ( "move.w %%sr,%0\n\t" \
|
| 263 |
|
|
"or.w #0x0700,%%sr" \
|
| 264 |
|
|
: "=d" (_level))
|
| 265 |
|
|
#endif
|
| 266 |
|
|
|
| 267 |
|
|
#define m68k_enable_interrupts( _level ) \
|
| 268 |
|
|
asm volatile ( "move.w %0,%%sr " : : "d" (_level));
|
| 269 |
|
|
|
| 270 |
|
|
#if ( M68K_COLDFIRE_ARCH == 1 )
|
| 271 |
|
|
#define m68k_flash_interrupts( _level ) \
|
| 272 |
|
|
do { register unsigned32 _tmpsr = 0x0700; \
|
| 273 |
|
|
asm volatile ( "move.w %2,%%sr\n\t" \
|
| 274 |
|
|
"or.l %2,%1\n\t" \
|
| 275 |
|
|
"move.w %1,%%sr" \
|
| 276 |
|
|
: "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
|
| 277 |
|
|
} while( 0 )
|
| 278 |
|
|
#else
|
| 279 |
|
|
#define m68k_flash_interrupts( _level ) \
|
| 280 |
|
|
asm volatile ( "move.w %0,%%sr\n\t" \
|
| 281 |
|
|
"or.w #0x0700,%%sr" \
|
| 282 |
|
|
: : "d" (_level))
|
| 283 |
|
|
#endif
|
| 284 |
|
|
|
| 285 |
|
|
#define m68k_get_interrupt_level( _level ) \
|
| 286 |
|
|
do { \
|
| 287 |
|
|
register unsigned32 _tmpsr; \
|
| 288 |
|
|
\
|
| 289 |
|
|
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
|
| 290 |
|
|
_level = (_tmpsr & 0x0700) >> 8; \
|
| 291 |
|
|
} while (0)
|
| 292 |
|
|
|
| 293 |
|
|
#define m68k_set_interrupt_level( _newlevel ) \
|
| 294 |
|
|
do { \
|
| 295 |
|
|
register unsigned32 _tmpsr; \
|
| 296 |
|
|
\
|
| 297 |
|
|
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
|
| 298 |
|
|
_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
|
| 299 |
|
|
asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
|
| 300 |
|
|
} while (0)
|
| 301 |
|
|
|
| 302 |
|
|
#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
|
| 303 |
|
|
#define m68k_get_vbr( vbr ) \
|
| 304 |
|
|
asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
|
| 305 |
|
|
|
| 306 |
|
|
#define m68k_set_vbr( vbr ) \
|
| 307 |
|
|
asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
|
| 308 |
|
|
|
| 309 |
|
|
#elif ( M68K_COLDFIRE_ARCH == 1 )
|
| 310 |
|
|
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
|
| 311 |
|
|
|
| 312 |
|
|
#define m68k_set_vbr( _vbr ) \
|
| 313 |
|
|
asm volatile ("move.l %%a7,%%d1 \n\t" \
|
| 314 |
|
|
"move.l %0,%%a7\n\t" \
|
| 315 |
|
|
"movec %%a7,%%vbr\n\t" \
|
| 316 |
|
|
"move.l %%d1,%%a7\n\t" \
|
| 317 |
|
|
: : "d" (_vbr) : "d1" );
|
| 318 |
|
|
|
| 319 |
|
|
#else
|
| 320 |
|
|
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
|
| 321 |
|
|
#define m68k_set_vbr( _vbr )
|
| 322 |
|
|
#endif
|
| 323 |
|
|
|
| 324 |
|
|
/*
|
| 325 |
|
|
* The following routine swaps the endian format of an unsigned int.
|
| 326 |
|
|
* It must be static because it is referenced indirectly.
|
| 327 |
|
|
*/
|
| 328 |
|
|
|
| 329 |
|
|
static inline unsigned int m68k_swap_u32(
|
| 330 |
|
|
unsigned int value
|
| 331 |
|
|
)
|
| 332 |
|
|
{
|
| 333 |
|
|
unsigned int swapped = value;
|
| 334 |
|
|
|
| 335 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 336 |
|
|
asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
|
| 337 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 338 |
|
|
|
| 339 |
|
|
return( swapped );
|
| 340 |
|
|
}
|
| 341 |
|
|
|
| 342 |
|
|
static inline unsigned int m68k_swap_u16(
|
| 343 |
|
|
unsigned int value
|
| 344 |
|
|
)
|
| 345 |
|
|
{
|
| 346 |
|
|
unsigned short swapped = value;
|
| 347 |
|
|
|
| 348 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 349 |
|
|
|
| 350 |
|
|
return( swapped );
|
| 351 |
|
|
}
|
| 352 |
|
|
|
| 353 |
|
|
/* XXX this is only valid for some m68k family members and should be fixed */
|
| 354 |
|
|
|
| 355 |
|
|
#define m68k_enable_caching() \
|
| 356 |
|
|
{ register unsigned32 _ctl=0x01; \
|
| 357 |
|
|
asm volatile ( "movec %0,%%cacr" \
|
| 358 |
|
|
: "=d" (_ctl) : "0" (_ctl) ); \
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
#define CPU_swap_u32( value ) m68k_swap_u32( value )
|
| 362 |
|
|
#define CPU_swap_u16( value ) m68k_swap_u16( value )
|
| 363 |
|
|
|
| 364 |
|
|
#endif /* !ASM */
|
| 365 |
|
|
|
| 366 |
|
|
#ifdef __cplusplus
|
| 367 |
|
|
}
|
| 368 |
|
|
#endif
|
| 369 |
|
|
|
| 370 |
|
|
#endif
|
| 371 |
|
|
/* end of include file */
|
