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199 |
simons |
#ifndef ACORNSCSI_H
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#define ACORNSCSI_H
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#ifndef ASM
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extern int acornscsi_detect (Scsi_Host_Template *);
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extern int acornscsi_release (struct Scsi_Host *);
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extern const char *acornscsi_info (struct Scsi_Host *);
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extern int acornscsi_queuecmd (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
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extern int acornscsi_abort (Scsi_Cmnd *);
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extern int acornscsi_reset (Scsi_Cmnd *, unsigned int);
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extern int acornscsi_proc_info (char *, char **, off_t, int, int, int);
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extern int acornscsi_biosparam (Disk *, kdev_t, int []);
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#ifndef NULL
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#define NULL 0
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#endif
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#ifndef CMD_PER_LUN
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#define CMD_PER_LUN 2
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#endif
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#ifndef CAN_QUEUE
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#define CAN_QUEUE 16
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#endif
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#ifndef PROC_SCSI_AKA30
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#include "linux/proc_fs.h"
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#define PROC_SCSI_AKA30 PROC_SCSI_EATA
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#endif
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#include <scsi/scsicam.h>
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#define ACORNSCSI_3 { \
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NULL, /* Ptr for modules */ \
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NULL, /* usage count for modules */ \
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NULL, \
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acornscsi_proc_info, \
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"AcornSCSI", \
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acornscsi_detect, \
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acornscsi_release, /* Release */ \
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acornscsi_info, \
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NULL, \
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acornscsi_queuecmd, \
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acornscsi_abort, \
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acornscsi_reset, \
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NULL, \
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scsicam_bios_param, \
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CAN_QUEUE, /* can_queue */ \
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7, /* this id */ \
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SG_ALL, /* sg_tablesize */ \
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CMD_PER_LUN, /* cmd_per_lun */ \
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0, /* number of boards */ \
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0, /* unchecked isa dma */ \
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DISABLE_CLUSTERING \
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}
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#ifndef HOSTS_C
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/* SBIC registers */
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#define OWNID 0
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#define OWNID_FS1 (1<<7)
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#define OWNID_FS2 (1<<6)
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#define OWNID_EHP (1<<4)
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#define OWNID_EAF (1<<3)
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#define CTRL 1
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#define CTRL_DMAMODE (1<<7)
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#define CTRL_DMADBAMODE (1<<6)
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#define CTRL_DMABURST (1<<5)
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#define CTRL_DMAPOLLED 0
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#define CTRL_HHP (1<<4)
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#define CTRL_EDI (1<<3)
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#define CTRL_IDI (1<<2)
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#define CTRL_HA (1<<1)
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#define CTRL_HSP (1<<0)
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#define TIMEOUT 2
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#define TOTSECTS 3
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#define TOTHEADS 4
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#define TOTCYLH 5
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#define TOTCYLL 6
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#define LOGADDRH 7
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#define LOGADDRM2 8
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#define LOGADDRM1 9
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#define LOGADDRL 10
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#define SECTORNUM 11
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#define HEADNUM 12
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#define CYLH 13
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#define CYLL 14
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#define TARGETLUN 15
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#define TARGETLUN_TLV (1<<7)
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#define TARGETLUN_DOK (1<<6)
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#define CMNDPHASE 16
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#define SYNCHTRANSFER 17
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#define SYNCHTRANSFER_OF0 0x00
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#define SYNCHTRANSFER_OF1 0x01
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#define SYNCHTRANSFER_OF2 0x02
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#define SYNCHTRANSFER_OF3 0x03
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#define SYNCHTRANSFER_OF4 0x04
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#define SYNCHTRANSFER_OF5 0x05
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#define SYNCHTRANSFER_OF6 0x06
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#define SYNCHTRANSFER_OF7 0x07
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#define SYNCHTRANSFER_OF8 0x08
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#define SYNCHTRANSFER_OF9 0x09
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#define SYNCHTRANSFER_OF10 0x0A
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#define SYNCHTRANSFER_OF11 0x0B
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#define SYNCHTRANSFER_OF12 0x0C
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#define SYNCHTRANSFER_8DBA 0x00
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#define SYNCHTRANSFER_2DBA 0x20
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#define SYNCHTRANSFER_3DBA 0x30
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#define SYNCHTRANSFER_4DBA 0x40
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#define SYNCHTRANSFER_5DBA 0x50
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#define SYNCHTRANSFER_6DBA 0x60
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#define SYNCHTRANSFER_7DBA 0x70
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#define TRANSCNTH 18
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#define TRANSCNTM 19
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#define TRANSCNTL 20
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#define DESTID 21
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#define DESTID_SCC (1<<7)
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#define DESTID_DPD (1<<6)
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#define SOURCEID 22
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#define SOURCEID_ER (1<<7)
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#define SOURCEID_ES (1<<6)
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#define SOURCEID_DSP (1<<5)
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#define SOURCEID_SIV (1<<4)
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#define SSR 23
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#define CMND 24
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#define CMND_RESET 0x00
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#define CMND_ABORT 0x01
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#define CMND_ASSERTATN 0x02
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#define CMND_NEGATEACK 0x03
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#define CMND_DISCONNECT 0x04
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#define CMND_RESELECT 0x05
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#define CMND_SELWITHATN 0x06
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#define CMND_SELECT 0x07
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#define CMND_SELECTATNTRANSFER 0x08
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#define CMND_SELECTTRANSFER 0x09
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#define CMND_RESELECTRXDATA 0x0A
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#define CMND_RESELECTTXDATA 0x0B
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#define CMND_WAITFORSELRECV 0x0C
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#define CMND_SENDSTATCMD 0x0D
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#define CMND_SENDDISCONNECT 0x0E
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#define CMND_SETIDI 0x0F
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#define CMND_RECEIVECMD 0x10
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#define CMND_RECEIVEDTA 0x11
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#define CMND_RECEIVEMSG 0x12
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#define CMND_RECEIVEUSP 0x13
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#define CMND_SENDCMD 0x14
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#define CMND_SENDDATA 0x15
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#define CMND_SENDMSG 0x16
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#define CMND_SENDUSP 0x17
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#define CMND_TRANSLATEADDR 0x18
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#define CMND_XFERINFO 0x20
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#define CMND_SBT (1<<7)
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#define DATA 25
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#define ASR 26
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#define ASR_INT (1<<7)
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#define ASR_LCI (1<<6)
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#define ASR_BSY (1<<5)
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#define ASR_CIP (1<<4)
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#define ASR_PE (1<<1)
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#define ASR_DBR (1<<0)
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/* DMAC registers */
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#define INIT 0x00
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#define INIT_8BIT (1)
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#define CHANNEL 0x80
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#define CHANNEL_0 0x00
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#define CHANNEL_1 0x01
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#define CHANNEL_2 0x02
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#define CHANNEL_3 0x03
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#define TXCNTLO 0x01
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#define TXCNTHI 0x81
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#define TXADRLO 0x02
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#define TXADRMD 0x82
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#define TXADRHI 0x03
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#define DEVCON0 0x04
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#define DEVCON0_AKL (1<<7)
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#define DEVCON0_RQL (1<<6)
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#define DEVCON0_EXW (1<<5)
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#define DEVCON0_ROT (1<<4)
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#define DEVCON0_CMP (1<<3)
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#define DEVCON0_DDMA (1<<2)
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#define DEVCON0_AHLD (1<<1)
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#define DEVCON0_MTM (1<<0)
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#define DEVCON1 0x84
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#define DEVCON1_WEV (1<<1)
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#define DEVCON1_BHLD (1<<0)
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#define MODECON 0x05
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#define MODECON_WOED 0x01
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#define MODECON_VERIFY 0x00
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#define MODECON_READ 0x04
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#define MODECON_WRITE 0x08
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#define MODECON_AUTOINIT 0x10
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#define MODECON_ADDRDIR 0x20
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#define MODECON_DEMAND 0x00
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#define MODECON_SINGLE 0x40
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#define MODECON_BLOCK 0x80
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#define MODECON_CASCADE 0xC0
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#define STATUS 0x85
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#define STATUS_TC0 (1<<0)
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#define STATUS_RQ0 (1<<4)
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#define TEMPLO 0x06
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#define TEMPHI 0x86
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#define REQREG 0x07
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#define MASKREG 0x87
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#define MASKREG_M0 0x01
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#define MASKREG_M1 0x02
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#define MASKREG_M2 0x04
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#define MASKREG_M3 0x08
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| 224 |
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/* miscellaneous internal variables */
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#define POD_SPACE(x) ((x) + 0xd0000)
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#define MASK_ON (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0)
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#define MASK_OFF (MASKREG_M3|MASKREG_M2|MASKREG_M1)
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| 230 |
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#define min(x,y) ((x) < (y) ? (x) : (y))
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#define max(x,y) ((x) < (y) ? (y) : (x))
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| 232 |
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| 233 |
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/*
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* SCSI driver phases
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*/
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| 236 |
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typedef enum {
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| 237 |
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PHASE_IDLE, /* we're not planning on doing anything */
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PHASE_CONNECTING, /* connecting to a target */
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PHASE_CONNECTED, /* connected to a target */
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PHASE_MSGOUT, /* message out to device */
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PHASE_RECONNECTED, /* reconnected */
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PHASE_COMMANDPAUSED, /* command partly sent */
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PHASE_COMMAND, /* command all sent */
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PHASE_DATAOUT, /* data out to device */
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PHASE_DATAIN, /* data in from device */
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PHASE_STATUSIN, /* status in from device */
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PHASE_MSGIN, /* message in from device */
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PHASE_DONE, /* finished */
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PHASE_ABORTED, /* aborted */
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PHASE_DISCONNECT, /* disconnecting */
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} phase_t;
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/*
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* After interrupt, what to do now
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*/
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| 256 |
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typedef enum {
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INTR_IDLE, /* not expecting another IRQ */
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INTR_NEXT_COMMAND, /* start next command */
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INTR_PROCESSING, /* interrupt routine still processing */
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| 260 |
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} intr_ret_t;
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| 261 |
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| 262 |
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/*
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| 263 |
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* DMA direction
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| 264 |
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*/
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| 265 |
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typedef enum {
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| 266 |
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DMA_OUT, /* DMA from memory to chip */
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| 267 |
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DMA_IN /* DMA from chip to memory */
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| 268 |
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} dmadir_t;
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| 269 |
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| 270 |
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/*
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| 271 |
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* Synchronous transfer state
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| 272 |
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*/
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| 273 |
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typedef enum { /* Synchronous transfer state */
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| 274 |
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SYNC_ASYNCHRONOUS, /* don't negociate synchronous transfers*/
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SYNC_NEGOCIATE, /* start negociation */
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| 276 |
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SYNC_SENT_REQUEST, /* sent SDTR message */
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| 277 |
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SYNC_COMPLETED, /* received SDTR reply */
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| 278 |
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} syncxfer_t;
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| 279 |
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| 280 |
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/*
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| 281 |
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* Command type
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| 282 |
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*/
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| 283 |
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typedef enum { /* command type */
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| 284 |
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CMD_READ, /* READ_6, READ_10, READ_12 */
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| 285 |
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CMD_WRITE, /* WRITE_6, WRITE_10, WRITE_12 */
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| 286 |
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CMD_MISC, /* Others */
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| 287 |
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} cmdtype_t;
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| 288 |
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| 289 |
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/*
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| 290 |
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* Data phase direction
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| 291 |
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*/
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| 292 |
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typedef enum { /* Data direction */
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| 293 |
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DATADIR_IN, /* Data in phase expected */
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| 294 |
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DATADIR_OUT /* Data out phase expected */
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| 295 |
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} datadir_t;
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| 296 |
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| 297 |
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#include "queue.h"
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| 298 |
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#include "msgqueue.h"
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| 299 |
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| 300 |
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#define STATUS_BUFFER_SIZE 32
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| 301 |
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/*
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| 302 |
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* This is used to dump the previous states of the SBIC
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| 303 |
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*/
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| 304 |
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struct status_entry {
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| 305 |
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unsigned long when;
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| 306 |
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unsigned char ssr;
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| 307 |
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unsigned char ph;
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| 308 |
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unsigned char irq;
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| 309 |
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unsigned char unused;
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| 310 |
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};
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| 311 |
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| 312 |
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#define ADD_STATUS(_q,_ssr,_ph,_irq) \
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| 313 |
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({ \
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| 314 |
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host->status[(_q)][host->status_ptr[(_q)]].when = jiffies; \
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| 315 |
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host->status[(_q)][host->status_ptr[(_q)]].ssr = (_ssr); \
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| 316 |
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host->status[(_q)][host->status_ptr[(_q)]].ph = (_ph); \
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| 317 |
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host->status[(_q)][host->status_ptr[(_q)]].irq = (_irq); \
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| 318 |
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host->status_ptr[(_q)] = (host->status_ptr[(_q)] + 1) & (STATUS_BUFFER_SIZE - 1); \
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| 319 |
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})
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| 320 |
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| 321 |
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/*
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| 322 |
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* AcornSCSI host specific data
|
| 323 |
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*/
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| 324 |
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typedef struct acornscsi_hostdata {
|
| 325 |
|
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/* miscellaneous */
|
| 326 |
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struct Scsi_Host *host; /* host */
|
| 327 |
|
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Scsi_Cmnd *SCpnt; /* currently processing command */
|
| 328 |
|
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Scsi_Cmnd *origSCpnt; /* original connecting command */
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| 329 |
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| 330 |
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/* driver information */
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| 331 |
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struct {
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| 332 |
|
|
unsigned int io_port; /* base address of WD33C93 */
|
| 333 |
|
|
unsigned char irq; /* interrupt */
|
| 334 |
|
|
phase_t phase; /* current phase */
|
| 335 |
|
|
|
| 336 |
|
|
struct {
|
| 337 |
|
|
unsigned char target; /* reconnected target */
|
| 338 |
|
|
unsigned char lun; /* reconnected lun */
|
| 339 |
|
|
unsigned char tag; /* reconnected tag */
|
| 340 |
|
|
} reconnected;
|
| 341 |
|
|
|
| 342 |
|
|
Scsi_Pointer SCp; /* current commands data pointer */
|
| 343 |
|
|
|
| 344 |
|
|
MsgQueue_t msgs;
|
| 345 |
|
|
|
| 346 |
|
|
unsigned short last_message; /* last message to be sent */
|
| 347 |
|
|
unsigned char disconnectable:1; /* this command can be disconnected */
|
| 348 |
|
|
unsigned char interrupt:1; /* interrupt active */
|
| 349 |
|
|
} scsi;
|
| 350 |
|
|
|
| 351 |
|
|
/* statistics information */
|
| 352 |
|
|
struct {
|
| 353 |
|
|
unsigned int queues;
|
| 354 |
|
|
unsigned int removes;
|
| 355 |
|
|
unsigned int fins;
|
| 356 |
|
|
unsigned int reads;
|
| 357 |
|
|
unsigned int writes;
|
| 358 |
|
|
unsigned int miscs;
|
| 359 |
|
|
unsigned int disconnects;
|
| 360 |
|
|
unsigned int aborts;
|
| 361 |
|
|
unsigned int resets;
|
| 362 |
|
|
} stats;
|
| 363 |
|
|
|
| 364 |
|
|
/* queue handling */
|
| 365 |
|
|
struct {
|
| 366 |
|
|
Queue_t issue; /* issue queue */
|
| 367 |
|
|
Queue_t disconnected; /* disconnected command queue */
|
| 368 |
|
|
} queues;
|
| 369 |
|
|
|
| 370 |
|
|
/* per-device info */
|
| 371 |
|
|
struct {
|
| 372 |
|
|
unsigned char sync_xfer; /* synchronous transfer (SBIC value) */
|
| 373 |
|
|
syncxfer_t sync_state; /* sync xfer negociation state */
|
| 374 |
|
|
unsigned char disconnect_ok:1; /* device can disconnect */
|
| 375 |
|
|
} device[8];
|
| 376 |
|
|
unsigned char busyluns[8]; /* array of bits indicating LUNs busy */
|
| 377 |
|
|
|
| 378 |
|
|
/* DMA info */
|
| 379 |
|
|
struct {
|
| 380 |
|
|
unsigned int io_port; /* base address of DMA controller */
|
| 381 |
|
|
unsigned int io_intr_clear; /* address of DMA interrupt clear */
|
| 382 |
|
|
unsigned int free_addr; /* next free address */
|
| 383 |
|
|
unsigned int start_addr; /* start address of current transfer */
|
| 384 |
|
|
dmadir_t direction; /* dma direction */
|
| 385 |
|
|
unsigned int transferred; /* number of bytes transferred */
|
| 386 |
|
|
unsigned int xfer_start; /* scheduled DMA transfer start */
|
| 387 |
|
|
unsigned int xfer_length; /* scheduled DMA transfer length */
|
| 388 |
|
|
char *xfer_ptr; /* pointer to area */
|
| 389 |
|
|
unsigned char xfer_required:1; /* set if we need to transfer something */
|
| 390 |
|
|
unsigned char xfer_setup:1; /* set if DMA is setup */
|
| 391 |
|
|
unsigned char xfer_done:1; /* set if DMA reached end of BH list */
|
| 392 |
|
|
} dma;
|
| 393 |
|
|
|
| 394 |
|
|
/* card info */
|
| 395 |
|
|
struct {
|
| 396 |
|
|
unsigned int io_intr; /* base address of interrupt id reg */
|
| 397 |
|
|
unsigned int io_page; /* base address of page reg */
|
| 398 |
|
|
unsigned int io_ram; /* base address of RAM access */
|
| 399 |
|
|
unsigned char page_reg; /* current setting of page reg */
|
| 400 |
|
|
} card;
|
| 401 |
|
|
|
| 402 |
|
|
unsigned char status_ptr[9];
|
| 403 |
|
|
struct status_entry status[9][STATUS_BUFFER_SIZE];
|
| 404 |
|
|
} AS_Host;
|
| 405 |
|
|
|
| 406 |
|
|
#endif /* ndef HOSTS_C */
|
| 407 |
|
|
|
| 408 |
|
|
#endif /* ndef ASM */
|
| 409 |
|
|
#endif /* ACORNSCSI_H */
|
