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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [ppc/] [kernel/] [head.S] - Blame information for rev 1781

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1 199 simons 
#include "ppc_asm.tmpl"
2 
#include "ppc_defs.h"
3 
#include
4 
#define NEWMM
5 
#define SYNC() \
6 
        isync; \
7 
        sync
8 
 
9 
/* #define TLB_STATS */
10 
 
11 
/* Keep track of low-level exceptions - rather crude, but informative */
12 
#define STATS
13 
 
14 
/*
15 
 * Increment a [64 bit] statistic counter
16 
 * Uses R2, R3
17 
 */
18 
#define BUMP(ctr) \
19 
        lis     r2,ctr@h; \
20 
        ori     r2,r2,ctr@l; \
21 
        lwz     r3,4(r2); \
22 
        addic   r3,r3,1; \
23 
        stw     r3,4(r2); \
24 
        lwz     r3,0(r2); \
25 
        addze   r3,r3; \
26 
        stw     r3,0(r2)
27 
 
28 
/* The same as 'BUMP' but running unmapped (TLB code) */
29 
#define BUMP_UNMAPPED(ctr) \
30 
        mfspr   r0,XER; \
31 
        lis     r2,ctr@h; \
32 
        ori     r2,r2,ctr@l; \
33 
        lis     r3,0xF000; \
34 
        andc    r2,r2,r3; \
35 
        lwz     r3,4(r2); \
36 
        addic   r3,r3,1; \
37 
        stw     r3,4(r2); \
38 
        lwz     r3,0(r2); \
39 
        addze   r3,r3; \
40 
        mtspr   XER,r0; \
41 
        stw     r3,0(r2)
42 
 
43 
/* These macros can be used to generate very raw traces of low-level */
44 
/* operations (where printf, etc. can't help).  All they provide is */
45 
/* some after-the-fact documentation of what took place.  Since [in */
46 
/* most instances] they have no registers to work with, they use the */
47 
/* hardware "special" registers SPRx for storage.  Because of this, */
48 
/* defining more than one of them simultaneously will yield incorrect */
49 
/* results and a non-functional system.  Note: the trick here is to */
50 
/* gather some data without disturbing anything - Heisenberg are you watching? */
51 
 
52 
/* CAUTION! Don't turn on more than one of these at once! */
53 
/* #define DO_TRAP_TRACE   */
54 
/* #define DO_TLB_TRACE    */
55 
/* #define DO_RFI_TRACE    */
56 
 
57 
#ifdef DO_RFI_TRACE
58 
#define DO_RFI_TRACE_UNMAPPED(mark) \
59 
        mtspr   SPR0,r1; \
60 
        mtspr   SPR1,r2; \
61 
        mtspr   SPR2,r3; \
62 
        mfcr    r3; \
63 
        mtspr   SPR3,r3; \
64 
        lis     r1,_RFI_ptr@h; \
65 
        ori     r1,r1,_RFI_ptr@l; \
66 
        lis     r3,0xF000; \
67 
        andc    r1,r1,r3; \
68 
        lwz     r1,0(r1); \
69 
        andc    r1,r1,r3; \
70 
        subi    r1,r1,4; \
71 
        lis     r2,(mark>>16); \
72 
        ori     r2,r2,(mark&0xFFFF); \
73 
        stwu    r2,4(r1); \
74 
        mfspr   r2,SRR0; \
75 
        stwu    r2,4(r1); \
76 
        mfspr   r2,SRR1; \
77 
        stwu    r2,4(r1); \
78 
        addi    r1,r1,4+4; \
79 
        lis     r2,_RFI_ptr@h; \
80 
        ori     r2,r2,_RFI_ptr@l; \
81 
        andc    r2,r2,r3; \
82 
        stw     r1,0(r2); \
83 
        mfspr   r3,SPR3; \
84 
        mtcrf   0xFF,r3; \
85 
        mfspr   r1,SPR0; \
86 
        mfspr   r2,SPR1; \
87 
        mfspr   r3,SPR2
88 
#define DO_RFI_TRACE_MAPPED(mark) \
89 
        mtspr   SPR0,r1; \
90 
        mtspr   SPR1,r2; \
91 
        mtspr   SPR2,r3; \
92 
        mfcr    r3; \
93 
        mtspr   SPR3,r3; \
94 
        lis     r1,_RFI_ptr@h; \
95 
        ori     r1,r1,_RFI_ptr@l; \
96 
        lwz     r1,0(r1); \
97 
        lis     r3,0x9000; \
98 
        or      r1,r1,r3; \
99 
        subi    r1,r1,4; \
100 
        lis     r2,(mark>>16); \
101 
        ori     r2,r2,(mark&0xFFFF); \
102 
        stwu    r2,4(r1); \
103 
        mfspr   r2,SRR0; \
104 
        stwu    r2,4(r1); \
105 
        mfspr   r2,SRR1; \
106 
        stwu    r2,4(r1); \
107 
        addi    r1,r1,4+4; \
108 
        lis     r2,_RFI_ptr@h; \
109 
        ori     r2,r2,_RFI_ptr@l; \
110 
        stw     r1,0(r2); \
111 
        mfspr   r3,SPR3; \
112 
        mtcrf   0xFF,r3; \
113 
        mfspr   r1,SPR0; \
114 
        mfspr   r2,SPR1; \
115 
        mfspr   r3,SPR2
116 
#else
117 
#define DO_RFI_TRACE_UNMAPPED(mark)
118 
#define DO_RFI_TRACE_MAPPED(mark)
119 
#endif
120 
 
121 
#ifdef DO_TRAP_TRACE
122 
#define DEFAULT_TRAP(offset) \
123 
        mtspr   SPR0,r1; \
124 
        mtspr   SPR1,r2; \
125 
        mtspr   SPR2,r3; \
126 
        lis     r1,_TRAP_ptr@h; \
127 
        ori     r1,r1,_TRAP_ptr@l; \
128 
        lis     r3,0xF000; \
129 
        andc    r1,r1,r3; \
130 
        lwz     r1,0(r1); \
131 
        andc    r1,r1,r3; \
132 
        subi    r1,r1,4; \
133 
        lis     r2,0xCACA; \
134 
        ori     r2,r2,offset; \
135 
        stwu    r2,4(r1); \
136 
        mfspr   r2,SRR0; \
137 
        stwu    r2,4(r1); \
138 
        mfspr   r2,SRR1; \
139 
        stwu    r2,4(r1); \
140 
        mfspr   r2,SPR0; \
141 
        stwu    r2,4(r1); \
142 
        addi    r1,r1,4; \
143 
        lis     r2,_TRAP_ptr@h; \
144 
        ori     r2,r2,_TRAP_ptr@l; \
145 
        andc    r2,r2,r3; \
146 
        stw     r1,0(r2); \
147 
        mfspr   r1,SPR0; \
148 
        mfspr   r2,SPR1; \
149 
        mfspr   r3,SPR2; \
150 
        li      r13,0; \
151 
        ori     r13,r13,HID0_ICE; \
152 
        mtspr   HID0,r13; \
153 
        lis     r13,0xFFF00000>>16; \
154 
        ori     r13,r13,offset; \
155 
        mtlr    r13; \
156 
        b       hang
157 
#define TRACE_TRAP(offset) \
158 
        mtspr   SPR0,r1; \
159 
        mtspr   SPR1,r2; \
160 
        mtspr   SPR2,r3; \
161 
        mfcr    r3; \
162 
        mtspr   SPR3,r3; \
163 
        lis     r1,_TRAP_ptr@h; \
164 
        ori     r1,r1,_TRAP_ptr@l; \
165 
        lis     r3,0xF000; \
166 
        andc    r1,r1,r3; \
167 
        lwz     r1,0(r1); \
168 
        andc    r1,r1,r3; \
169 
        subi    r1,r1,4; \
170 
        lis     r2,0xCABB; \
171 
        ori     r2,r2,offset; \
172 
        stwu    r2,4(r1); \
173 
        dcbst   0,r1; \
174 
        mfspr   r2,SRR0; \
175 
        stwu    r2,4(r1); \
176 
        dcbst   0,r1; \
177 
        mfspr   r2,SRR1; \
178 
        stwu    r2,4(r1); \
179 
        dcbst   0,r1; \
180 
        li      r2,offset; \
181 
        cmpi    0,r2,0x0C00; \
182 
        beq     01f; \
183 
        cmpi    0,r2,0x0300; \
184 
        beq     00f; \
185 
        cmpi    0,r2,0x0400; \
186 
        beq     00f; \
187 
        mfspr   r2,SPR0; \
188 
        b       02f; \
189 
00:     mfspr   r2,DAR; \
190 
        b       02f; \
191 
01:     mr      r2,r0; \
192 
02:     stwu    r2,4(r1); \
193 
        dcbst   0,r1; \
194 
        addi    r1,r1,4; \
195 
        mflr    r2; \
196 
        stw     r2,0(r1); \
197 
        bl      check_trace; \
198 
        lwz     r2,0(r1); \
199 
        mtlr    r2; \
200 
02:     lis     r2,_TRAP_ptr@h; \
201 
        ori     r2,r2,_TRAP_ptr@l; \
202 
        oris    r1,r1,0x9000; \
203 
        cmp     0,r1,r2; \
204 
        bne     00f; \
205 
        lis     r1,_TRAP_TRACE@h; \
206 
        ori     r1,r1,_TRAP_TRACE@l; \
207 
00:     lis     r3,0xF000; \
208 
        andc    r2,r2,r3; \
209 
        stw     r1,0(r2); \
210 
        mfspr   r1,SPR0; \
211 
        mfspr   r2,SPR1; \
212 
        mfspr   r3,SPR3; \
213 
        mtcrf   0xFF,r3; \
214 
        mfspr   r3,SPR2
215 
#else
216 
#define DEFAULT_TRAP(offset) \
217 
        li      r13,0; \
218 
        ori     r13,r13,HID0_ICE; \
219 
        mtspr   HID0,r13; \
220 
        lis     r13,0xFFF00000>>16; \
221 
        ori     r13,r13,offset; \
222 
        mtlr    r13; \
223 
        blr
224 
#define TRACE_TRAP(offset)
225 
#endif
226 
 
227 
#define DATA_CACHE_OFF() \
228 
        mfspr   r2,HID0; \
229 
        li      r3,0; \
230 
        ori     r3,r3,HID0_DCE; \
231 
        andc    r2,r2,r3; \
232 
        mtspr   HID0,r2;
233 
 
234 
#define DATA_CACHE_ON() \
235 
        mfspr   r2,HID0; \
236 
        ori     r2,r2,HID0_DCE; \
237 
        mtspr   HID0,r2;
238 
 
239 
/* This instruction is not implemented on the PPC 603 */
240 
#define tlbia \
241 
        li      r4,64; \
242 
        mtspr   CTR,r4; \
243 
        lis     r4,0x9000; \
244 
0:      tlbie   r4; \
245 
        addi    r4,r4,0x1000; \
246 
        bdnz    0b
247 
 
248 
/* Validate kernel stack - check for overflow */
249 
#define CHECK_STACK()
250 
#define _CHECK_STACK() \
251 
        mtspr   SPR0,r3; \
252 
        lis     r2,current_set@ha; \
253 
        lwz     r2,current_set@l(r2); \
254 
        lwz     r2,KERNEL_STACK_PAGE(r2); \
255 
        lis     r3,sys_stack@h; \
256 
        ori     r3,r3,sys_stack@l; \
257 
        cmpl    0,r1,r3; \
258 
        ble     02f; \
259 
        li      r3,0x0FFF; \
260 
        andc    r2,r2,r3; \
261 
        andc    r3,r1,r3; \
262 
        cmp     0,r3,r2; \
263 
        beq     02f; \
264 
        mr      r3,r1; \
265 
        bl      _EXTERN(bad_stack); \
266 
02:     mfspr   r3,SPR0
267 
 
268 
/* Save all registers on kernel stack during an exception */
269 
#define SAVE_REGS(mark) \
270 
        subi    r1,r1,INT_FRAME_SIZE;   /* Make room for frame */ \
271 
        stmw    r3,GPR3(r1);    /* Save R3..R31 */ \
272 
        stw     r3,ORIG_GPR3(r1); \
273 
        stw     r0,GPR0(r1); \
274 
        mfspr   r2,SPR0; \
275 
        stw     r2,GPR1(r1); \
276 
        mfspr   r2,SPR1; \
277 
        stw     r2,GPR2(r1); \
278 
        mfspr   r2,SPR2; \
279 
        stw     r2,_NIP(r1); \
280 
        mfspr   r2,SPR3; \
281 
        stw     r2,_MSR(r1); \
282 
        mfctr   r2; \
283 
        stw     r2,_CTR(r1); \
284 
        mflr    r2; \
285 
        stw     r2,_LINK(r1); \
286 
        mfcr    r2; \
287 
        stw     r2,_CCR(r1); \
288 
        mfspr   r2,XER; \
289 
        stw     r2,_XER(r1); \
290 
        stfd    fr0,FPR0(r1); \
291 
        stfd    fr1,FPR1(r1); \
292 
        stfd    fr2,FPR2(r1); \
293 
        stfd    fr3,FPR3(r1); \
294 
        mffs    fr0; \
295 
        stfd    fr0,FPCSR(r1); \
296 
        lis     r2,_break_lwarx@h; \
297 
        ori     r2,r2,_break_lwarx@l; \
298 
        stwcx.  r2,0,r2; \
299 
        li      r2,mark; \
300 
        stw     r2,TRAP(r1); \
301 
        lis     r2,0xDEAD; \
302 
        ori     r2,r2,0xDEAD; \
303 
        stw     r2,MARKER(r1); \
304 
        li      r2,0; \
305 
        stw     r2,RESULT(r1)
306 
 
307 
#define SAVE_PAGE_FAULT_REGS(offset) \
308 
        mfspr   r2,DAR; \
309 
        stw     r2,_DAR(r1); \
310 
        mfspr   r2,DSISR; \
311 
        stw     r2,_DSISR(r1); \
312 
        mfspr   r2,PVR;                 /* Check for 603/603e */ \
313 
        srwi    r2,r2,16; \
314 
        cmpi    0,r2,3;                 /* 603 */ \
315 
        beq     22f; \
316 
        cmpi    0,r2,6;                 /* 603e */ \
317 
        bne     24f; \
318 
22:     mfspr   r2,HASH1;               /* Note: these registers exist only on 603 */ \
319 
        stw     r2,_HASH1(r1); \
320 
        mfspr   r2,HASH2; \
321 
        stw     r2,_HASH2(r1); \
322 
        mfspr   r2,IMISS; \
323 
        stw     r2,_IMISS(r1); \
324 
        mfspr   r2,DMISS; \
325 
        stw     r2,_DMISS(r1); \
326 
        mfspr   r2,ICMP; \
327 
        stw     r2,_ICMP(r1); \
328 
        mfspr   r2,DCMP; \
329 
        stw     r2,_DCMP(r1); \
330 
24:
331 
 
332 
#define SAVE_INT_REGS(mark) \
333 
        mtspr   SPR0,r1;        /* Save current stack pointer */ \
334 
        mtspr   SPR1,r2;        /* Scratch */ \
335 
        mfcr    r2; \
336 
        mtspr   SPR2,r2; \
337 
        mfspr   r2,SRR1;        /* Interrupt from user/system mode */ \
338 
        andi.   r2,r2,MSR_PR; \
339 
        beq+    10f;            /* Jump if system - already have stack */ \
340 
        mfspr   r2,SPR2;        /* Restore CCR */ \
341 
        mtcrf   0xFF,r2; \
342 
        mfspr   r2,SRR0;        /* Preserve interrupt registers */ \
343 
        mtspr   SPR2,r2; \
344 
        mfspr   r2,SRR1; \
345 
        mtspr   SPR3,r2; \
346 
        lis     r2,05f@h; \
347 
        ori     r2,r2,05f@l; \
348 
        mtspr   SRR0,r2; \
349 
        mfmsr   r2; \
350 
        ori     r2,r2,MSR_|MSR_DR|MSR_IR; \
351 
        mtspr   SRR1,r2; \
352 
        rfi; \
353 
05:     lis     r2,current_set@ha; \
354 
        lwz     r2,current_set@l(r2); \
355 
        mfspr   r1,SPR2; \
356 
        stw     r1,TSS+LAST_PC(r2); \
357 
        mfspr   r1,SPR0; \
358 
        stw     r1,TSS+USER_STACK(r2); \
359 
        lwz     r1,TSS+KSP(r2); \
360 
        subi    r1,r1,INT_FRAME_SIZE;   /* Make room for frame */ \
361 
        stw     r1,TSS+PT_REGS(r2);     /* Save regs pointer for 'ptrace' */ \
362 
        lwz     r1,TSS+KSP(r2); \
363 
        b       20f; \
364 
10:     mfspr   r2,SPR2;        /* Restore CCR */ \
365 
        mtcrf   0xFF,r2; \
366 
        mfspr   r2,SRR0;        /* Preserve interrupt registers */ \
367 
        mtspr   SPR2,r2; \
368 
        mfspr   r2,SRR1; \
369 
        mtspr   SPR3,r2; \
370 
        lis     r2,20f@h; \
371 
        ori     r2,r2,20f@l; \
372 
        mtspr   SRR0,r2; \
373 
        mfmsr   r2; \
374 
        ori     r2,r2,MSR_|MSR_DR|MSR_IR; \
375 
        mtspr   SRR1,r2; \
376 
        SYNC(); \
377 
        rfi; \
378 
20:     SAVE_REGS(mark); \
379 
        CHECK_STACK()
380 
 
381 
#define RETURN_FROM_INT(mark) \
382 
90:     mfmsr   r0;             /* Disable interrupts */ \
383 
        li      r4,0; \
384 
        ori     r4,r4,MSR_EE; \
385 
        andc    r0,r0,r4; \
386 
        sync;                   /* Some chip revs need this... */ \
387 
        mtmsr   r0; \
388 
        lis     r2,intr_count@ha; /* Need to run 'bottom half' */ \
389 
        lwz     r3,intr_count@l(r2); \
390 
        cmpi    0,r3,0; \
391 
        bne     00f; \
392 
        lis     r4,bh_mask@ha; \
393 
        lwz     r4,bh_mask@l(r4); \
394 
        lis     r5,bh_active@ha; \
395 
        lwz     r5,bh_active@l(r5); \
396 
        and.    r4,r4,r5; \
397 
        beq     00f; \
398 
        addi    r3,r3,1; \
399 
        stw     r3,intr_count@l(r2); \
400 
        bl      _EXTERN(_do_bottom_half); \
401 
        lis     r2,intr_count@ha; \
402 
        lwz     r3,intr_count@l(r2); \
403 
        subi    r3,r3,1; \
404 
        stw     r3,intr_count@l(r2); \
405 
00:     lwz     r2,_MSR(r1); /* Returning to user mode? */ \
406 
        andi.   r2,r2,MSR_PR; \
407 
        beq+    10f;            /* no - no need to mess with stack */ \
408 
/*      lis     r2,kernel_pages_are_copyback@ha; \
409 
        lwz     r2,kernel_pages_are_copyback@l(r2); \
410 
        cmpi    0,r2,0; \
411 
        beq     05f; \
412 
        bl      _EXTERN(flush_instruction_cache); */ \
413 
05:     lis     r3,current_set@ha;      /* need to save kernel stack pointer */ \
414 
        lwz     r3,current_set@l(r3); \
415 
        addi    r4,r1,INT_FRAME_SIZE;   /* size of frame */ \
416 
        stw     r4,TSS+KSP(r3); \
417 
        lwz     r4,STATE(r3);   /* If state != 0, can't run */ \
418 
        cmpi    0,r4,0; \
419 
        beq     06f; \
420 
        bl      _EXTERN(schedule); \
421 
        b       90b; \
422 
06:     lwz     r4,COUNTER(r3); /* Time quantum expired? */ \
423 
        cmpi    0,r4,0; \
424 
        bne     07f; \
425 
        bl      _EXTERN(schedule); \
426 
        b       90b; \
427 
07:     lwz     r4,BLOCKED(r3); /* Check for pending unblocked signals */ \
428 
        lwz     r5,SIGNAL(r3); \
429 
        andc.   r0,r5,r4;       /* Lets thru any unblocked */ \
430 
        beq     10f; \
431 
        mr      r3,r4; \
432 
        mr      r4,r1; \
433 
        bl      _EXTERN(do_signal); \
434 
10:     lwz     r2,_NIP(r1);    /* Restore environment */ \
435 
        mtspr   SRR0,r2; \
436 
        lwz     r2,_MSR(r1); \
437 
        mtspr   SRR1,r2; \
438 
        lmw     r3,GPR3(r1); \
439 
        lwz     r2,_CTR(r1); \
440 
        mtctr   r2; \
441 
        lwz     r2,_LINK(r1); \
442 
        mtlr    r2; \
443 
        lwz     r2,_XER(r1); \
444 
        mtspr   XER,r2; \
445 
        lwz     r2,_CCR(r1); \
446 
        mtcrf   0xFF,r2; \
447 
        lfd     fr0,FPCSR(r1); \
448 
        mtfsf   0xFF,fr0; \
449 
        lfd     fr0,FPR0(r1); \
450 
        lfd     fr1,FPR1(r1); \
451 
        lfd     fr2,FPR2(r1); \
452 
        lfd     fr3,FPR3(r1); \
453 
        lwz     r0,GPR0(r1); \
454 
        lwz     r2,GPR2(r1); \
455 
        lwz     r1,GPR1(r1); \
456 
        SYNC(); \
457 
        rfi
458 
 
459 
_TEXT()
460 
/*
461 
 * This code may be executed by a bootstrap process.  If so, the
462 
 * purpose is to relocate the loaded image to it's final location
463 
 * in memory.
464 
 *    R3: End of image
465 
 *    R4: Start of image - 0x400
466 
 *   R11: Start of command line string
467 
 *   R12: End of command line string
468 
 *   R30: 'BeBx' if this is a BeBox
469 
 *
470 
 */
471 
        .globl  _start
472 
        .globl  _stext
473 
_stext:
474 
_start:
475 
        addi    r4,r4,0x400     /* Point at start of image */
476 
        li      r5,0            /* Load address */
477 
        subi    r4,r4,4         /* Adjust for auto-increment */
478 
        subi    r5,r5,4
479 
        subi    r3,r3,4
480 
00:     lwzu    r0,4(r4)        /* Fast move */
481 
        stwu    r0,4(r5)
482 
        cmp     0,r3,r4
483 
        bne     00b
484 
        li      r5,0x100        /* Actual code starts here */
485 
        mtlr    r5
486 
        blr
487 
 
488 
hang:
489 
        ori     r0,r0,0
490 
        b       hang
491 
 
492 
/*
493 
 * BeBox CPU #1 vector & code
494 
 */
495 
_ORG(0x0080)
496 
        .globl  BeBox_CPU1_vector
497 
BeBox_CPU1_vector:
498 
        .long   0
499 
BeBox_CPU1_reset:
500 
        li      r1,BeBox_CPU1_vector@l
501 
        li      r2,0
502 
        stw     r2,0(r1)
503 
00:     lwz     r2,0(r1)
504 
        cmpi    0,r2,0
505 
        bne     10f
506 
        li      r2,10000
507 
        mtctr   r2
508 
02:     nop
509 
        bdnz    02b
510 
        b       00b
511 
10:     mtlr    r1
512 
        blr
513 
 
514 
_ORG(0x0100)
515 
 
516 
/* Hard Reset */
517 
        .globl  HardReset
518 
HardReset:
519 
        b       Reset
520 
 
521 
_ORG(0x0200)
522 
        b       MachineCheck
523 
 
524 
_ORG(0x0300)
525 
        b       DataAccess
526 
 
527 
_ORG(0x0400)
528 
        b       InstructionAccess
529 
 
530 
_ORG(0x0500)
531 
        b       HardwareInterrupt
532 
 
533 
_ORG(0x0600)
534 
        b       Alignment
535 
 
536 
_ORG(0x0700)
537 
        b       ProgramCheck
538 
 
539 
_ORG(0x0800)
540 
        b       FloatingPointCheck
541 
 
542 
/* Decrementer register - ignored for now... */
543 
_ORG(0x0900)
544 
/* TRACE_TRAP(0x900) */
545 
        mtspr   SPR0,r1
546 
        lis     r1,0x7FFF
547 
        ori     r1,r1,0xFFFF
548 
        mtspr   DEC,r1
549 
        mfspr   r1,SPR0
550 
#if 0
551 
        SYNC
552 
#endif
553 
        rfi
554 
 
555 
_ORG(0x0A00)
556 
DEFAULT_TRAP(0x0A00)
557 
_ORG(0x0B00)
558 
DEFAULT_TRAP(0x0B00)
559 
 
560 
/*
561 
 * System call
562 
 */
563 
_ORG(0x0C00)
564 
        b       SystemCall
565 
 
566 
_ORG(0x0D00)
567 
        b       SingleStep
568 
 
569 
_ORG(0x0E00)
570 
DEFAULT_TRAP(0x0E00)
571 
_ORG(0x0F00)
572 
DEFAULT_TRAP(0x0F00)
573 
 
574 
/*
575 
 * Handle TLB Miss on an instruction load
576 
 */
577 
_ORG(0x1000)
578 
/* Note: It is *unsafe* to use the TRACE TRAP macro here since there */
579 
/* could be a 'trace' in progress when the TLB miss occurs.          */
580 
/* TRACE_TRAP(0x1000) */
581 
#ifdef TLB_STATS
582 
        lis     r2,DataLoadTLB_trace_ptr@h
583 
        ori     r2,r2,DataLoadTLB_trace_ptr@l
584 
        lis     r3,0xF000
585 
        andc    r2,r2,r3
586 
        lwz     r1,0(r2)
587 
        andc    r1,r1,r3
588 
        li      r0,0x1000
589 
        stw     r0,0(r1)
590 
        mftbu   r0
591 
        stw     r0,4(r1)
592 
        mftb    r0
593 
        stw     r0,8(r1)
594 
        mfspr   r0,IMISS
595 
        mfspr   r3,SRR1
596 
        extrwi  r3,r3,1,14
597 
        or      r0,r0,r3
598 
        stw     r0,12(r1)
599 
        addi    r1,r1,16
600 
        mfcr    r0
601 
        cmpl    0,r1,r2
602 
        blt     00f
603 
        lis     r1,DataLoadTLB_trace_buf@h
604 
        ori     r1,r1,DataLoadTLB_trace_buf@l
605 
        lis     r3,0xF000
606 
        andc    r1,r1,r3
607 
00:     mtcrf   0xFF,r0
608 
        stw     r1,0(r2)
609 
#endif
610 
        b       InstructionTLBMiss
611 
 
612 
/*
613 
 * Handle TLB Miss on a data item load
614 
 */
615 
_ORG(0x1100)
616 
/* TRACE_TRAP(0x1100) */
617 
#ifdef TLB_STATS
618 
        lis     r2,DataLoadTLB_trace_ptr@h
619 
        ori     r2,r2,DataLoadTLB_trace_ptr@l
620 
        lis     r3,0xF000
621 
        andc    r2,r2,r3
622 
        lwz     r1,0(r2)
623 
        andc    r1,r1,r3
624 
        li      r0,0x1100
625 
        stw     r0,0(r1)
626 
        mftbu   r0
627 
        stw     r0,4(r1)
628 
        mftb    r0
629 
        stw     r0,8(r1)
630 
        mfspr   r0,DMISS
631 
        mfspr   r3,SRR1
632 
        extrwi  r3,r3,1,14
633 
        or      r0,r0,r3
634 
        stw     r0,12(r1)
635 
        addi    r1,r1,16
636 
        mfcr    r0
637 
        cmpl    0,r1,r2
638 
        blt     00f
639 
        lis     r1,DataLoadTLB_trace_buf@h
640 
        ori     r1,r1,DataLoadTLB_trace_buf@l
641 
        lis     r3,0xF000
642 
        andc    r1,r1,r3
643 
00:     mtcrf   0xFF,r0
644 
        stw     r1,0(r2)
645 
        .data
646 
DataLoadTLB_trace_buf:
647 
        .space  64*1024*4
648 
DataLoadTLB_trace_ptr:
649 
        .long   DataLoadTLB_trace_buf
650 
        .text
651 
#endif
652 
        b       DataLoadTLBMiss
653 
 
654 
/*
655 
 * Handle TLB Miss on a store operation
656 
 */
657 
_ORG(0x1200)
658 
/* TRACE_TRAP(0x1200) */
659 
#ifdef TLB_STATS
660 
        lis     r2,DataLoadTLB_trace_ptr@h
661 
        ori     r2,r2,DataLoadTLB_trace_ptr@l
662 
        lis     r3,0xF000
663 
        andc    r2,r2,r3
664 
        lwz     r1,0(r2)
665 
        andc    r1,r1,r3
666 
        li      r0,0x1200
667 
        stw     r0,0(r1)
668 
        mftbu   r0
669 
        stw     r0,4(r1)
670 
        mftb    r0
671 
        stw     r0,8(r1)
672 
        mfspr   r0,DMISS
673 
        mfspr   r3,SRR1
674 
        extrwi  r3,r3,1,14
675 
        or      r0,r0,r3
676 
        stw     r0,12(r1)
677 
        addi    r1,r1,16
678 
        mfcr    r0
679 
        cmpl    0,r1,r2
680 
        blt     00f
681 
        lis     r1,DataLoadTLB_trace_buf@h
682 
        ori     r1,r1,DataLoadTLB_trace_buf@l
683 
        lis     r3,0xF000
684 
        andc    r1,r1,r3
685 
00:     mtcrf   0xFF,r0
686 
        stw     r1,0(r2)
687 
#endif
688 
        b       DataStoreTLBMiss
689 
 
690 
_ORG(0x1300)
691 
InstructionAddressBreakpoint:
692 
        DEFAULT_TRAP(0x1300)
693 
 
694 
_ORG(0x1400)
695 
SystemManagementInterrupt:
696 
        DEFAULT_TRAP(0x1400)
697 
 
698 
_ORG(0x1500)
699 
 
700 
/*
701 
 * This space [buffer] is used to forceably flush the data cache when
702 
 * running in copyback mode.  This is necessary IFF the data cache could
703 
 * contain instructions for which the instruction cache has stale data.
704 
 * Since the instruction cache NEVER snoops the data cache, memory must
705 
 * be made coherent with the data cache to insure that the instruction
706 
 * cache gets a valid instruction stream.  Note that this flushing is
707 
 * only performed when switching from system to user mode since this is
708 
 * the only juncture [as far as the OS goes] where the data cache may
709 
 * contain instructions, e.g. after a disk read.
710 
 */
711 
#define NUM_CACHE_LINES 128*4
712 
#define CACHE_LINE_SIZE 32
713 
cache_flush_buffer:
714 
        .space  NUM_CACHE_LINES*CACHE_LINE_SIZE /* CAUTION! these need to match hardware */
715 
 
716 
#if NUM_CACHE_LINES < 512
717 
_ORG(0x4000)
718 
#endif
719 
 
720 
 
721 
/*
722 
 * Hardware reset [actually from bootstrap]
723 
 * Initialize memory management & call secondary init
724 
 * Registers initialized by bootstrap:
725 
 *   R11: Start of command line string
726 
 *   R12: End of command line string
727 
 *   R30: 'BeBx' if this is a BeBox
728 
 */
729 
Reset:
730 
        lis     r7,0xF000               /* To mask upper 4 bits */
731 
#define IS_BE_BOX       0x42654278      /* 'BeBx' */
732 
        lis     r1,isBeBox@h
733 
        ori     r1,r1,isBeBox@l
734 
        andc    r1,r1,r7
735 
/* See if this is a CPU other than CPU#1 */
736 
/* This [currently] happens on the BeBox */
737 
        lwz     r2,0(r1)
738 
        cmpi    0,r2,0
739 
        bne     Reset_BeBox_CPU1
740 
/* Save machine type indicator */
741 
        li      r2,0
742 
        lis     r3,IS_BE_BOX>>16
743 
        ori     r3,r3,IS_BE_BOX&0xFFFF
744 
        cmp     0,r30,r3
745 
        bne     00f
746 
        li      r2,1
747 
        mr      r11,r28
748 
        mr      r12,r29
749 
        lis     r5,BeBox_CPU1_vector@h
750 
        ori     r5,r5,BeBox_CPU1_vector@l
751 
        andc    r5,r5,r7                /* Tell CPU #1 where to go */
752 
00:     stw     r2,0(r1)
753 
        stw     r30,4(r1)
754 
/* Copy argument string */
755 
        li      r0,0            /* Null terminate string */
756 
        stb     r0,0(r12)
757 
        lis     r1,cmd_line@h
758 
        ori     r1,r1,cmd_line@l
759 
        andc    r1,r1,r7        /* No MMU yet - need unmapped address */
760 
        subi    r1,r1,1
761 
        subi    r11,r11,1
762 
00:     lbzu    r0,1(r11)
763 
        cmpi    0,r0,0
764 
        stbu    r0,1(r1)
765 
        bne     00b
766 
        lis     r1,sys_stack@h
767 
        ori     r1,r1,sys_stack@l
768 
        li      r2,0x0FFF       /* Mask stack address down to page boundary */
769 
        andc    r1,r1,r2
770 
        subi    r1,r1,INT_FRAME_SIZE    /* Padding for first frame */
771 
        li      r2,0            /* TOC pointer for nanokernel */
772 
        li      r0,MSR_         /* Make sure FPU enabled */
773 
        mtmsr   r0
774 
        lis     r3,_edata@h     /* Clear BSS */
775 
        ori     r3,r3,_edata@l
776 
        andc    r3,r3,r7        /* make unmapped address */
777 
        lis     r4,_end@h
778 
        ori     r4,r4,_end@l
779 
        andc    r4,r4,r7        /* make unmapped address */
780 
        subi    r3,r3,4
781 
        li      r0,0
782 
00:     stwu    r0,4(r3)
783 
        cmp     0,r3,r4
784 
        blt     00b
785 
/* Initialize BAT registers */
786 
        lis     r3,BAT0@h
787 
        ori     r3,r3,BAT0@l
788 
        andc    r3,r3,r7        /* make unmapped address */
789 
        lwz     r0,0(r3)
790 
        mtspr   IBAT0U,r0
791 
        mtspr   DBAT0U,r0
792 
        lwz     r0,4(r3)
793 
        mtspr   IBAT0L,r0
794 
        mtspr   DBAT0L,r0
795 
        lis     r3,BAT1@h
796 
        ori     r3,r3,BAT1@l
797 
        andc    r3,r3,r7        /* make unmapped address */
798 
        lwz     r0,0(r3)
799 
        mtspr   IBAT1U,r0
800 
        mtspr   DBAT1U,r0
801 
        lwz     r0,4(r3)
802 
        mtspr   IBAT1L,r0
803 
        mtspr   DBAT1L,r0
804 
/* this BAT mapping will cover all of kernel space */
805 
#ifdef NEWMM
806 
        lis     r3,BAT2@h
807 
        ori     r3,r3,BAT2@l
808 
#else
809 
        lis     r3,TMP_BAT2@h
810 
        ori     r3,r3,TMP_BAT2@l
811 
#endif
812 
        andc    r3,r3,r7        /* make unmapped address */
813 
        lwz     r0,0(r3)
814 
        mtspr   IBAT2U,r0
815 
        mtspr   DBAT2U,r0
816 
        lwz     r0,4(r3)
817 
        mtspr   IBAT2L,r0
818 
        mtspr   DBAT2L,r0
819 
#if 0
820 
        lis     r3,BAT3@h
821 
        ori     r3,r3,BAT3@l
822 
        andc    r3,r3,r7        /* make unmapped address */
823 
        lwz     r0,0(r3)
824 
        mtspr   IBAT3U,r0
825 
        mtspr   DBAT3U,r0
826 
        lwz     r0,4(r3)
827 
        mtspr   IBAT3L,r0
828 
        mtspr   DBAT3L,r0
829 
#endif
830 
/* Now we can turn on the MMU */
831 
        mfmsr   r3
832 
        ori     r3,r3,MSR_DR|MSR_IR
833 
        mtspr   SRR1,r3
834 
        lis     r3,10f@h
835 
        ori     r3,r3,10f@l
836 
        mtspr   SRR0,r3
837 
DO_RFI_TRACE_UNMAPPED(0xDEAD0000)
838 
        SYNC
839 
        rfi                             /* enables MMU */
840 
10:     bl      _EXTERN(MMU_init)       /* initialize MMU environment */
841 
DO_RFI_TRACE_MAPPED(0xDEAD0100)
842 
/* Withdraw BAT2->RAM mapping */
843 
        lis     r7,0xF000               /* To mask upper 4 bits */
844 
        lis     r3,20f@h
845 
        ori     r3,r3,20f@l
846 
        andc    r3,r3,r7        /* make unmapped address */
847 
        mtspr   SRR0,r3
848 
        mfmsr   r3
849 
        li      r4,MSR_DR|MSR_IR
850 
        andc    r3,r3,r4
851 
        mtspr   SRR1,r3
852 
        SYNC
853 
DO_RFI_TRACE_MAPPED(0xDEAD0200)
854 
        SYNC
855 
        rfi
856 
20:
857 
 
858 
DO_RFI_TRACE_UNMAPPED(0xDEAD0400)
859 
20:     lis     r3,BAT2@h
860 
        ori     r3,r3,BAT2@l
861 
        andc    r3,r3,r7        /* make unmapped address */
862 
        lwz     r0,0(r3)
863 
        mtspr   IBAT2U,r0
864 
        mtspr   DBAT2U,r0
865 
        lwz     r0,4(r3)
866 
        mtspr   IBAT2L,r0
867 
        mtspr   DBAT2L,r0
868 
/* Load up the kernel context */
869 
        lis     r2,init_task@h
870 
        ori     r2,r2,init_task@l
871 
        addi    r2,r2,TSS
872 
        andc    r2,r2,r7        /* make unmapped address */
873 
        SYNC                    /* Force all PTE updates to finish */
874 
        tlbia                   /* Clear all TLB entries */
875 
        lis     r3,_SDR1@h
876 
        ori     r3,r3,_SDR1@l
877 
        andc    r3,r3,r7        /* make unmapped address */
878 
        lwz     r3,0(r3)
879 
        mtspr   SDR1,r3
880 
        lwz     r0,MMU_SEG0(r2)
881 
        mtsr    SR0,r0
882 
        lwz     r0,MMU_SEG1(r2)
883 
        mtsr    SR1,r0
884 
        lwz     r0,MMU_SEG2(r2)
885 
        mtsr    SR2,r0
886 
        lwz     r0,MMU_SEG3(r2)
887 
        mtsr    SR3,r0
888 
        lwz     r0,MMU_SEG4(r2)
889 
        mtsr    SR4,r0
890 
        lwz     r0,MMU_SEG5(r2)
891 
        mtsr    SR5,r0
892 
        lwz     r0,MMU_SEG6(r2)
893 
        mtsr    SR6,r0
894 
        lwz     r0,MMU_SEG7(r2)
895 
        mtsr    SR7,r0
896 
        lwz     r0,MMU_SEG8(r2)
897 
        mtsr    SR8,r0
898 
        lwz     r0,MMU_SEG9(r2)
899 
        mtsr    SR9,r0
900 
        lwz     r0,MMU_SEG10(r2)
901 
        mtsr    SR10,r0
902 
        lwz     r0,MMU_SEG11(r2)
903 
        mtsr    SR11,r0
904 
        lwz     r0,MMU_SEG12(r2)
905 
        mtsr    SR12,r0
906 
        lwz     r0,MMU_SEG13(r2)
907 
        mtsr    SR13,r0
908 
        lwz     r0,MMU_SEG14(r2)
909 
        mtsr    SR14,r0
910 
        lwz     r0,MMU_SEG15(r2)
911 
        mtsr    SR15,r0
912 
/* Now turn on the MMU for real! */
913 
        mfmsr   r3
914 
        ori     r3,r3,MSR_DR|MSR_IR
915 
        mtspr   SRR1,r3
916 
        lis     r3,30f@h
917 
        ori     r3,r3,30f@l
918 
        mtspr   SRR0,r3
919 
DO_RFI_TRACE_UNMAPPED(0xDEAD0500)
920 
        SYNC
921 
        rfi                             /* enables MMU */
922 
30:
923 
/* Turn on L1 Data Cache */
924 
        mfspr   r3,HID0         /* Caches are controlled by this register */
925 
        ori     r4,r3,(HID0_ICE|HID0_ICFI)
926 
        ori     r3,r3,(HID0_ICE)
927 
        ori     r4,r4,(HID0_DCE|HID0_DCI)
928 
        ori     r3,r3,(HID0_DCE)
929 
        sync
930 
        mtspr   HID0,r4
931 
        mtspr   HID0,r3
932 
/* L1 cache enable */
933 
        mfspr   r2,PVR                  /* Check for 603/603e */
934 
        srwi    r2,r2,16
935 
        cmpi    0,r2,4                  /* 604 */
936 
        bne     40f
937 
        mfspr   r3,HID0                 /* Turn on 604 specific features */
938 
        ori     r3,r3,(HID0_SIED|HID0_BHTE)
939 
        mtspr   HID0,r3
940 
40:     b       _EXTERN(start_kernel)           /* call main code */
941 
        .long   0                # Illegal!
942 
 
943 
/*
944 
 * BeBox CPU #2 runs here
945 
 */
946 
Reset_BeBox_CPU1:
947 
        lis     r1,CPU1_stack@h
948 
        ori     r1,r1,CPU1_stack@l
949 
        li      r2,0x0FFF       /* Mask stack address down to page boundary */
950 
        andc    r1,r1,r2
951 
        subi    r1,r1,INT_FRAME_SIZE    /* Padding for first frame */
952 
        lis     r30,CPU1_trace@h
953 
        ori     r30,r30,CPU1_trace@l
954 
        andc    r30,r30,r7
955 
        li      r5,1
956 
        stw     r5,0(r30)
957 
        li      r2,0            /* TOC pointer for nanokernel */
958 
        li      r0,MSR_         /* Make sure FPU enabled */
959 
        mtmsr   r0
960 
/* Initialize BAT registers */
961 
        lis     r3,BAT0@h
962 
        ori     r3,r3,BAT0@l
963 
        andc    r3,r3,r7        /* make unmapped address */
964 
        lwz     r0,0(r3)
965 
        mtspr   IBAT0U,r0
966 
        mtspr   DBAT0U,r0
967 
        lwz     r0,4(r3)
968 
        mtspr   IBAT0L,r0
969 
        mtspr   DBAT0L,r0
970 
        lis     r3,BAT1@h
971 
        ori     r3,r3,BAT1@l
972 
        andc    r3,r3,r7        /* make unmapped address */
973 
        lwz     r0,0(r3)
974 
        mtspr   IBAT1U,r0
975 
        mtspr   DBAT1U,r0
976 
        lwz     r0,4(r3)
977 
        mtspr   IBAT1L,r0
978 
        mtspr   DBAT1L,r0
979 
        lis     r3,TMP_BAT2@h
980 
        ori     r3,r3,TMP_BAT2@l
981 
        andc    r3,r3,r7        /* make unmapped address */
982 
        lwz     r0,0(r3)
983 
        mtspr   IBAT2U,r0
984 
        mtspr   DBAT2U,r0
985 
        lwz     r0,4(r3)
986 
        mtspr   IBAT2L,r0
987 
        mtspr   DBAT2L,r0
988 
/* Now we can turn on the MMU */
989 
        mfmsr   r3
990 
        ori     r3,r3,MSR_DR|MSR_IR
991 
        mtspr   SRR1,r3
992 
        lis     r3,10f@h
993 
        ori     r3,r3,10f@l
994 
        mtspr   SRR0,r3
995 
        li      r5,2
996 
        stw     r5,0(r30)
997 
        SYNC
998 
        rfi                             /* enables MMU */
999 
10:
1000 
        lis     r30,CPU1_trace@h
1001 
        ori     r30,r30,CPU1_trace@l
1002 
        li      r5,3
1003 
        stw     r5,0(r30)
1004 
        bl      _EXTERN(BeBox_CPU1)
1005 
 
1006 
/*
1007 
 * Machine Check (Bus Errors, etc)
1008 
 */
1009 
MachineCheck:
1010 
        TRACE_TRAP(0x0200)
1011 
        SAVE_INT_REGS(0x0200)
1012 
        mr      r3,r1           /* Set pointer to saved regs */
1013 
        bl      _EXTERN(MachineCheckException)
1014 
        RETURN_FROM_INT(0x0200)
1015 
 
1016 
/*
1017 
 * Data Access exception
1018 
 */
1019 
DataAccess:
1020 
/*      TRACE_TRAP(0x0300) */
1021 
        SAVE_INT_REGS(0x0300)
1022 
        SAVE_PAGE_FAULT_REGS(0x0300)
1023 
        BUMP(__Data_Page_Faults)
1024 
        mr      r3,r1           /* Set pointer to saved regs */
1025 
        bl      _EXTERN(DataAccessException)
1026 
#if 0
1027 
        bl      _EXTERN(flush_instruction_cache)
1028 
#endif
1029 
        RETURN_FROM_INT(0x0300)
1030 
 
1031 
/*
1032 
 * Instruction Access Exception
1033 
 */
1034 
InstructionAccess:
1035 
/*      TRACE_TRAP(0x0400) */
1036 
        SAVE_INT_REGS(0x0400)
1037 
        SAVE_PAGE_FAULT_REGS(0x0400)
1038 
        BUMP(__Instruction_Page_Faults)
1039 
        mr      r3,r1           /* Set pointer to saved regs */
1040 
        bl      _EXTERN(InstructionAccessException)
1041 
#if 0
1042 
        bl      _EXTERN(flush_instruction_cache)
1043 
#endif
1044 
        RETURN_FROM_INT(0x0400)
1045 
 
1046 
/*
1047 
 * Hardware Interrupt
1048 
 */
1049 
HardwareInterrupt:
1050 
        SAVE_INT_REGS(0x0500)
1051 
        BUMP(__Hardware_Interrupts)
1052 
        mr      r3,r1           /* Set pointer to saved regs */
1053 
        bl      _EXTERN(handle_IRQ)
1054 
        RETURN_FROM_INT(0x0500)
1055 
 
1056 
/*
1057 
 * Alignment
1058 
 */
1059 
Alignment:
1060 
        TRACE_TRAP(0x0600)
1061 
        SAVE_INT_REGS(0x0600)
1062 
        mr      r3,r1           /* Set pointer to saved regs */
1063 
        bl      _EXTERN(AlignmentException)
1064 
        RETURN_FROM_INT(0x0600)
1065 
 
1066 
/*
1067 
 * Illegal instruction
1068 
 */
1069 
ProgramCheck:
1070 
        TRACE_TRAP(0x0700)
1071 
        SAVE_INT_REGS(0x0700)
1072 
        mr      r3,r1           /* Set pointer to saved regs */
1073 
        bl      _EXTERN(ProgramCheckException)
1074 
        RETURN_FROM_INT(0x0700)
1075 
 
1076 
/*
1077 
 * Single Step Exception
1078 
 */
1079 
SingleStep:
1080 
        SAVE_INT_REGS(0x0D00)
1081 
        SAVE_PAGE_FAULT_REGS(0x0D00)
1082 
        mr      r3,r1           /* Set pointer to saved regs */
1083 
        bl      _EXTERN(SingleStepException)
1084 
#if 0
1085 
        bl      _EXTERN(flush_instruction_cache)
1086 
#endif
1087 
        RETURN_FROM_INT(0x0D00)
1088 
 
1089 
/*
1090 
 * Floating point [not available, etc]
1091 
 */
1092 
FloatingPointCheck:
1093 
        TRACE_TRAP(0x0800)
1094 
        SAVE_INT_REGS(0x0800)
1095 
        mr      r3,r1           /* Set pointer to saved regs */
1096 
        bl      _EXTERN(FloatingPointCheckException)
1097 
        RETURN_FROM_INT(0x0200)
1098 
 
1099 
/*
1100 
 * System Call exception
1101 
 */
1102 
SystemCall:
1103 
/*      TRACE_TRAP(0x0C00) */
1104 
        SAVE_INT_REGS(0x0C00)
1105 
        lwz     r2,_CCR(r1)     /* Clear SO bit in CR */
1106 
        lis     r9,0x1000
1107 
        andc    r2,r2,r9
1108 
        stw     r2,_CCR(r1)
1109 
        cmpi    0,r0,0x7777     /* Special case for 'sys_sigreturn' */
1110 
        bne+    10f
1111 
        mr      r3,r1
1112 
        bl      _EXTERN(sys_sigreturn)
1113 
        cmpi    0,r3,0          /* Check for restarted system call */
1114 
        bge     99f
1115 
        b       20f
1116 
10:     lis     r2,current_set@ha
1117 
        lwz     r2,current_set@l(r2)
1118 
        lwz     r2,TASK_FLAGS(r2)
1119 
        andi.   r2,r2,PF_TRACESYS
1120 
        bne     50f
1121 
        lis     r2,sys_call_table@h
1122 
        ori     r2,r2,sys_call_table@l
1123 
        slwi    r0,r0,2
1124 
        lwzx    r2,r2,r0        /* Fetch system call handler [ptr] */
1125 
        mtlr    r2
1126 
        mr      r9,r1
1127 
        blrl                    /* Call handler */
1128 
20:     stw     r3,RESULT(r1)   /* Save result */
1129 
        cmpi    0,r3,0
1130 
        bge     30f
1131 
        neg     r3,r3
1132 
        cmpi    0,r3,ERESTARTNOHAND
1133 
        bne     22f
1134 
        li      r3,EINTR
1135 
22:     lwz     r2,_CCR(r1)     /* Set SO bit in CR */
1136 
        oris    r2,r2,0x1000
1137 
        stw     r2,_CCR(r1)
1138 
30:     stw     r3,GPR3(r1)     /* Update return value */
1139 
#if 0
1140 
        mr      r3,r1
1141 
        bl      _EXTERN(trace_syscall)
1142 
#endif
1143 
        b       99f
1144 
/* Traced system call support */
1145 
50:     bl      _EXTERN(syscall_trace)
1146 
        lwz     r0,GPR0(r1)     /* Restore original registers */
1147 
        lwz     r3,GPR3(r1)
1148 
        lwz     r4,GPR4(r1)
1149 
        lwz     r5,GPR5(r1)
1150 
        lwz     r6,GPR6(r1)
1151 
        lwz     r7,GPR7(r1)
1152 
        lwz     r8,GPR8(r1)
1153 
        lwz     r9,GPR9(r1)
1154 
        lis     r2,sys_call_table@h
1155 
        ori     r2,r2,sys_call_table@l
1156 
        slwi    r0,r0,2
1157 
        lwzx    r2,r2,r0        /* Fetch system call handler [ptr] */
1158 
        mtlr    r2
1159 
        mr      r9,r1
1160 
        blrl                    /* Call handler */
1161 
        stw     r3,RESULT(r1)   /* Save result */
1162 
        cmpi    0,r3,0
1163 
        bge     60f
1164 
        neg     r3,r3
1165 
        cmpi    0,r3,ERESTARTNOHAND
1166 
        bne     52f
1167 
        li      r3,EINTR
1168 
52:     lwz     r2,_CCR(r1)     /* Set SO bit in CR */
1169 
        oris    r2,r2,0x1000
1170 
        stw     r2,_CCR(r1)
1171 
60:     stw     r3,GPR3(r1)     /* Update return value */
1172 
        bl      _EXTERN(syscall_trace)
1173 
99:
1174 
#if 0 /* This isn't needed here - already in RETURN_FROM_INT */
1175 
        lis     r2,kernel_pages_are_copyback@ha
1176 
        lwz     r2,kernel_pages_are_copyback@l(r2)
1177 
        cmpi    0,r2,0
1178 
        beq     00f
1179 
        bl      _EXTERN(flush_instruction_cache)        /* Ensure cache coherency */
1180 
00:
1181 
#endif
1182 
        RETURN_FROM_INT(0x0C00)
1183 
 
1184 
/*
1185 
 * Handle TLB miss for instruction
1186 
 */
1187 
InstructionTLBMiss:
1188 
        BUMP_UNMAPPED(__Instruction_TLB_Misses)
1189 
#ifdef DO_TLB_TRACE
1190 
        lis     r1,_TLB_ptr@h
1191 
        ori     r1,r1,_TLB_ptr@l
1192 
        lis     r2,0xF000
1193 
        andc    r1,r1,r2
1194 
        lwz     r1,0(r1)
1195 
        andc    r1,r1,r2
1196 
        subi    r1,r1,4
1197 
        lis     r2,0xBEBE
1198 
        ori     r2,r2,0x0100
1199 
        stwu    r2,4(r1)
1200 
        mfspr   r2,SRR0
1201 
        stwu    r2,4(r1)
1202 
        mfspr   r2,SRR1
1203 
        stwu    r2,4(r1)
1204 
        mfspr   r2,HASH1
1205 
        stwu    r2,4(r1)
1206 
        mfspr   r2,HASH2
1207 
        stwu    r2,4(r1)
1208 
        mfspr   r2,ICMP
1209 
        stwu    r2,4(r1)
1210 
        mfspr   r2,IMISS
1211 
        stwu    r2,4(r1)
1212 
        addi    r1,r1,4+(1*4)
1213 
        lis     r3,_TLB_ptr@h
1214 
        ori     r3,r3,_TLB_ptr@l
1215 
        lis     r2,0xF000
1216 
        andc    r3,r3,r2
1217 
        stw     r1,0(r3)
1218 
#endif
1219 
        mfctr   r0              /* Need to save this - CTR can't be touched! */
1220 
        mfspr   r2,HASH1        /* Get PTE pointer */
1221 
        mfspr   r3,ICMP         /* Partial item compare value */
1222 
00:     li      r1,8            /* 8 items / bucket */
1223 
        mtctr   r1
1224 
        subi    r2,r2,8         /* Preset pointer */
1225 
10:     lwzu    r1,8(r2)        /* Get next PTE */
1226 
        cmp     0,r1,r3         /* Found entry yet? */
1227 
        bdne    10b             /* Jump back if not, until CTR==0 */
1228 
        bne     30f             /* Try secondary hash if CTR==0 */
1229 
        lwz     r1,4(r2)        /* Get second word of entry */
1230 
#if 0
1231 
        andi.   r3,r1,0x08      /* Check guard bit - invalid access if set */
1232 
        bne     InstructionFetchError
1233 
#endif
1234 
        andi.   r3,r1,0x100     /* Check R bit (referenced) */
1235 
        bne     20f             /* If set, all done */
1236 
        ori     r1,r1,0x100     /* Set bit */
1237 
        stw     r1,4(r2)        /* Update memory image */
1238 
20:     mtctr   r0              /* Restore CTR */
1239 
        mfspr   r3,SRR1         /* Need to restore CR0 */
1240 
        mtcrf   0x80,r3
1241 
        mfspr   r0,IMISS        /* Set to update TLB */
1242 
        mtspr   RPA,r1
1243 
        tlbli   r0
1244 
#if 0
1245 
        SYNC
1246 
#endif
1247 
        rfi                     /* All done */
1248 
/* Secondary hash */
1249 
30:     andi.   r1,r3,0x40      /* Already doing secondary hash? */
1250 
        bne     InstructionAddressInvalid /* Yes - item not in hash table */
1251 
        mfspr   r2,HASH2        /* Get hash table pointer */
1252 
        ori     r3,r3,0x40      /* Set secondary hash */
1253 
        b       00b                     /* Try lookup again */
1254 
 
1255 
/*
1256 
 * Handle TLB miss for DATA Load operation
1257 
 */
1258 
DataLoadTLBMiss:
1259 
        BUMP_UNMAPPED(__DataLoad_TLB_Misses)
1260 
#ifdef DO_TLB_TRACE
1261 
        lis     r1,_TLB_ptr@h
1262 
        ori     r1,r1,_TLB_ptr@l
1263 
        lis     r2,0xF000
1264 
        andc    r1,r1,r2
1265 
        lwz     r1,0(r1)
1266 
        andc    r1,r1,r2
1267 
        subi    r1,r1,4
1268 
        lis     r2,0xBEBE
1269 
        ori     r2,r2,0x0200
1270 
        stwu    r2,4(r1)
1271 
        mfspr   r2,SRR0
1272 
        stwu    r2,4(r1)
1273 
        mfspr   r2,SRR1
1274 
        stwu    r2,4(r1)
1275 
        mfspr   r2,HASH1
1276 
        stwu    r2,4(r1)
1277 
        mfspr   r2,HASH2
1278 
        stwu    r2,4(r1)
1279 
        mfspr   r2,DCMP
1280 
        stwu    r2,4(r1)
1281 
        mfspr   r2,DMISS
1282 
        stwu    r2,4(r1)
1283 
        addi    r1,r1,4+(1*4)
1284 
        lis     r3,_TLB_ptr@h
1285 
        ori     r3,r3,_TLB_ptr@l
1286 
        lis     r2,0xF000
1287 
        andc    r3,r3,r2
1288 
        stw     r1,0(r3)
1289 
#endif
1290 
        mfctr   r0              /* Need to save this - CTR can't be touched! */
1291 
        mfspr   r2,HASH1        /* Get PTE pointer */
1292 
        mfspr   r3,DCMP         /* Partial item compare value */
1293 
00:     li      r1,8            /* 8 items / bucket */
1294 
        mtctr   r1
1295 
        subi    r2,r2,8         /* Preset pointer */
1296 
10:     lwzu    r1,8(r2)        /* Get next PTE */
1297 
        cmp     0,r1,r3         /* Found entry yet? */
1298 
        bdne    10b             /* Jump back if not, until CTR==0 */
1299 
        bne     30f             /* Try secondary hash if CTR==0 */
1300 
        lwz     r1,4(r2)        /* Get second word of entry */
1301 
        andi.   r3,r1,0x100     /* Check R bit (referenced) */
1302 
        ori     r1,r1,0x100     /* Set bit */
1303 
        bne     20f             /* If set, all done */
1304 
        stw     r1,4(r2)        /* Update memory image */
1305 
20:     mtctr   r0              /* Restore CTR */
1306 
        mfspr   r3,SRR1         /* Need to restore CR0 */
1307 
        mtcrf   0x80,r3
1308 
        mfspr   r0,DMISS        /* Set to update TLB */
1309 
        mtspr   RPA,r1
1310 
/*      SYNC() */
1311 
        tlbld   r0
1312 
#if 0
1313 
        SYNC
1314 
#endif
1315 
        rfi                     /* All done */
1316 
/* Secondary hash */
1317 
30:     andi.   r1,r3,0x40      /* Already doing secondary hash? */
1318 
        bne     DataAddressInvalid /* Yes - item not in hash table */
1319 
        mfspr   r2,HASH2        /* Get hash table pointer */
1320 
        ori     r3,r3,0x40      /* Set secondary hash */
1321 
        b       00b                     /* Try lookup again */
1322 
 
1323 
/*
1324 
 * Handle TLB miss for DATA STORE
1325 
 */
1326 
DataStoreTLBMiss:
1327 
        BUMP_UNMAPPED(__DataStore_TLB_Misses)
1328 
#ifdef DO_TLB_TRACE
1329 
        lis     r1,_TLB_ptr@h
1330 
        ori     r1,r1,_TLB_ptr@l
1331 
        lis     r2,0xF000
1332 
        andc    r1,r1,r2
1333 
        lwz     r1,0(r1)
1334 
        andc    r1,r1,r2
1335 
        subi    r1,r1,4
1336 
        lis     r2,0xBEBE
1337 
        ori     r2,r2,0x0300
1338 
        stwu    r2,4(r1)
1339 
        mfspr   r2,SRR0
1340 
        stwu    r2,4(r1)
1341 
        mfspr   r2,SRR1
1342 
        stwu    r2,4(r1)
1343 
        mfspr   r2,HASH1
1344 
        stwu    r2,4(r1)
1345 
        mfspr   r2,HASH2
1346 
        stwu    r2,4(r1)
1347 
        mfspr   r2,DCMP
1348 
        stwu    r2,4(r1)
1349 
        mfspr   r2,DMISS
1350 
        stwu    r2,4(r1)
1351 
        addi    r1,r1,4+(1*4)
1352 
        lis     r3,_TLB_ptr@h
1353 
        ori     r3,r3,_TLB_ptr@l
1354 
        lis     r2,0xF000
1355 
        andc    r3,r3,r2
1356 
        stw     r1,0(r3)
1357 
#endif
1358 
        mfctr   r0              /* Need to save this - CTR can't be touched! */
1359 
        mfspr   r2,HASH1        /* Get PTE pointer */
1360 
        mfspr   r3,DCMP         /* Partial item compare value */
1361 
00:     li      r1,8            /* 8 items / bucket */
1362 
        mtctr   r1
1363 
        subi    r2,r2,8         /* Preset pointer */
1364 
10:     lwzu    r1,8(r2)        /* Get next PTE */
1365 
        cmp     0,r1,r3         /* Found entry yet? */
1366 
        bdne    10b             /* Jump back if not, until CTR==0 */
1367 
        bne     30f             /* Try secondary hash if CTR==0 */
1368 
        lwz     r1,4(r2)        /* Get second word of entry */
1369 
        andi.   r3,r1,0x80      /* Check C bit (changed) */
1370 
#if 0 /* Note: no validation */
1371 
        beq     40f             /* If not set (first time) validate access */
1372 
#else
1373 
        ori     r1,r1,0x180     /* Set changed, accessed */
1374 
        bne     20f
1375 
        stw     r1,4(r2)
1376 
#endif
1377 
20:     mtctr   r0              /* Restore CTR */
1378 
        mfspr   r3,SRR1         /* Need to restore CR0 */
1379 
        mtcrf   0x80,r3
1380 
        mfspr   r0,DMISS        /* Set to update TLB */
1381 
        mtspr   RPA,r1
1382 
        tlbld   r0
1383 
#if 0
1384 
        SYNC
1385 
#endif
1386 
        rfi                     /* All done */
1387 
/* Secondary hash */
1388 
30:     andi.   r1,r3,0x40      /* Already doing secondary hash? */
1389 
        bne     DataAddressInvalid /* Yes - item not in hash table */
1390 
        mfspr   r2,HASH2        /* Get hash table pointer */
1391 
        ori     r3,r3,0x40      /* Set secondary hash */
1392 
        b       00b                     /* Try lookup again */
1393 
/* PTE found - validate access */
1394 
40:     rlwinm. r3,r1,30,0,1    /* Extract PP bits */
1395 
        bge-    50f             /* Jump if PP=0,1 */
1396 
        andi.   r3,r1,1
1397 
        beq+    70f             /* Access OK */
1398 
        b       WriteProtectError       /* Not OK - fail! */
1399 
50:     mfspr   r3,SRR1         /* Check privilege */
1400 
        andi.   r3,r3,MSR_PR
1401 
        beq+    60f             /* Jump if supervisor mode */
1402 
        mfspr   r3,DMISS        /* Get address */
1403 
        mfsrin  r3,r3           /* Get segment register */
1404 
        andis.  r3,r3,0x2000    /* If Kp==0, OK */
1405 
        beq+    70f
1406 
        b       WriteProtectError       /* Bad access */
1407 
60:     mfspr   r3,DMISS        /* Get address */
1408 
        mfsrin  r3,r3           /* Get segment register */
1409 
        andis.  r3,r3,0x4000    /* If Ks==0, OK */
1410 
        beq+    70f
1411 
        b       WriteProtectError       /* Bad access */
1412 
70:     ori     r1,r1,0x180     /* Set changed, accessed */
1413 
        stw     r1,4(r2)        /* Update PTE in memory */
1414 
        b       20b
1415 
 
1416 
/*
1417 
 * These routines are error paths/continuations of the exception
1418 
 * handlers above.  They are placed here to avoid the problems
1419 
 * of only 0x100 bytes per exception handler.
1420 
 */
1421 
 
1422 
/* Invalid address */
1423 
InstructionAddressInvalid:
1424 
        mfspr   r3,SRR1
1425 
        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
1426 
        addis   r1,r1,0x4000    /* Set bit 1 -> PTE not found */
1427 
        b       10f
1428 
 
1429 
/* Fetch from guarded or no-access page */
1430 
InstructionFetchError:
1431 
        mfspr   r3,SRR1
1432 
        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
1433 
        addis   r1,r1,0x0800    /* Set bit 4 -> protection error */
1434 
10:     mtspr   DSISR,r1
1435 
        mtctr   r0              /* Restore CTR */
1436 
        andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
1437 
        mtspr   SRR1,r2
1438 
        mfspr   r1,IMISS        /* Get failing address */
1439 
        rlwinm. r2,r2,0,31,31   /* Check for little endian access */
1440 
        beq     20f             /* Jump if big endian */
1441 
        xori    r1,r1,3
1442 
20:     mtspr   DAR,r1          /* Set fault address */
1443 
        mfmsr   r0              /* Restore "normal" registers */
1444 
        xoris   r0,r0,MSR_TGPR>>16
1445 
        mtcrf   0x80,r3         /* Restore CR0 */
1446 
        ori     r0,r0,MSR_FP    /* Need to keep FP enabled */
1447 
        sync                    /* Some chip revs have problems here... */
1448 
        mtmsr   r0
1449 
        b       InstructionAccess
1450 
 
1451 
/* Invalid address */
1452 
DataAddressInvalid:
1453 
        mfspr   r3,SRR1
1454 
        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
1455 
        addis   r1,r1,0x4000    /* Set bit 1 -> PTE not found */
1456 
        b       10f
1457 
 
1458 
/* Write to read-only space */
1459 
WriteProtectError:
1460 
        mfspr   r3,SRR1
1461 
        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
1462 
        addis   r1,r1,0x0800    /* Set bit 4 -> protection error */
1463 
10:     mtspr   DSISR,r1
1464 
        mtctr   r0              /* Restore CTR */
1465 
        andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
1466 
        mtspr   SRR1,r2
1467 
        mfspr   r1,DMISS        /* Get failing address */
1468 
        rlwinm. r2,r2,0,31,31   /* Check for little endian access */
1469 
        beq     20f             /* Jump if big endian */
1470 
        xori    r1,r1,3
1471 
20:     mtspr   DAR,r1          /* Set fault address */
1472 
        mfmsr   r0              /* Restore "normal" registers */
1473 
        xoris   r0,r0,MSR_TGPR>>16
1474 
        mtcrf   0x80,r3         /* Restore CR0 */
1475 
        ori     r0,r0,MSR_FP    /* Need to keep FP enabled */
1476 
        sync                    /* Some chip revs have problems here... */
1477 
        mtmsr   r0
1478 
        b       DataAccess
1479 
 
1480 
/*
1481 
 * Flush instruction cache
1482 
 * *** I'm really paranoid here!
1483 
 */
1484 
_GLOBAL(flush_instruction_cache)
1485 
        mflr    r5
1486 
        bl      _EXTERN(flush_data_cache)
1487 
        mfspr   r3,HID0 /* Caches are controlled by this register */
1488 
        li      r4,0
1489 
        ori     r4,r4,(HID0_ICE|HID0_ICFI)
1490 
        or      r3,r3,r4        /* Need to enable+invalidate to clear */
1491 
        mtspr   HID0,r3
1492 
        andc    r3,r3,r4
1493 
        ori     r3,r3,HID0_ICE  /* Enable cache */
1494 
        mtspr   HID0,r3
1495 
        mtlr    r5
1496 
        blr
1497 
 
1498 
/*
1499 
 * Flush data cache
1500 
 * *** I'm really paranoid here!
1501 
 */
1502 
_GLOBAL(flush_data_cache)
1503 
        BUMP(__Cache_Flushes)
1504 
        lis     r3,cache_is_copyback@ha
1505 
        lwz     r3,cache_is_copyback@l(r3)
1506 
        cmpi    0,r3,0
1507 
        beq     10f
1508 
/* When DATA CACHE is copy-back */
1509 
        lis     r3,cache_flush_buffer@h
1510 
        ori     r3,r3,cache_flush_buffer@l
1511 
        li      r4,NUM_CACHE_LINES
1512 
        mtctr   r4
1513 
00:     dcbz    0,r3                    /* Flush cache line with minimal BUS traffic */
1514 
        addi    r3,r3,CACHE_LINE_SIZE   /* Next line, please */
1515 
        bdnz    00b
1516 
10:     blr
1517 
 
1518 
/*
1519 
 * Flush a particular page from the DATA cache
1520 
 * Note: this is necessary because the instruction cache does *not*
1521 
 * snoop from the data cache.
1522 
 *      void flush_page(void *page)
1523 
 */
1524 
_GLOBAL(flush_page)
1525 
        li      r4,0x0FFF
1526 
        andc    r3,r3,r4                /* Get page base address */
1527 
        li      r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
1528 
        mtctr   r4
1529 
00:     dcbf    0,r3                    /* Clear line */
1530 
        icbi    0,r3
1531 
        addi    r3,r3,CACHE_LINE_SIZE
1532 
        bdnz    00b
1533 
        blr
1534 
 
1535 
/*
1536 
 * This routine switches between two different tasks.  The process
1537 
 * state of one is saved on its kernel stack.  Then the state
1538 
 * of the other is restored from its kernel stack.  The memory
1539 
 * management hardware is updated to the second process's state.
1540 
 * Finally, we can return to the second process, via the 'return'.
1541 
 *
1542 
 * Note: there are two ways to get to the "going out" portion
1543 
 * of this code; either by coming in via the entry (_switch)
1544 
 * or via "fork" which must set up an environment equivalent
1545 
 * to the "_switch" path.  If you change this (or in particular, the
1546 
 * SAVE_REGS macro), you'll have to change the fork code also.
1547 
 *
1548 
 * The code which creates the new task context is in 'copy_thread'
1549 
 * in arch/ppc/kernel/process.c
1550 
 */
1551 
_GLOBAL(_switch)
1552 
        mtspr   SPR0,r1         /* SAVE_REGS prologue */
1553 
        mtspr   SPR1,r2
1554 
        mflr    r2              /* Return to switch caller */
1555 
        mtspr   SPR2,r2
1556 
        mfmsr   r2
1557 
        mtspr   SPR3,r2
1558 
        SAVE_REGS(0x0FF0)
1559 
        SYNC()
1560 
        stw     r1,KSP(r3)      /* Set old stack pointer */
1561 
        BUMP(__Context_Switches)
1562 
        lwz     r1,KSP(r4)      /* Load new stack pointer */
1563 
        CHECK_STACK()
1564 
        lwz     r0,MMU_SEG0(r4)
1565 
        mtsr    SR0,r0
1566 
        lwz     r0,MMU_SEG1(r4)
1567 
        mtsr    SR1,r0
1568 
        lwz     r0,MMU_SEG2(r4)
1569 
        mtsr    SR2,r0
1570 
        lwz     r0,MMU_SEG3(r4)
1571 
        mtsr    SR3,r0
1572 
        lwz     r0,MMU_SEG4(r4)
1573 
        mtsr    SR4,r0
1574 
        lwz     r0,MMU_SEG5(r4)
1575 
        mtsr    SR5,r0
1576 
        lwz     r0,MMU_SEG6(r4)
1577 
        mtsr    SR6,r0
1578 
        lwz     r0,MMU_SEG7(r4)
1579 
        mtsr    SR7,r0
1580 
        lwz     r0,MMU_SEG8(r4)
1581 
        mtsr    SR8,r0
1582 
        lwz     r0,MMU_SEG9(r4)
1583 
        mtsr    SR9,r0
1584 
        lwz     r0,MMU_SEG10(r4)
1585 
        mtsr    SR10,r0
1586 
        lwz     r0,MMU_SEG11(r4)
1587 
        mtsr    SR11,r0
1588 
        lwz     r0,MMU_SEG12(r4)
1589 
        mtsr    SR12,r0
1590 
        lwz     r0,MMU_SEG13(r4)
1591 
        mtsr    SR13,r0
1592 
        lwz     r0,MMU_SEG14(r4)
1593 
        mtsr    SR14,r0
1594 
        lwz     r0,MMU_SEG15(r4)
1595 
        mtsr    SR15,r0
1596 
        tlbia                           /* Invalidate entire TLB */
1597 
        BUMP(__TLBIAs)
1598 
        bl      _EXTERN(flush_instruction_cache)
1599 
#ifdef TLB_STATS
1600 
/* TEMP */
1601 
        lis     r2,DataLoadTLB_trace_ptr@h
1602 
        ori     r2,r2,DataLoadTLB_trace_ptr@l
1603 
        lis     r3,0x9000
1604 
        lwz     r4,0(r2)
1605 
        or      r4,r4,r3
1606 
        li      r0,0
1607 
        stw     r0,0(r4)
1608 
        stw     r0,4(r4)
1609 
        stw     r0,8(r4)
1610 
        stw     r0,12(r4)
1611 
        addi    r4,r4,4
1612 
        cmpl    0,r4,r2
1613 
        blt     00f
1614 
        lis     r4,DataLoadTLB_trace_buf@h
1615 
        ori     r4,r4,DataLoadTLB_trace_buf@l
1616 
00:     stw     r4,0(r2)
1617 
/* TEMP */
1618 
#endif
1619 
#if 0
1620 
        lwz     r2,_NIP(r1)     /* Force TLB/MMU hit */
1621 
        lwz     r2,0(r2)
1622 
#endif
1623 
        RETURN_FROM_INT(0xF000)
1624 
 
1625 
 
1626 
/*
1627 
 * This routine is just here to keep GCC happy - sigh...
1628 
 */
1629 
_GLOBAL(__main)
1630 
        blr
1631 
 
1632 
#ifdef DO_TRAP_TRACE
1633 
check_trace:
1634 
        sync                            /* Force all writes out */
1635 
        lwz     r2,-8(r1)
1636 
        andi.   r2,r2,MSR_PR
1637 
        bne     99f
1638 
        lwz     r2,-32(r1)
1639 
        lwz     r3,-16(r1)
1640 
        cmp     0,r2,r3
1641 
        bne     99f
1642 
        andi.   r2,r2,0x7FFF
1643 
        cmpi    0,r2,0x0C00
1644 
        bge     99f
1645 
        lwz     r2,-32+4(r1)
1646 
        lwz     r3,-16+4(r1)
1647 
        cmp     0,r2,r3
1648 
        bne     99f
1649 
        lwz     r2,-32+8(r1)
1650 
        lwz     r3,-16+8(r1)
1651 
        cmp     0,r2,r3
1652 
        bne     99f
1653 
        lwz     r2,-32(r1)
1654 
        lwz     r3,-16(r1)
1655 
        cmp     0,r2,r3
1656 
        bne     99f
1657 
        andi.   r2,r2,0x7FFF
1658 
        cmpi    0,r2,0x0600
1659 
        beq     00f
1660 
        lwz     r2,-32+12(r1)
1661 
        lwz     r3,-16+12(r1)
1662 
        cmp     0,r2,r3
1663 
        bne     99f
1664 
00:     li      r2,0x7653
1665 
        stw     r2,0(r1)
1666 
        b       00b
1667 
99:     blr
1668 
#endif
1669 
 
1670 
        .data
1671 
        .globl  sdata
1672 
sdata:
1673 
        .space  2*4096
1674 
sys_stack:
1675 
        .space  2*4096
1676 
CPU1_stack:
1677 
 
1678 
        .globl  empty_zero_page
1679 
empty_zero_page:
1680 
        .space  4096
1681 
 
1682 
        .globl  swapper_pg_dir
1683 
swapper_pg_dir:
1684 
        .space  4096
1685 
 
1686 
/*
1687 
 * This space gets a copy of optional info passed to us by the bootstrap
1688 
 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1689 
 */
1690 
        .globl  cmd_line
1691 
cmd_line:
1692 
        .space  512
1693 
 
1694 
#ifdef STATS
1695 
/*
1696 
 * Miscellaneous statistics - gathered just for performance info
1697 
 */
1698 
 
1699 
        .globl  _INTR_stats
1700 
_INTR_stats:
1701 
__Instruction_TLB_Misses:
1702 
        .long   0,0     /* Instruction TLB misses */
1703 
__DataLoad_TLB_Misses:
1704 
        .long   0,0     /* Data [load] TLB misses */
1705 
__DataStore_TLB_Misses:
1706 
        .long   0,0     /* Data [store] TLB misses */
1707 
__Instruction_Page_Faults:
1708 
        .long   0,0     /* Instruction page faults */
1709 
__Data_Page_Faults:
1710 
        .long   0,0     /* Data page faults */
1711 
__Cache_Flushes:
1712 
        .long   0,0     /* Explicit cache flushes */
1713 
__Context_Switches:
1714 
        .long   0,0     /* Context switches */
1715 
__Hardware_Interrupts:
1716 
        .long   0,0     /* I/O interrupts (disk, timer, etc) */
1717 
        .globl  __TLBIAs
1718 
__TLBIAs:
1719 
        .long   0,0     /* TLB cache forceably flushed */
1720 
        .globl  __TLBIEs
1721 
__TLBIEs:
1722 
        .long   0,0     /* Specific TLB entry flushed */
1723 
#endif
1724 
 
1725 
/*
1726 
 * This location is used to break any outstanding "lock"s when
1727 
 * changing contexts.
1728 
 */
1729 
_break_lwarx:   .long   0
1730 
 
1731 
/*
1732 
 * Various trace buffers
1733 
 */
1734 
#ifdef DO_TRAP_TRACE
1735 
        .data
1736 
_TRAP_TRACE: .space     32*1024
1737 
_TRAP_ptr:   .long      _TRAP_TRACE
1738 
        .text
1739 
#endif
1740 
 
1741 
#ifdef DO_TLB_TRACE
1742 
        .data
1743 
_TLB_TRACE: .space      128*1024
1744 
_TLB_ptr:   .long       _TLB_TRACE
1745 
        .text
1746 
#endif
1747 
 
1748 
#ifdef DO_RFI_TRACE
1749 
        .data
1750 
_RFI_DATA: .space       128*1024
1751 
_RFI_ptr:  .long        _RFI_DATA
1752 
        .text
1753 
#endif
1754 
 

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