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doru |
-- <File header>
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- Version
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-- 0.32
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-- Date
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-- 2002 August 07
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- <File info>
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-- This tests pAVR's Register File.
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-- The following tests are done:
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-- - read all ports, one at a time
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-- - read port 1 (RFRD1)
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-- - read port 2 (RFRD2)
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-- - write port (RFWR)
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-- - write pointer register X (RFXWR)
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-- - write pointer register Y (RFYWR)
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-- - write pointer register Z (RFZWR)
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-- - combined RFRD1, RFRD2, RFWR
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-- They should work simultaneousely.
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-- - combined RFXWR, RFYWR, RFZWR
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-- They should work simultaneousely.
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-- - combined RFRD1, RFRD2, RFWR, RFXWR, RFYWR, RFZWR
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-- That is, all RF ports are accessed simultaneousely. They should work do
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-- their job.
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-- However, note that the pointer registers are accessible for writting by
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-- their own ports but also by the RF write port. Writing them via pointer
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-- register write ports overwrites writing via general write port.
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-- Even though concurrent writing could happen in a perfectly legal AVR
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-- implementation, AVR's behavior is unpredictible (what write port has
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-- priority). We have chosen for pAVR the priority as mentioned above.
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-- </File info>
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-- <File body>
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.std_util.all;
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use work.pavr_util.all;
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use work.pavr_constants.all;
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entity test_pavr_rf is
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end;
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architecture test_pavr_rf_arch of test_pavr_rf is
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signal clk, res, syncres: std_logic;
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-- Clock counter
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signal cnt: std_logic_vector(7 downto 0);
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-- RF read port 1
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signal pavr_rf_rd1_addr : std_logic_vector(4 downto 0);
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signal pavr_rf_rd1_rd : std_logic;
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signal pavr_rf_rd1_do : std_logic_vector(7 downto 0);
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-- RF read port 2
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signal pavr_rf_rd2_addr : std_logic_vector(4 downto 0);
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signal pavr_rf_rd2_rd : std_logic;
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signal pavr_rf_rd2_do : std_logic_vector(7 downto 0);
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-- RF write port
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signal pavr_rf_wr_addr : std_logic_vector(4 downto 0);
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signal pavr_rf_wr_wr : std_logic;
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signal pavr_rf_wr_di : std_logic_vector(7 downto 0);
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-- X pointer port
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signal pavr_rf_x : std_logic_vector(15 downto 0);
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signal pavr_rf_x_wr : std_logic;
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signal pavr_rf_x_di : std_logic_vector(15 downto 0);
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-- Y pointer port
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signal pavr_rf_y : std_logic_vector(15 downto 0);
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signal pavr_rf_y_wr : std_logic;
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signal pavr_rf_y_di : std_logic_vector(15 downto 0);
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-- Z pointer port
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signal pavr_rf_z : std_logic_vector(15 downto 0);
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signal pavr_rf_z_wr : std_logic;
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signal pavr_rf_z_di : std_logic_vector(15 downto 0);
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-- Declare the Register File.
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component pavr_rf
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port(
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pavr_rf_clk: in std_logic;
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pavr_rf_res: in std_logic;
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pavr_rf_syncres: in std_logic;
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-- Read port #1
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pavr_rf_rd1_addr: in std_logic_vector(4 downto 0);
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pavr_rf_rd1_rd: in std_logic;
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pavr_rf_rd1_do: out std_logic_vector(7 downto 0);
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-- Read port #2
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pavr_rf_rd2_addr: in std_logic_vector(4 downto 0);
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pavr_rf_rd2_rd: in std_logic;
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pavr_rf_rd2_do: out std_logic_vector(7 downto 0);
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-- Write port
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pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
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pavr_rf_wr_wr: in std_logic;
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pavr_rf_wr_di: in std_logic_vector(7 downto 0);
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-- Pointer registers
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pavr_rf_x: out std_logic_vector(15 downto 0);
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pavr_rf_x_wr: in std_logic;
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pavr_rf_x_di: in std_logic_vector(15 downto 0);
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pavr_rf_y: out std_logic_vector(15 downto 0);
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pavr_rf_y_wr: in std_logic;
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pavr_rf_y_di: in std_logic_vector(15 downto 0);
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pavr_rf_z: out std_logic_vector(15 downto 0);
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pavr_rf_z_wr: in std_logic;
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pavr_rf_z_di: in std_logic_vector(15 downto 0)
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);
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end component;
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for all: pavr_rf use entity work.pavr_rf(pavr_rf_arch);
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begin
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-- Instantiate a the Register File.
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pavr_rf_instance1: pavr_rf
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port map(
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clk,
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res,
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syncres,
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-- Read port #1
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pavr_rf_rd1_addr,
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pavr_rf_rd1_rd,
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pavr_rf_rd1_do,
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-- Read port #2
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pavr_rf_rd2_addr,
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pavr_rf_rd2_rd,
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pavr_rf_rd2_do,
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-- Write port
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pavr_rf_wr_addr,
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pavr_rf_wr_wr,
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pavr_rf_wr_di,
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-- Pointer registers
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pavr_rf_x,
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pavr_rf_x_wr,
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pavr_rf_x_di,
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pavr_rf_y,
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pavr_rf_y_wr,
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pavr_rf_y_di,
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pavr_rf_z,
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pavr_rf_z_wr,
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pavr_rf_z_di
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);
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generate_clock:
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process
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begin
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clk <= '1';
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wait for 50 ns;
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clk <= '0';
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wait for 50 ns;
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end process generate_clock;
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generate_reset:
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process
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begin
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res <= '0';
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wait for 100 ns;
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res <= '1';
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wait for 110 ns;
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res <= '0';
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wait for 1 ms;
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end process generate_reset;
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generate_sync_reset:
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process
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begin
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syncres <= '0';
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wait for 300 ns;
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syncres <= '1';
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wait for 110 ns;
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syncres <= '0';
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wait for 1 ms;
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end process generate_sync_reset;
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test_main:
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process(clk, res, syncres,
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cnt,
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pavr_rf_rd1_addr,
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pavr_rf_rd2_addr,
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pavr_rf_wr_addr, pavr_rf_wr_di,
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pavr_rf_x_di,
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pavr_rf_y_di,
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pavr_rf_z_di
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)
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begin
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if res='1' then
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-- Async reset
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-- The Register File should take care of reseting its registers. Check
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-- this too.
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cnt <= int_to_std_logic_vector(0, cnt'length);
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elsif clk'event and clk='1' then
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-- Clock counter
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cnt <= cnt+1;
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-- Initialize inputs.
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pavr_rf_rd1_addr <= int_to_std_logic_vector(3, pavr_rf_rd1_addr'length);
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pavr_rf_rd1_rd <= '0';
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pavr_rf_rd2_addr <= int_to_std_logic_vector(4, pavr_rf_rd2_addr'length);
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pavr_rf_rd2_rd <= '0';
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pavr_rf_wr_addr <= int_to_std_logic_vector(5, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '0';
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pavr_rf_wr_di <= int_to_std_logic_vector(6, pavr_rf_wr_di'length);
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pavr_rf_x_wr <= '0';
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pavr_rf_x_di <= int_to_std_logic_vector(7, pavr_rf_x_di'length);
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pavr_rf_y_wr <= '0';
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pavr_rf_y_di <= int_to_std_logic_vector(8, pavr_rf_y_di'length);
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pavr_rf_z_wr <= '0';
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pavr_rf_z_di <= int_to_std_logic_vector(9, pavr_rf_z_di'length);
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case std_logic_vector_to_nat(cnt) is
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-- TEST 1
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-- Test RFWR, RFRD1 and RFRD1, one port at a time. Access RF registers
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-- others than pointer registers.
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-- RFWR
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when 5 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(50, pavr_rf_wr_di'length);
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-- RFWR
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when 6 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(11, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(51, pavr_rf_wr_di'length);
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-- RFRD1
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when 7 =>
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pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
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pavr_rf_rd1_rd <= '1';
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-- RFRD2
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when 8 =>
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pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
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pavr_rf_rd2_rd <= '1';
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-- TEST 2
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-- Test RFWR, RFRD1 and RFRD1, one port at a time. Access RF pointer
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-- registers.
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-- RFWR
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when 12 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(26, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(60, pavr_rf_wr_di'length);
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when 13 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(27, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(61, pavr_rf_wr_di'length);
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when 14 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(28, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(62, pavr_rf_wr_di'length);
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when 15 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(29, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(63, pavr_rf_wr_di'length);
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when 16 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(30, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(64, pavr_rf_wr_di'length);
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when 17 =>
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pavr_rf_wr_addr <= int_to_std_logic_vector(31, pavr_rf_wr_addr'length);
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pavr_rf_wr_wr <= '1';
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pavr_rf_wr_di <= int_to_std_logic_vector(65, pavr_rf_wr_di'length);
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-- RFRD1
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when 18 =>
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pavr_rf_rd1_addr <= int_to_std_logic_vector(26, pavr_rf_rd1_addr'length);
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pavr_rf_rd1_rd <= '1';
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-- RFRD2
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when 19 =>
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pavr_rf_rd2_addr <= int_to_std_logic_vector(27, pavr_rf_rd2_addr'length);
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pavr_rf_rd2_rd <= '1';
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-- RFRD1
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when 20 =>
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pavr_rf_rd1_addr <= int_to_std_logic_vector(28, pavr_rf_rd1_addr'length);
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pavr_rf_rd1_rd <= '1';
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-- RFRD1
|
326 |
|
|
when 21 =>
|
327 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(29, pavr_rf_rd1_addr'length);
|
328 |
|
|
pavr_rf_rd1_rd <= '1';
|
329 |
|
|
-- RFRD2
|
330 |
|
|
when 22 =>
|
331 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(30, pavr_rf_rd2_addr'length);
|
332 |
|
|
pavr_rf_rd2_rd <= '1';
|
333 |
|
|
-- RFRD2
|
334 |
|
|
when 23 =>
|
335 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
|
336 |
|
|
pavr_rf_rd2_rd <= '1';
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
-- TEST 3
|
341 |
|
|
-- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF registers
|
342 |
|
|
-- others than pointer registers.
|
343 |
|
|
-- Note: RFWR and RFRD1 access the same location.
|
344 |
|
|
when 26 =>
|
345 |
|
|
pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
|
346 |
|
|
pavr_rf_wr_wr <= '1';
|
347 |
|
|
pavr_rf_wr_di <= int_to_std_logic_vector(70, pavr_rf_wr_di'length);
|
348 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
|
349 |
|
|
pavr_rf_rd1_rd <= '1';
|
350 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
|
351 |
|
|
pavr_rf_rd2_rd <= '1';
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
-- TEST 4
|
356 |
|
|
-- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF pointer
|
357 |
|
|
-- registers.
|
358 |
|
|
-- Note: RFWR, RFRD1 and RFRD2 access the same location.
|
359 |
|
|
when 29 =>
|
360 |
|
|
pavr_rf_wr_addr <= int_to_std_logic_vector(26, pavr_rf_wr_addr'length);
|
361 |
|
|
pavr_rf_wr_wr <= '1';
|
362 |
|
|
pavr_rf_wr_di <= int_to_std_logic_vector(80, pavr_rf_wr_di'length);
|
363 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(26, pavr_rf_rd1_addr'length);
|
364 |
|
|
pavr_rf_rd1_rd <= '1';
|
365 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(26, pavr_rf_rd2_addr'length);
|
366 |
|
|
pavr_rf_rd2_rd <= '1';
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
-- TEST 5
|
371 |
|
|
-- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF pointer
|
372 |
|
|
-- registers.
|
373 |
|
|
-- Note: RFWR, RFRD1 and RFRD2 each access a different location.
|
374 |
|
|
-- RFWR
|
375 |
|
|
when 32 =>
|
376 |
|
|
pavr_rf_wr_addr <= int_to_std_logic_vector(27, pavr_rf_wr_addr'length);
|
377 |
|
|
pavr_rf_wr_wr <= '1';
|
378 |
|
|
pavr_rf_wr_di <= int_to_std_logic_vector(90, pavr_rf_wr_di'length);
|
379 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(28, pavr_rf_rd1_addr'length);
|
380 |
|
|
pavr_rf_rd1_rd <= '1';
|
381 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
|
382 |
|
|
pavr_rf_rd2_rd <= '1';
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
-- TEST 6
|
387 |
|
|
-- Test pointer register write ports.
|
388 |
|
|
when 35 =>
|
389 |
|
|
pavr_rf_x_wr <= '1';
|
390 |
|
|
pavr_rf_x_di <= int_to_std_logic_vector(16#1111#, pavr_rf_x_di'length);
|
391 |
|
|
pavr_rf_y_wr <= '1';
|
392 |
|
|
pavr_rf_y_di <= int_to_std_logic_vector(16#2222#, pavr_rf_y_di'length);
|
393 |
|
|
pavr_rf_z_wr <= '1';
|
394 |
|
|
pavr_rf_z_di <= int_to_std_logic_vector(16#3333#, pavr_rf_z_di'length);
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
-- TEST 7
|
399 |
|
|
-- Test RFWR, RFRD1, RFRD2 and pointer register write ports, all at
|
400 |
|
|
-- the same time. No writes compete for the same location.
|
401 |
|
|
when 38 =>
|
402 |
|
|
pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
|
403 |
|
|
pavr_rf_wr_wr <= '1';
|
404 |
|
|
pavr_rf_wr_di <= int_to_std_logic_vector(110, pavr_rf_wr_di'length);
|
405 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
|
406 |
|
|
pavr_rf_rd1_rd <= '1';
|
407 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
|
408 |
|
|
pavr_rf_rd2_rd <= '1';
|
409 |
|
|
pavr_rf_x_wr <= '1';
|
410 |
|
|
pavr_rf_x_di <= int_to_std_logic_vector(111, pavr_rf_x_di'length);
|
411 |
|
|
pavr_rf_y_wr <= '1';
|
412 |
|
|
pavr_rf_y_di <= int_to_std_logic_vector(112, pavr_rf_y_di'length);
|
413 |
|
|
pavr_rf_z_wr <= '1';
|
414 |
|
|
pavr_rf_z_di <= int_to_std_logic_vector(113, pavr_rf_z_di'length);
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
|
418 |
|
|
-- TEST 8
|
419 |
|
|
-- Test RFWR, RFRD1, RFRD2 and pointer register write ports, all at
|
420 |
|
|
-- the same time. RFWR and RFZWR try to write the same location.
|
421 |
|
|
-- RFZWR should win.
|
422 |
|
|
when 41 =>
|
423 |
|
|
pavr_rf_wr_addr <= int_to_std_logic_vector(31, pavr_rf_wr_addr'length);
|
424 |
|
|
pavr_rf_wr_wr <= '1';
|
425 |
|
|
pavr_rf_wr_di <= int_to_std_logic_vector(120, pavr_rf_wr_di'length);
|
426 |
|
|
pavr_rf_rd1_addr <= int_to_std_logic_vector(30, pavr_rf_rd1_addr'length);
|
427 |
|
|
pavr_rf_rd1_rd <= '1';
|
428 |
|
|
pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
|
429 |
|
|
pavr_rf_rd2_rd <= '1';
|
430 |
|
|
pavr_rf_x_wr <= '1';
|
431 |
|
|
pavr_rf_x_di <= int_to_std_logic_vector(121, pavr_rf_x_di'length);
|
432 |
|
|
pavr_rf_y_wr <= '1';
|
433 |
|
|
pavr_rf_y_di <= int_to_std_logic_vector(122, pavr_rf_y_di'length);
|
434 |
|
|
pavr_rf_z_wr <= '1';
|
435 |
|
|
pavr_rf_z_di <= int_to_std_logic_vector(123, pavr_rf_z_di'length);
|
436 |
|
|
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
when others =>
|
440 |
|
|
null;
|
441 |
|
|
end case;
|
442 |
|
|
|
443 |
|
|
if syncres='1' then
|
444 |
|
|
-- Sync reset
|
445 |
|
|
-- The Register File should take care of reseting its registers. Check
|
446 |
|
|
-- this too.
|
447 |
|
|
cnt <= int_to_std_logic_vector(0, cnt'length);
|
448 |
|
|
end if;
|
449 |
|
|
end if;
|
450 |
|
|
end process test_main;
|
451 |
|
|
|
452 |
|
|
|
453 |
|
|
end;
|
454 |
|
|
-- </File body>
|